index [mist.ac.in]mist.ac.in/pdfs/labmanuals/ece/hdlsimulationlabmanual.pdf3. design of 8-to-3...
TRANSCRIPT
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 1
INDEX
1. Introduction 2. List of experiments 3. General guidelines for conducting an experiment
3.1 Simulation 3.1.1 Creating a project 3.1.2 VHDL design entry 3.1.3 VERILOG design entry 3.1.4 Functional verification
3.2 Implementation 3.2.1 Creating timing constraints 3.2.2 Verification of constraints 3.2.3 Assigning pin location constraints 3.2.4 Downloading design to Spartan-3 demo kit
3.3 Do’s and Don’ts
4. Experiments 4.1 HDL code to realize all the logic gates
4.1.1 AIM 4.1.2 VHDL simulation 4.1.3 VERILOG simulation 4.1.4 Design implementation
4.2 Design of 2 – to – 4 decoder 4.2.1 AIM 4.2.2 VHDL simulation 4.2.3 VERILOG simulation 4.2.4 Design implementation
4.3 Design of 8-to-3 encoder (with Priority and without priority) 4.3.1 Aim 4.3.2 VHDL simulation 4.3.3 VERILOG simulation 4.3.4 Design implementation
4.4 Design of 8-to-1 multiplexer and 1-to-8 de-multiplexer 4.4.1 Aim 4.4.2 VHDL simulation 4.4.3 VERILOG simulation 4.4.4 Design implementation
4.5 Design of 4 bit binary to gray code converter 4.5.1 Aim 4.5.2 VHDL simulation 4.5.3 VERILOG simulation 4.5.4 Design implementation
4.6 Design of 4 bit comparator 4.6.1 Aim 4.6.2 VHDL simulation 4.6.3 VERILOG simulation 4.6.4 Design implementation
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 2
4.7 Design of full adder using 3 modeling styles 4.7.1 Aim 4.7.2 VHDL simulation 4.7.3 VERILOG simulation 4.7.4 Design implementation
4.8 Design of flip flops: RS, D, JK, T 4.8.1 Aim 4.8.2 VHDL simulation 4.8.3 VERILOG simulation 4.8.4 Design implementation
4.9 Design of 4 bit binary, BCD converter (Synchronous/ asynchronous) 4.9.1 Aim 4.9.2 VHDL simulation 4.9.3 VERILOG simulation 4.9.4 Design implementation
4.10 Finite state machine design
4.10.1 Aim 4.10.2 VHDL simulation 4.10.3 VERILOG simulation 4.10.4 Design implementation
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 3
1.Introduction
HDL simulation lab is for B.Tech III ,I- semester. It is a part of IC Applications and HDL
simulation lab (code : A50488, Part-II ). Students learn the theory subject (DDVHDL) in II
year II semester. This lab experiments are meant to give hands on experience to the students
on the subject, DDVHDL. HDL is meant for designing, testing, debugging and prototyping
simple to complex digital circuits. HDL is having two languages namely, VHDL and
VERILOG.
There are ten experiments in this lab. All the experiments are provided with VHDL and
VERILOG codes and the procedure to prototype on FPGA according to JNTUH R-13
syllabus, out of which at least seven experiments have to be performed.
The list of experiments is given in section -2. Section-3 deals with general guidelines to
conduct an experiment. The VHDL, VERILOG program codes of each experiment along
with the expected waveforms and procedure to prototype on FPGA is provided in section – 4.
2. List of Experiments
1. HDL code to realize all the logic gates.
2. Design of 2-to-4 decoder
3. Design of 8-to-3 encoder (without and with parity)
4. Design of 8-to-1 multiplexer and 1-to-8 de-multiplexer
5. Design of 4 bit binary to gray code converter
6. Design of 4 bit comparator
7. Design of full adder using 3 modeling styles
8. Design of flip flops: SR, D, JK, T
9. Design of 4 bit binary, BCD counters (Synchronous/ asynchronous reset)
10. Finite state machine design
Additional experiments beyond the syllabus
1. Ripple carry adder 2. Modeling of shift registers
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 4
3.0 General guidelines and procedures to conduct an experiment
Each experiment has to be first simulated using XILINX, both with VHDL and VERILOG.
Then the circuit has to be tested using a test bench in simulation level. After simulation is
over, the circuit has to be implemented on FPGA Spartan -3 startup kit.
Each experiment will have to follow the following steps:
- Design description/Design entry (Design is described in various levels of abstraction)
- Functional verification (functionality of the design is tested by test benches) - Synthesis (converting the design description in to gate level netlist) - Implementation (The synthesized circuit is mapped on to FPGA via proper
interface and programming)
3.1 Simulation 3.1.1 Creating a new project
Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 5
Figure 2: Project Device Properties
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.
Create an HDL Source In this section, you will create the top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the “Creating a
VHDL Source” section below, or skip to the “Creating a Verilog Source” section.
3.1.2 VHDL design entry
Creating a VHDL Source Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type. 3. Type in the file name counter. 4. Verify that the Add to project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shown
below:
7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template.
8. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below:
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 6
Figure 3:
7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template.
8. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below:
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 7
Using Language Templates (VHDL) The next step in creating the new source is to add the behavioral description for the
counter. To do this you will use a simple counter code example from the ISE Language
Templates and customize it for the counter design.
1. Place the cursor just below the begin statement within the counter architecture.
2. Open the Language Templates by selecting Edit → Language Templates…
Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.
3. Using the “+” symbol, browse to the following code example:
VHDL → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in
File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.
Final Editing of the VHDL Source 1. Add the following signal declaration to handle the feedback of the counter output
below the architecture declaration and above the first begin statement: signal count_int : std_logic_vector(3 downto 0) := "0000";
2. Customize the source file for the counter design by replacing the port and signal name placeholders with the actual ones as follows:
♦ replace all occurrences of with CLOCK
♦ replace all occurrences of with DIRECTION
♦ replace all occurrences of with count_int
3. Add the following line below the end process; statement: COUNT_OUT
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 8
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitive in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 9
7. Click Next, then Finish in the New Source Information dialog box to complete the new source file template.
8. Click Next, then Next, then Finish. The source file containing the counter module displays in the Workspace, and the counter
displays in the Sources tab, as shown below:
Using Language Templates (Verilog) The next step in creating the new source is to add the behavioral description for counter.
Use a simple counter code example from the ISE Language Templates and customize it for
the counter design.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 10
1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
2. Open the Language Templates by selecting Edit → Language Templates…
Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.
3. Using the “+” symbol, browse to the following code example:
Verilog → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in
File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.
Final Editing of the Verilog Source 1. To declare and initialize the register that stores the counter value, modify the
declaration statement in the first line of the template as follows:
replace: reg [:0] ;
with: reg [3:0] count_int = 0;
2. Customize the template for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
♦ replace all occurrences of with CLOCK
♦ replace all occurrences of with DIRECTION
♦ replace all occurrences of with count_int
3. Add the following line just above the endmodule statement to assign the register value
to the output port: assign COUNT_OUT = count_int;
4. Save the file by selecting File → Save.
When you are finished, the code for the counter will look like the following: module counter(CLOCK, DIRECTION, COUNT_OUT);
input CLOCK;
input DIRECTION;
output [3:0] COUNT_OUT;
);
reg [3:0] count_int = 0;
always @(posedge CLOCK)
if (DIRECTION)
count_int
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 11
Design Simulation Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type counter_tbw in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform
with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays
the source directory, type, and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.
The requirements for this design are the following:
♦ The counter must operate correctly with an input clock frequency = 25 MHz.
♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.
The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information:
♦ Clock High Time: 20 ns.
♦ Clock Low Time: 20 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
♦ Global Signals: GSR (FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
♦ Initial Length of Test Bench: 1500 ns.
Leave the default values in the remaining fields.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 12
Figure 7: Initialize Timing
8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the
Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to
define the input stimulus for the counter design as follows:
♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so
that the counter will count up.
♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION low so
that the counter will count down.
Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons
Figure 8: Test Bench Waveform 10. Save the waveform.
11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 13
Figure 9: Behavior Simulation Selection
Simulating Design Functionality Verify that the counter design functions as you expect by performing behavior simulation
as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window.
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the transitions.
The simulation waveform results will look like the following:
Figure 10: Simulation Results
Note: You can ignore any rows that start with TX. 4. Verify that the counter is counting up and down as expected.
5. Close the simulation view. If you are prompted with the following message, “You have
an active simulation open. Are you sure you want to close it?“, click Yes to continue. You have now completed simulation of your design using the ISE Simulator.
3.2 Design Implementation The design implementation is having the following steps.
- Creating timing constraints - Verifying constraints - Assigning pin location constraints - Downloading design to Spartan-3 demo kit 3.2.1 Creating timing constraints
Create Timing Constraints Specify the timing between the FPGA and its surrounding logic as well as the frequency
the design must operate at internal to the FPGA. The timing is specified by entering
constraints that guide the placement and routing of the design. It is recommended that you
enter global constraints. The clock period constraint specifies the clock frequency at which
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 14
your design must operate inside the FPGA. The offset constraints specify when to expect
valid data at the FPGA inputs and when valid data will be available at the FPGA outputs.
Entering Timing Constraints To constrain the design do the following:
1. Select Implementation from the drop-down list in the Sources window. 2. Select the counter HDL source file. 3. Click the “+” sign next to the User Constraints processes group, and double-click the Create Timing Constraints process. ISE runs the Synthesis and Translate steps and automatically creates a User
Constraints File (UCF). You will be prompted with the following message:
Figure 11: Prompt to Add UCF File to Project
4. Click Yes to add the UCF file to your project.
The counter.ucf file is added to your project and is visible in the Sources window.
The Xilinx Constraints Editor opens automatically.
Note: You can also create a UCF file for your project by selecting Project → Create New
Source.
5. In the Timing Constraints dialog, enter the following in the Period, Pad to Setup, and
CLock to Pad fields:
♦ Period: 40
♦ Pade to Setup: 10
♦ Clock to Pad: 10
6. Press Enter. After the information has been entered, the dialog should look like what is shown
below..
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 15
Figure 12: Creating Timing Constraints 7. Select Timing Constraints under Constraint Type in the Timing Constraints tab and
the newly created timing constraints are displayed as follows:
Figure 13: Timing Constraints 8. Save the timing constraints. If you are prompted to rerun the TRANSLATE or XST
step, click OK to continue. 9. Close the Constraints Editor.
3.2.2 Verification of constraints
Implement Design and Verify Constraints Implement the design and verify that it meets the timing constraints specified in the
previous section.
Implementing the Design 1. Select the counter source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary process in the Processes tab.
3. Double-click the Implement Design process in the Processes tab. 4. Notice that after Implementation is complete, the Implementation processes have a
green check mark next to them indicating that they completed successfully without
Errors or Warnings.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 16
Figure 14: Post Implementation Design Summary
6. Locate the Performance Summary table near the bottom of the Design Summary. 7. Click the All Constraints Met link in the Timing Constraints field to view the Timing
Constraints report. Verify that the design meets the specified timing requirements
Figure 15: All Constraints Met Report
8. Close the Design Summary.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 17
3.2.3 Assigning Pin location constraints
Assigning Pin Location Constraints Specify the pin locations for the ports of the design so that they are connected correctly on
the Spartan-3 Startup Kit demo board.
To constrain the design ports to package pins, do the following:
1. Verify that counter is selected in the Sources window. 2. Double-click the Floorplan Area/IO/Logic - Post Synthesis process found in the User Constraints process group. The Xilinx Pinout and Area Constraints Editor
(PACE) opens.
3. Select the Package View tab. 4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following information:
♦ CLOCK input port connects to FPGA pin T9 (GCK0 signal on board)
♦ COUNT_OUT output port connects to FPGA pin K12 (LD0 signal on board)
♦ COUNT_OUT output port connects to FPGA pin P14 (LD1 signal on board)
♦ COUNT_OUT output port connects to FPGA pin L12 (LD2 signal on board)
♦ COUNT_OUT output port connects to FPGA pin N14 (LD3 signal on board)
♦ DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)
Notice that the assigned pin locations are shown in blue:
Figure 16: Package Pin Locations
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 18
5. Select File → Save. You are prompted to select the bus delimiter type based on the
synthesis tool you are using. Select XST Default and click OK. 6. Close PACE.
Notice that the Implement Design processes have an orange question mark next to them,
indicating they are out-of-date with one or more of the design files. This is because the UCF
file has been modified.
Reimplement Design and Verify Pin Locations Reimplement the design and verify that the ports of the counter design are routed to the
package pins specified in the previous section.
First, review the Pinout Report from the previous implementation by doing the following:
1. Open the Design Summary by double-clicking the View Design Summary process in the Processes window.
2. Select the Pinout Report and select the Signal Name column header to sort the signal names. Notice the Pin Numbers assigned to the design ports in the absence of location
constraints.
Figure 17: Package Pin Locations Prior to Pin Location Constraints
3. Reimplement the design by double-clicking the Implement Design process. 4. Select the Pinout Report again and select the Signal Name column header to sort the signal names.
5. Verify that signals are now being routed to the correct package pins.
Figure 18: Package Pin Locations After Pin Location Constraints
6. Close the Design Summary.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 19
3.2.4 Downloading design to Spartan-3 demo kit
Download Design to the Spartan™-3 Demo Board This is the last step in the design verification process. This section provides simple
instructions for downloading the counter design to the Spartan-3 Starter Kit demo board.
1. Connect the 5V DC power cable to the power input on the demo board (J4).
2. Connect the download cable between the PC and demo board (J7).
3. Select Implementation from the drop-down list in the Sources window. 4. Select counter in the Sources window. 5. In the Process window, double-click the Configure Target Device process. 6. The Xilinx WebTalk Dialog box may open during this process. Click Decline. iMPACT opens and the Configure Devices dialog box is displayed.
Figure 19: iMPACT Welcome Dialog Box
7. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). 8. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected.
9. Click Finish. 10. If you get a message saying that there are two devices found, click OK to continue. The devices connected to the JTAG chain on the board will be detected and displayed
in the iMPACT window.
11. The Assign New Configuration File dialog box appears. To assign a configuration file
to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 20
Figure 20: Assign New Configuration File
12. If you get a Warning message, click OK. 13. Select Bypass to skip any remaining devices. 14. Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens. 15. Click OK to program the device. When programming is complete, the Program Succeeded message is displayed.
On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.
16. Close iMPACT without saving.
You have completed the ISE Quick Start Tutorial. For an in-depth explanation of the ISE
design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 21
3.3 Do’s and Don’ts The students are to follow the given general Do’s and Don’ts for simulation lab.
Do’s:
1. Enter in to the simulation lab in time. 2. Wear student identity badges round your neck before entering the lab. 3. Keep silence in the lab 4. Follow the instructions of the lab in-charges and lab supervisor. 5. Always save your input files and results in the prescribed directory. Don’ts:
1. Do not use internet or open any other programs other than MATLAB. 2. Do not mishandle or rough handle the keyboard of CPU. 3. Do not use pen drive or card reader without the permission of the lab in-charge. 4. Do not make noise in the lab.
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 22
4.0 EXPERIMENTS
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 23
Experiment No:1
4.1 HDL Code to realize all the logic gates
4.1.1 Aim: To Design Logic Gates using VHDL and simulate the same using
Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE
4.1.2 VHDL simulation
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logic_gates is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
AND1 : out STD_LOGIC;
OR1 : out STD_LOGIC;
NOT1 : out STD_LOGIC;
XOR1 : out STD_LOGIC;
NAND1 : out STD_LOGIC;
NOR1 : out STD_LOGIC;
XNOR1 : out STD_LOGIC);
end logic_gates;
architecture Behavioral of logic_gates is
begin
AND1
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 24
end Behavioral;
Synthesis Report
A) Final Report:
Final Results
RTL Top Level Output File Name : logic_gates.ngr
Top Level Output File Name : logic_gates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
B) Design Statistics
# IOs : 9
Cell Usage :
# BELS : 7
# INV : 1
# LUT2 : 6
# IO Buffers : 9
# IBUF : 2
# OBUF : 7
=====================================================================
====
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 4 out of 2448 0%
Number of 4 input LUTs: 7 out of 4896 0%
Number of IOs: 9
Number of bonded IOBs: 9 out of 172 5%
C) TIMING REPORT: Delay: 5.998ns (Levels of Logic = 3)
Source: A (PAD) Destination: NOR1 (PAD)
Data Path: A to NOR1
Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 1.106 0.754 A_IBUF (A_IBUF)
LUT2:I0->O 1 0.612 0.357 OR11 (OR1_OBUF) OBUF:I->O 3.169 OR1_OBUF (OR1)
----------------------------------------
Total 5.998ns
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 25
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_logic_gates_vhd IS
END tb_logic_gates_vhd;
ARCHITECTURE behavior OF tb_logic_gates_vhd IS
COMPONENT logic_gates
PORT(
A : IN std_logic;
B : IN std_logic;
AND1 : OUT std_logic;
OR1 : OUT std_logic;
NOT1 : OUT std_logic;
XOR1 : OUT std_logic;
NAND1 : OUT std_logic;
NOR1 : OUT std_logic;
XNOR1 : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL AND1 : std_logic;
SIGNAL OR1 : std_logic;
SIGNAL NOT1 : std_logic;
SIGNAL XOR1 : std_logic;
SIGNAL NAND1 : std_logic;
SIGNAL NOR1 : std_logic;
SIGNAL XNOR1 : std_logic;
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 26
BEGIN
uut: logic_gates PORT MAP(
A => A,
B => B,
AND1 => AND1,
OR1 => OR1,
NOT1 => NOT1,
XOR1 => XOR1,
NAND1 => NAND1,
NOR1 => NOR1,
XNOR1 => XNOR1
);
A
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 27
7408N TRUTH TABLE:
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is
port( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC
); end
AND2;
--Dataflow model
architecture behav1 of AND2 is
begin
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 28
end process;
end behav2;
OUTPUT WAVEFORM:
#2-TITLE: OR gate
LOGIC GATE SYMBOL:
X 7432
Z Y
TRUTH TABLE:
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is
port( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC
);
end OR2;
x y z
0 0 0
0 1 1
1 0 1
1 1 1
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 29
--Dataflow model architecture
behav1 of OR2 is begin
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 30
entity not1 is
port(
X: in STD_LOGIC; Z:
out STD_LOGIC ); end
not1;
--Dataflow model
architecture behav1 of not1 is
begin
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 31
LOGIC GATE SYMBOL: X Z Y
7400 TRUTH TABLE:
x y z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL CODE:
Library IEEE;
use IEEE.std_logic_1164.all;
entity nand2 is
port(
x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC
); end
nand2; --Dataflow model
architecture behav1 of nand2 is
begin
z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 32
else
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 33
entity nor2 is Port
( X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC
);
end nor2;
--Dataflow model
architecture behav1 of nor2 is
begin
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 34
LOGIC GATE SYMBOL: X Z Y
7486
Library IEEE;
use IEEE.std_logic_1164.all;
entity xor2 is Port
( X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC
);
end xor2;
--Dataflow model
architecture behav1 of xor2 is
begin
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 35
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 36
entity xnor2 is
Port ( X: in STD_LOGIC; Y: in STD_LOGIC; Z: out STD_LOGIC
); end
xnor2; --Dataflow model
architecture behav1 of xnor2 is
begin
Z
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 37
4.1.3 Verilog simulation
// Design description for all the basic gates
module allgates(not1,or2,and3,nor4,nand5,xor6,xnor7,A,B);
input A, B;
output not1,or2,and3,nor4,nand5,xor6,xnor7;
reg not1,or2,and3,nor4,nand5,xor6,xnor7;
always@(Aor B)
begin
not1 = ~A;
or2 = A|B;
and3 = A&B;
nor4 = ~(A|B);
nand5 = ~(A&B);
xor6 = (A^B);
xnor7 = ~(A^B);
end
endmodule
// Test bench for all gates
module allgatestest;
reg a,b;
allgates gg(not1,or2,and3,nor4,nand5,xor6,xnor7,a,b); //instatiation of module allgates
always
begin
a = 1’b0, b=1’b0;
#3 a=1’b1,b=1’b0;
#3 a=1’b1,b=1’b1;
#3 a=1’b0,b=1’b1;
#3 a=1’b0,b=1’b0;
#3 a=1’b1,b=1’b1;
end
initial
$minotor($time, “a=%b, b=%b, not1 = %b,
or2=%b,and3=%b,nor4=%b,nand5=%b,xor6=%b,xnor7=%b”,
a,b,not1,or2,and3,nor4,nand5,xor6,xnor7);
Initial #24 $stop;
endmodule
4.1.4 Implementation:
Implementation can be done on Spartan-3 FPGA kit as described in section -3
Result:
Logic Gates are designed using VHDL , VERILOG and simulated the same using Xilinx ISE Simulator
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 38
Experiment No:2
4.2 Design of 2-to-4 decoder
4.2.1 Aim: To Design 2-To-4 decoder using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE
4.2.3 VHDL simulation
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
process(En,I)
begin
if En='0' then YYYYYY
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 39
end Behavioral;
Synthesis Report
Final Report:
Final Results RTL Top Level Output File Name : decoder.ngr Top Level Output File Name : decoder Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 7 Cell Usage : # BELS : 4 # LUT3 : 4 # IO Buffers : 7
# IBUF : 3
# OBUF : 4
=========================================================================
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 2 out of 2448 0%
Number of 4 input LUTs: 4 out of 4896 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 172 4%
TIMING REPORT:
Delay: 5.895ns (Levels of Logic = 3) Source: I (PAD) Destination: Y (PAD) Data Path: I to Y Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 4 1.106 0.651 I_1_IBUF (I_1_IBUF) LUT3:I0->O 1 0.612 0.357 Y1 (Y_3_OBUF) OBUF:I->O 3.169 Y_3_OBUF (Y) ---------------------------------------- Total 5.895ns
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 40
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_decoder_vhd IS
END tb_decoder_vhd;
ARCHITECTURE behavior OF tb_decoder_vhd IS
COMPONENT decoder
PORT(
En : IN std_logic;
I : IN std_logic_vector(1 downto 0);
Y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL En : std_logic := '0';
SIGNAL I : std_logic_vector(1 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(3 downto 0);
BEGIN
uut: decoder PORT MAP(
En => En,
I => I,
Y => Y
);
En
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 41
Simulation Results:
Schematic Diagram:
3x8 DECODER AIM: Write a VHDL code for IC74138 -3X8 Decoder
TITLE: IC74138—3x8 Decoder.
BLOCK DIAGRAM:
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 42
TRUTH TABLE:
S.No Enable inputs Encoded inputs Decoded
g1 g2a_l g2b_l A B C output
1 0 X X X X X 11111111
2 1 1 X X X X 11111111
3 1 X 1 X X X 11111111
4 1 0 0 0 0 0 01111111
5 1 0 0 0 0 1 10111111
6 1 0 0 0 1 0 11011111
7 1 0 0 0 1 1 11101111
8 1 0 0 1 0 0 11110111
9 1 0 0 1 0 1 11111011
10 1 0 0 1 1 0 11111101
11 1 0 0 1 1 1 11111110
VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder3X8 is
port ( g1 : in STD_LOGIC; --g1, g2a_l, g2b_l cascade i/ps g2a_l
: in STD_LOGIC; g2b_l : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0); y_l : out
STD_LOGIC_VECTOR (0 to 7) );
end decoder3X8;
architecture deco38 of decoder3X8 is
begin
process (a,g1,g2a_l,g2b_l)
begin
if (g1 and not g2a_l and not g2b_l)='1'then if a
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 43
WAVEFORMS
Result: 2-To-4 Decoder is designed using VHDL and simulated the same using Xilinx ISE Simulator
4.2.3 Verilog simulation
// Code for 2-4 decoder simulation
module decoder(data,code);
output [3:0] data;
input [1:0] code;
reg [3:0] data;
always @ (code)
begin
if (code ==0) data = 4’b0001; else
if(code ==1) data = 4’b0010; else
if(code==2) data=4’b0100; else
data = 4’b1000;
end
/* Alternate description is
always @ (code)
case(code)
0 : data=4’b0001;
1 : data=4’b0010;
2 : data=4’b0100;
3 : data=4’b1000;
Endcase
*/
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 44
Endmodule
//Test bench for 2-4 decoder
module decodertest;
reg [1:0]code;
decoder gg(data, code); // Instatiation of decoder block
always
begin
code = 2’b00;
#3 code = 2’b01;
#3 code=2’b10;
#3 code=2’b11;
end
$monitor($time, “code=%b, data = %b”,code,data);
Initial #24 $stop
endmodule
-----------------X-------------X---------------X-----------------X----------------X---------------
4.2.4 Implementation:
The decoder can be implemented on Spartan-3 FPGA kit as described in
section-3.
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 45
Experiment No:3
4.3 Design of 8-to-3 encoder (without and with priority)
4.3.1 Aim: To Design 8-To-3 Encoder with and without Priority using VHDL and
simulate the same using Xilinx ISE Simulator.
Tools Required: 1.PC
2. Xilinx ISE
4.3.2 VHDL simulation
(A)Design of 8-to-3 encoder (without priority)
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_without_priority is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder_without_priority;
architecture Behavioral of encoder_without_priority is
begin
process(En,I)
begin
if En='0' then YYYYYYYYY
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 46
when others=>Y
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 47
END COMPONENT;
SIGNAL En : std_logic := '0';
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(2 downto 0);
BEGIN
uut: encoder_without_priority PORT MAP(
En => En,
I => I,
Y => Y
);
En
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 48
Number of Slices: 9 out of 2448 0% Number of 4 input LUTs: 15 out of 4896 0% Number of IOs: 12 Number of bonded IOBs: 12 out of 172 6% TIMING REPORT: Delay: 9.315ns (Levels of Logic = 6) Source: I (PAD) Destination: Y (PAD) Data Path: I to Y Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 4 1.106 0.651 I_0_IBUF (I_0_IBUF) LUT3:I0->O 2 0.612 0.532 Y_mux000041 (Y_mux0000_bdd4) LUT3:I0->O 2 0.612 0.449 Y_not0001_inv21 (Y_not0001_inv_bdd3) LUT4:I1->O 1 0.612 0.509 Y_not0001_inv59 (Y_not0001_inv_map17) LUT4:I0->O 3 0.612 0.451 Y_not0001_inv93 (Y_not0001_inv) OBUFT:T->O 3.169 Y_2_OBUFT (Y) ----------------------------------------
Total 9.315ns
Result: 8-To-3 Encoder without Priority is designed using VHDL and simulated the same using Xilinx ISE Simulator
(B) Design of 8-to-3 encoder (with priority)
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Encoder_with_priority is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end Encoder_with_priority;
architecture Behavioral of Encoder_with_priority is
begin
process(En,I)
begin
if En='0' then Y
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 49
elsif I(4)='1' then Y
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 50
Y : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
SIGNAL En : std_logic := '0';
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(2 downto 0);
BEGIN
uut: encoder_with_priority PORT MAP(
En => En,
I => I,
Y => Y
);
En
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 51
Device utilization summary: Selected Device : 3s250eft256-5 Number of Slices: 3 out of 2448 0% Number of 4 input LUTs: 6 out of 4896 0% Number of IOs: 12 Number of bonded IOBs: 11 out of 172 6% TIMING REPORT: Delay: 6.846ns (Levels of Logic = 4) Source: I (PAD) Destination: Y (PAD)
Data Path: I to Y Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- - ----------------------------------- IBUF:I->O 3 1.106 0.603 I_5_IBUF (I_5_IBUF) LUT4:I0->O 1 0.612 0.387 Y_SW0 (N8) LUT4:I2->O 1 0.612 0.357 Y (Y_1_OBUF) OBUF:I->O 3.169 Y_1_OBUF (Y) ------------------------------------------------------------------------------ Total 6.846ns
4.3.3 VERILOG simulation
(A)Design of 8-to-3 encoder (without priority)
module encoder(code,data);
output [2:0]code;
input [7:0]data;
reg [2:0]code;
always @ (data)
begin
if(data==8’b00000001) code =0; else
if(data==8’b00000010) code =1; else
if(data==8’b00000100) code =2; else
if(data==8’b00001000) code =3; else
if(data==8’b00010000) code =4; else
if(data==8’b00100000) code =5; else
if(data==8’b01000000) code =6; else
if(data==8’b10000000) code =7; else code=3’bx;
end
/* Alternate description is given below
always @(data)
case(data)
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 52
8’b00000001 : code=0;
8’b00000010 : code=1;
8’b00000100 : code=2;
8’b00001000 : code=3;
8’b00010000 : code=4;
8’b00100000 : code=5;
8’b01000000 : code=6;
8’b10000000 : code=7;
endcase */
endmodule
// test bench for 8-3 encoder without priority
module encodertest;
reg [7:0]data;
wire [2:0] code;
encoder gg(core,data);//instantiation of encoder
always
begin
data = 8’b00000000;
#3 data = 8’b00000001;
#3 data = 8’b00000010;
#3 data = 8’b00000100;
#3 data = 8’b00001000;
#3 data = 8’b00010000;
#3 data = 8’b00100000;
#3 data = 8’b01000000;
#3 data = 8’b10000000;
end
$monitor($time, “data = $b, code = %b”,data,code);
initial #100 $stop
endmodule
(B)Design of 8-to-3 encoder (with priority)
module priorityencoder(code,valid_data,data);
output [2:0] code;
output valid_data;
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 53
input [7:0] data;
input [2:0] code;
assign valid_data = |data; //reduction ‘or’ operation
always @ (data)
begin
if (data[7]) code = 7; else
if (data[6]) code = 6; else
if (data[5]) code = 5; else
if (data[4]) code = 4; else
if (data[3]) code = 3; else
if (data[2]) code = 2; else
if (data[1]) code = 1; else
if (data[0]) code = 0; else
code=3’bx;
end
/* //Alternate description is given below
always @(data)
casex (data)
8’b1xxxxxxx : code=7;
8’b01xxxxxx : code=6;
8’b001xxxxx : code=5;
8’b0001xxxx : code=4;
8’b00001xxx : code=3;
8’b000001xx : code=2;
8’b0000001x : code=1;
8’b00000001 : code=0;
default : code=3’bx;
endcase
*/
endmodule
// test bench for 8-3 encoder with priority
module priorityencodertest;
reg [7:0]data;
wire [2:0] code;
priorityencoder gg(code,valid_data,data); //instantiation of encoder
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 54
always
begin
data = 8’bxxxxxxxx;
#3 data = 8’b00000001;
#3 data = 8’b0000001x;
#3 data = 8’b000001xx;
#3 data = 8’b00001xxx;
#3 data = 8’b0001xxxx;
#3 data = 8’b001xxxxx;
#3 data = 8’b01xxxxxx;
#3 data = 8’b1xxxxxxx;
end
$monitor($time, “valid_data = %b, data = $b, code = %b”,valid_data,data,code);
initial #100 $stop
endmodule
4.3.4 Implementaion
The decoder can be implemented on Spartan-3 FPGA kit as described
in section-3.
Result: 8-To-3 Encoder with Priority is designed using VHDL, VERILOG and simulated the same using Xilinx ISE Simulator
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 55
Experiment No:4
4.4 Design of 8-to-1 multiplexer
4.4.1 Aim: To Design 8-To-1 Multiplexer using VHDL and simulate the same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE
4.4.2 VHDL Simulation
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_8_1 is
Port ( En_L : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (2 downto 0);
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC);
end Mux_8_1;
architecture Behavioral of Mux_8_1 is
begin
process(S,I,En_L)
begin
if En_L='1' then YYYYYYYYY
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 56
when others=>Y
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 57
Number of Slices: 3 out of 2448 0%
Number of 4 input LUTs: 6 out of 4896 0%
Number of IOs: 13
Number of bonded IOBs: 13 out of 172 7%
TIMING REPORT:
Delay: 7.512ns (Levels of Logic = 6) Source: S (PAD) Destination: Y (PAD) Data Path: S to Y Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 4 1.106 0.651 S_0_IBUF (S_0_IBUF) LUT4:I0->O 1 0.612 0.000 Y97_F (N85) MUXF5:I0->O 2 0.278 0.449 Y97 (Y_map27) LUT3:I1->O 1 0.612 0.000 Y1241 (N89) MUXF5:I1->O 1 0.278 0.357 Y124_f5 (Y_OBUF) OBUF:I->O 3.169 Y_OBUF (Y) ---------------------------------------- Total 7.512ns
VHDL Test bench: LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Mux_8_1_vhd IS
END tb_Mux_8_1_vhd;
ARCHITECTURE behavior OF tb_Mux_8_1_vhd IS
COMPONENT Mux_8_1
PORT(
En_L : IN std_logic;
S : IN std_logic_vector(2 downto 0);
I : IN std_logic_vector(7 downto 0);
Y : OUT std_logic
);
END COMPONENT;
SIGNAL En_L : std_logic := '0';
SIGNAL S : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL Y : std_logic;
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 58
BEGIN
uut: Mux_8_1 PORT MAP(
En_L => En_L,
S => S,
I => I,
Y => Y
);
En_L
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 59
TRUTH TABLE:
S.No en_l Data select lines Output
A B C Y
1 0 0 0 0 I(0)
2 0 0 0 1 I(1)
3 0 0 1 0 I(2)
4 0 0 1 1 I(3)
5 0 1 0 0 I(4)
6 0 1 0 1 I(5)
7 0 1 1 0 I(6)
8 0 1 1 1 I(7)
9 1 X X X 0
VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;
entity mux151 is
port ( I :in STD_LOGIC_VECTOR (7 downto 0); --8 i/p lines
S :in STD_LOGIC_VECTOR (2 downto 0); --3 data select lines
en_l:in STD_LOGIC; --active low enable i/p
y :out STD_LOGIC --output line ); end
mux151; architecture mux151 of mux151 is
begin
process (I,s,en_l)
begin if en_l='0' then case
s is when "000" => y y y y y
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 60
when "101" => y y y null;
end case;
--y=0 when en_l=1
else y
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 61
TRUTH TABLE:
S.No. Data select lines output
strobe A B C D Y
1 0 0 0 0 0 d’(0)
2 0 0 0 0 1 d’(1)
3 0 0 0 1 0 d’(2)
4 0 0 0 1 1 d’(3)
5 0 0 1 0 0 d’(4)
6 0 0 1 0 1 d’(5)
7 0 0 1 1 0 d’(6)
8 0 0 1 1 1 d’(7)
9 0 1 0 0 0 d’(8)
10 0 1 0 0 1 d’(9)
11 0 1 0 1 0 d’(10)
12 0 1 0 1 1 d’(11)
13 0 1 1 0 0 d’(12)
14 0 1 1 0 1 d’(13)
15 0 1 1 1 0 d’(14)
16 0 1 1 1 1 d’(15)
17 1 X X X X 1
VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;
entity mux16 is
port(
strobe : in STD_LOGIC; --active low enable i/p D : in STD_LOGIC_VECTOR(15 downto 0); --16 i/p lines
Sel : in STD_LOGIC_VECTOR(3 downto 0); --4 data select lines Y :
out STD_LOGIC --output line ); end
mux16; architecture mux16 of mux16 is
signal Y_L:std_logic;
begin
with Sel select Y_L
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 62
D(12) when "1100", D(13)
when "1101", D(14) when
"1110", D(15) when "1111",
unaffected when others; Y
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 63
module mux_8-1-32bit(out,in1,in2,in3,in4,in4,in5,in6,in7,in8,select,enable);
output [31:0]out;
input [31:0] in1,in2,in3,in4,in5,in6,in7,in8;
input [2:0] select;
input enable;
reg [31:0] out1;
assign out=enable?out1:32’bz;
assign out1 = (select==0)?in1:
(select==1)?in2:
(select==2)?in3:
(select==3)?in4:
(select==4)?in5:
(select==5)?in6:
(select==6)?in7:
(select==7)?in8:32’bx;
endmodule
test bench for multiplexer
module muxtest;
reg [31:0] in1,in2,in3,in4,in5,in6,in7,in8;
reg [2:0] select;
wire [31:0] out;
mux_8-1-32bit gg(out,in1,in2,in3,in4,in4,in5,in6,in7,in8,select,enable);
initial eneble=1’b1;
always
begin
select = 3’b0;
#3 select = 3’b001
#3 select = 3’b010
#3 select = 3’b011
#3 select = 3’b100
#3 select = 3’b101
#3 select = 3’b110
#3 select = 3’b111
End
$monitor ($time, “select = %b, out\%b”,select,out);
Initial #100 $stop
endmodule
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 64
Experiment No:5
5.1 Design of 4 bit Binary to Gray code converter
5.1.1 Aim: To Design Binary-To-Gray Code Converter using VHDL and simulate the same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE
5.1.2 VHDL simulation
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Binary_to_gray is
Port ( B : in STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC_VECTOR (3 downto 0));
end Binary_to_gray;
architecture Behavioral of Binary_to_gray is
begin
G(3)
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 65
Simulation Results:
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Binary_to_gray_vhd IS
END tb_Binary_to_gray_vhd;
ARCHITECTURE behavior OF tb_Binary_to_gray_vhd IS
COMPONENT Binary_to_gray
PORT(
B : IN std_logic_vector(3 downto 0);
G : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL G : std_logic_vector(3 downto 0);
BEGIN
uut: Binary_to_gray PORT MAP(
B => B,
G => G
);
B
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 66
Schematic Diagram:
Synthesis Report
HDL Synthesis Report
Macro Statistics
# Xors : 3 1-bit xor2 : 3 Advanced HDL Synthesis Report Macro Statistics # Xors : 3 1-bit xor2 : 3
Final Report:
RTL Top Level Output File Name : Binary_to_gray.ngr Top Level Output File Name : Binary_to_gray Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 8 Cell Usage : # BELS : 3 # LUT2 : 3 # IO Buffers : 8 # IBUF : 4 # OBUF : 4 Device utilization summary: Selected Device : 3s250eft256-5 Number of Slices: 2 out of 2448 0% Number of 4 input LUTs: 3 out of 4896 0% Number of IOs: 8 Number of bonded IOBs: 8 out of 172 4% TIMING REPORT: Data Path: B to G Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 2 1.106 0.532 B_2_IBUF (B_2_IBUF) LUT2:I0->O 1 0.612 0.357 Mxor_G_Result1 (G_2_OBUF) OBUF:I->O 3.169 G_2_OBUF (G)
----------------------------------------
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 67
Total 5.776ns
Result: Binary-To-Gray Code Converter is designed using VHDL and simulated the same using Xilinx ISE Simulator
module binary2gray();
reg clk;
reg rstn;
reg [5:0] counter_binary, counter_binary_reg, counter_gray, co
unter_gray_reg;
integer count, file_wr;
/* Initial block to generate clock and reset */
initial begin
clk = 0; rstn = 0; #100 rstn = 1;
forever begin
#10 clk = !clk;
end end
/* Synchronous Logic for registering the data and incrementing
the counter for binary data */
always @ (posedge clk or negedge rstn)
begin
if (!rstn) begin
counter_binary_reg
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 68
for (i=5; i>0; i = i - 1)
binary2gray[i-1] = value[i] ^ value[i - 1];
end
endfunction
/* Get gray encoded output */
always @(*)
begin
counter_gray = counter_gray_reg;
counter_binary = counter_binary_reg;
counter_gray = binary2gray(counter_binary_reg); end
endmodule
// Another simple code for binary to gray code conversion
module bcd2gray(o,i);
output [3:0]o;
input [3:0]i;
reg [3:0]o;
always @(i)
begin
o[3]=i[3];
o[2]=i[3]^i[2];
o[1]=i[2]^i[1];
o[0]=i[1]^i[0];
end
endmodule
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 69
Experiment No:6
4.6 4 – bit Comparator
4.6.1 Aim: To Design 4-Bit Comparator using VHDL and simulate the same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE
4.6.2 VHDL Simulation
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
AEQB : out STD_LOGIC;
AGTB : out STD_LOGIC;
ALTB : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
process(A,B)
begin
if A=B then AEQB
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 70
Simulation Results:
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_comparator_vhd IS
END tb_comparator_vhd;
ARCHITECTURE behavior OF tb_comparator_vhd IS
COMPONENT comparator
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
AEQB : OUT std_logic;
AGTB : OUT std_logic;
ALTB : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL AEQB : std_logic;
SIGNAL AGTB : std_logic;
SIGNAL ALTB : std_logic;
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 71
BEGIN
uut: comparator PORT MAP(
A => A,
B => B,
AEQB => AEQB,
AGTB => AGTB,
ALTB => ALTB);
A
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 72
Number of IOs: 11 Number of bonded IOBs: 11 out of 172 6%
TIMING REPORT: Data Path: B to AGTB Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 1.106 0.603 B_1_IBUF (B_1_IBUF) LUT4:I0->O 2 0.612 0.532 AGTB31 (AGTB_bdd2) LUT4:I0->O 1 0.612 0.000 AGTB111 (N14) MUXF5:I1->O 1 0.278 0.357 AGTB11_f5 (AGTB_OBUF) OBUF:I->O 3.169 AGTB_OBUF (AGTB) ---------------------------------------- Total 7.269ns
Result: 4-Bit Comparator Converter is designed using VHDL and simulated the same using
Xilinx ISE
IC 74x85 – 4-BIT COMPARATOR
AIM: Write a VHDL code for IC 74x85 –4-bit comparator .
BLOCK DIAGRAM:
TRUTH TABLE:
S.No. Cascade Present input AGTBOUT AEQBOUT ALTBOUT
inputs condition
A>B A=B A
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 73
VHDL CODE:
library IEEE; use IEEE.std_logic_1164.all;
entity comp is
port ( altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC; a: in STD_LOGIC_VECTOR (3 downto 0); b: in STD_LOGIC_VECTOR (3 downto 0); agtbout: out STD_LOGIC; aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC );
end comp;
architecture comp of comp is begin
process(a,b,agtbin,aeqbin,altbin)
begin agtbout
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 74
4.6.4 VERILOG simulation /*Module for 4-bit comparator. Module for 2-bit comparator is prepared first. Using two 2-bit comparators, 4-bit comparator is built */ //module for 2-bit comparator
module comparator_2bit(A_gt_B,A_lt_B,A_eq_B,A0,A1,B0,B1);
output A_gt_B,A_lt_B,A_eq_B;
input A0,A1,B0,B1;
nor (A_gt_B,A_lt_B,A_eq_B);
or (A_lt_B,w1,w2,w3);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and(w2,w6,w7,B0);
and(w3,w7,B0,B1);
not(w6,A1);
not(w7,B0);
xnor(w4,A1,B1);
xnor(w5,A0,B0);
endmodule
//module for 4 bit comparator using 2-bit comparators module comparator_4bit(A_gt_B,A_lt_B,A_eq_B,A3,A2,A1,A0,B3,B2,B1,B0);
output A_gt_B,A_lt_B,A_eq_B;
input A3,A2,A1,A0,B3,B2,B1,B0;
wire w1,w0;
comparator_2bit m1(A_gt_B_M1,A_lt_B_M1,A_eq_B_M1,A3,A2,B3,B2);
comparator_2bit m0(A_gt_B_M0,A_lt_B_M0,A_eq_B_M0,A1,A0,B1,B0);
or (A_gt_B,A_gt_B_M1,w1);
and (w1,A_eq_B_M1,A_gt_B_M0);
and (A_eq_B,A_eq_B_M1,A_eq_B_M0)
or (A_lt_B,A_lt_B_M1,A_eq_B_M0);
and (w0,A_eq_B_M1,A_lt_B_M0);
endmodule
_____
//test bench for 4-bit comparator
module comparator_4bittest
reg [3:0] a,b;
wire a_gt_b , a_lt_b, a_eq_b;
comparator_4bit gg(a_gt_b,a_lt_b,a_eq_b,a[3],a[2],a[1],a[0],b[3],b[2],b[1],b[0]);
initial
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 75
begin
a_gt_b=1’b0;
a_lt_b=1’b0;
a_eq_b=1’b0;
end
always
begin
a=4’b0000;b=4’b0000;
#3 a=4’b0100;
#3 b=4’b0101;
#3 b=4’b0011;
#3 a=4’b1010;
#3 b=4’b1010;
#3 a=4’b1001;
End
$monitor($time,
“a=%b,b=%b,a_gt_b=%b,a_lt_b=%b,a_eq_b=%b”,a,b,a_gt_b,a_lt_b,a_eq_b);
Initial #100 $stop;
endmodule
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 76
Experiment No:7
4.7 Full Adder Using three design Styles
4.7.1 Aim: To Design Full Adder in three design Styles using VHDL and VERILOG and simulate the same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE
4.7.2 VHDL simulation
VHDL Code (data flow style):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Full_Adder_Dataflow is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder_Dataflow;
architecture Dataflow of Full_Adder_Dataflow is
signal X: STD_LOGIC;
begin
X
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 77
Schematic Diagram:
Synthesis Report
HDL Synthesis Report: Macro Statistics # Xors : 2 1-bit xor2 : 2
Final Report:
Final Results RTL Top Level Output File Name : Full_Adder_Dataflow.ngr Top Level Output File Name : Full_Adder_Dataflow Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 5 Cell Usage : # BELS : 2 # LUT3 : 2 # IO Buffers : 5 # IBUF : 3 # OBUF : 2 Device utilization summary: Selected Device : 3s250eft256-5 Number of Slices: 1 out of 2448 0% Number of 4 input LUTs: 2 out of 4896 0% Number of IOs: 5 Number of bonded IOBs: 5 out of 172 2%
TIMING
Delay: 5.776ns (Levels of Logic = 3)
Source: B (PAD)
Destination: Cout (PAD)
Data Path: B to Cout
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 78
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 B_IBUF (B_IBUF)
LUT3:I0->O 1 0.612 0.357 Cout1 (Cout_OBUF)
OBUF:I->O 3.169 Cout_OBUF (Cout)
----------------------------------------
Total 5.776ns
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Full_Adder_Dataflow_vhd IS
END tb_Full_Adder_Dataflow_vhd;
ARCHITECTURE behavior OF tb_Full_Adder_Dataflow_vhd IS
COMPONENT Full_Adder_Dataflow
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Sum : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL Cin : std_logic := '0';
SIGNAL Sum : std_logic;
SIGNAL Cout : std_logic;
BEGIN
uut: Full_Adder_Dataflow PORT MAP(
A => A,
B => B,
Cin => Cin,
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 79
Sum => Sum,
Cout => Cout
);
A
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 80
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder_Behavioral;
architecture Behavioral of Full_Adder_Behavioral is
signal P:Std_logic_vector(2 downto 0);
begin
PSum
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 81
Synthesis Report
HDL Synthesis Report
Macro Statistics # ROMs : 1 8x2-bit ROM : 1
Final Report:
Final Results
RTL Top Level Output File Name : Full_Adder_Behavioral.ngr
Top Level Output File Name : Full_Adder_Behavioral
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 5
Cell Usage :
# BELS : 2
# LUT3 : 2
# IO Buffers : 5
# IBUF : 3
# OBUF : 2
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 1 out of 2448 0%
Number of 4 input LUTs: 2 out of 4896 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 172 2%
TIMING REPORT:
Delay: 5.776ns (Levels of Logic = 3)
Source: B (PAD)
Destination: Cout (PAD)
Data Path: B to Cout
Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 2 1.106 0.532 B_IBUF (B_IBUF) LUT3:I0->O 1 0.612 0.357 Mrom_P_rom000011 (Mrom_P_rom0000) OBUF:I->O 3.169 Cout_OBUF (Cout)
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 82
---------------------------------------- Total 5.776ns
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Full_Adder_Behavioral_vhd IS
END tb_Full_Adder_Behavioral_vhd;
ARCHITECTURE behavior OF tb_Full_Adder_Behavioral_vhd IS
COMPONENT Full_Adder_Behavioral
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Sum : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL Cin : std_logic := '0';
SIGNAL Sum : std_logic;
SIGNAL Cout : std_logic;
BEGIN
uut: Full_Adder_Behavioral PORT MAP(
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
A
-
HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof
ECE department, Mahaveer institute of science and technology, Hyderabad Page 83
Cin
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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, La