imx53rm

i.MX53 Multimedia Applications Processor Reference Manual

Document Number: IMX53RM Rev. 1A 03/2011

i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/20112 Freescale Semiconductor, Inc.

ContentsSection Number Title Chapter 1 Introduction1.1 About This Document...................................................................................................................................................179 1.1.1 1.1.2 1.1.3 Audience......................................................................................................................................................180 Organization.................................................................................................................................................180 Suggested Reading.......................................................................................................................................180 1.1.3.1 1.1.3.2 1.1.4 1.1.5 1.1.6 1.1.7 1.2 1.3 1.4 1.5 General Information.................................................................................................................180 Related Documentation............................................................................................................181

Page

Conventions.................................................................................................................................................181 Register Diagram Field Access Type Legend..............................................................................................183 Signal Conventions......................................................................................................................................183 Acronyms and Abbreviations.......................................................................................................................183

Overview.......................................................................................................................................................................185 Target Applications.......................................................................................................................................................185 Features.........................................................................................................................................................................185 Architectural Overview.................................................................................................................................................189 1.5.1 1.5.2 1.5.3 1.5.4 Simplified Block Diagram...........................................................................................................................189 Major Subsystems........................................................................................................................................190 Architectural Partitioning.............................................................................................................................191 Endianness Support......................................................................................................................................193

1.6 1.7

Block List......................................................................................................................................................................193 Memory Interfaces........................................................................................................................................................204

Chapter 2 Memory Map2.1 2.2 ARM Platform System Memory Map...........................................................................................................................207 DMA Memory Map......................................................................................................................................................212

i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011Freescale Semiconductor, Inc. 3

Section Number

Title Chapter 3 Interrupts and SDMA Events

Page

3.1 3.2 3.3

Overview.......................................................................................................................................................................213 ARM Platform Interrupts..............................................................................................................................................213 SDMA Event Mapping.................................................................................................................................................217

Chapter 4 External Signals and Pin Multiplexing4.1 4.2 Overview.......................................................................................................................................................................221 Controlling Pin Multiplexing........................................................................................................................................221 4.2.1 4.2.2 4.3 Multiplexing and Pad Control......................................................................................................................222 Daisy Chain Control.....................................................................................................................................372

Special Package Pins.....................................................................................................................................................399

Chapter 5 External Memory5.1 5.2 Overview.......................................................................................................................................................................401 External Memory Interface - i.MX53 Specific Configuration......................................................................................403 5.2.1 5.2.2 5.3 EXTMC - AXI Bus Masters........................................................................................................................403 Features........................................................................................................................................................404

EXTMC Setup..............................................................................................................................................................407 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 Clock Domains.............................................................................................................................................407 Boot Scenarios.............................................................................................................................................408 Watermark Ports..........................................................................................................................................408 EXTMC I/O Multiplexing...........................................................................................................................408 External Interface Module (EIM) boot configuration..................................................................................415

5.4

External Memory Controller (EXTMC) Restrictions...................................................................................................415 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 Exclusive Access Support............................................................................................................................415 Software LPMD...........................................................................................................................................415 Data Paths....................................................................................................................................................416 NAND Flash Restrictions/Limitations.........................................................................................................416 OneNAND Restrictions/Limitations............................................................................................................417 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011

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Freescale Semiconductor, Inc.

Section Number

Title Chapter 6 System Debug

Page

6.1

Overview.......................................................................................................................................................................419 6.1.1 6.1.2 Introduction..................................................................................................................................................419 Debug Strategy.............................................................................................................................................420

6.2

System JTAG Controller - SJC.....................................................................................................................................420 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 JTAG Topology...........................................................................................................................................420 System JTAG Controller Main Feature.......................................................................................................421 SJC TAP Port...............................................................................................................................................421 SJC Main Blocks..........................................................................................................................................422 i.MX53 Specific SJC Features.....................................................................................................................422 6.2.5.1 6.2.5.2 JTAG Disable Mode................................................................................................................422 SJC i.MX53 Specific Registers................................................................................................423 6.252.1 General Purpose Unsecured Status Register 1 (SJC i.MX53 Specific Registers_GPUSR1).........................................................................................425 6.252.2 General Purpose Unsecured Status Register 2 (SJC i.MX53 Specific Registers_GPUSR2).........................................................................................426 6.252.3 General Purpose Unsecured Status Register 3 (SJC i.MX53 Specific Registers_GPUSR3).........................................................................................427 6.252.4 General Purpose Secured Status Register (SJC i.MX53 Specific Registers_GPSSR)............................................................................................428 6.252.5 6.252.6 6.252.7 Debug Control Register (Secured) (SJC i.MX53 Specific Registers_DCR)....429 Security Status Register (SJC i.MX53 Specific Registers_SSR).....................431 Charge Pump Configuration Register (SJC i.MX53 Specific Registers_CPCR)..............................................................................................433 6.252.8 General Purpose Clocks Control Register (SJC i.MX53 Specific Registers_GPCCR)...........................................................................................433 6.252.9 6.252.10 PLL Bypass Register (SJC i.MX53 Specific Registers_PLLBR)....................435 General Purpose Unsecured Control Register 1 n (SJC i.MX53 Specific Registers_GPUCR1).........................................................................................437


Section Number6.252.11

TitleGeneral Purpose Unsecured Control Register 2 n (SJC i.MX53 Specific

Page

Registers_GPUCR2).........................................................................................439 6.252.12 General Purpose Unsecured Control Register 3 n (SJC i.MX53 Specific Registers_GPUCR3).........................................................................................441 6.252.13 General Purpose Secured Control Register (SJC i.MX53 Specific Registers_GPSCR)............................................................................................443 6.252.14 6.252.15 6.252.16 6.252.17 6.252.18 6.252.19 Test Register (SJC i.MX53 Specific Registers_TESTREG)............................444 Serial Access Select Register (SJC i.MX53 Specific Registers_SASR)..........444 BIST Configuration Register 1 (SJC i.MX53 Specific Registers_BISTCR1). 445 BIST Configuration Register 2 (SJC i.MX53 Specific Registers_BISTCR2). 446 BIST Configuration Register 3 (SJC i.MX53 Specific Registers_BISTCR3). 447 BIST Configuration Register 4 n (SJC i.MX53 Specific Registers_BISTCR4)........................................................................................448 6.252.20 6.252.21 6.252.22 6.252.23 BIST Configuration Register 5 (SJC i.MX53 Specific Registers_BISTCR5). 450 Bist Configuration Register 6 (SJC i.MX53 Specific Registers_BISTCR6)....451 Bist Configuration Register 7 (SJC i.MX53 Specific Registers_BISTCR7)....452 Memory BIST Pass-Fail Register 1 (reserved for Test) (SJC i.MX53 Specific Registers_MBISTPASSR1)................................................................453 6.252.24 Memory BIST Pass-Fail Register 2 (SJC i.MX53 Specific Registers_MBISTPASSR2)..............................................................................455 6.252.25 Memory BIST Done Register 1 (SJC i.MX53 Specific Registers_MBISTDONER1)............................................................................455 6.252.26 Memory BIST Done Register 2 (SJC i.MX53 Specific Registers_MBISTDONER2)............................................................................457 6.252.27 Memory BIST Mask Register 2 (SJC i.MX53 Specific Registers_MBISTMASKR2)............................................................................457 6.252.28 6.252.29 6.252.30 BIST Pass-Fail Register (SJC i.MX53 Specific Registers_BISTPASSR).......458 BIST Done Register (SJC i.MX53 Specific Registers_BISTDONER)............458 Monitor BIST Select Register (SJC i.MX53 Specific Registers_MONBISTSELR).............................................................................459 6.252.31 RVAL/WVAL Control Register (SJC i.MX53 Specific Registers_RWVALCR)....................................................................................459 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/20116 Freescale Semiconductor, Inc.

Section Number6.2.5.3 6.3

Title

Page

PROD ID & JTAG ID..............................................................................................................459

CoreSight Design Kit....................................................................................................................................................460 6.3.1 6.3.2 6.3.3 6.3.4 Memory Map and Register Definition.........................................................................................................460 CoreSight Clock Enable ..............................................................................................................................460 CoreSight DAP and DAP_SYS...................................................................................................................460 Embedded Cross Trigger (ECT)..................................................................................................................461 6.3.4.1 6.3.4.2 6.3.4.3 6.3.5 CoreSight CTM........................................................................................................................463 CoreSight CTI..........................................................................................................................463 Extended CTI (CTI Wrapper)..................................................................................................466

CoreSight Trace Port Interface (TPIU) .......................................................................................................467

6.4

Cortex A8 Core and Platform.......................................................................................................................................467 6.4.1 6.4.2 6.4.3 Cortex A8 Core Debug Support Features....................................................................................................467 Embedded Cross Trigger Interface..............................................................................................................468 Additional Platform Debug Functionality....................................................................................................468

6.5

Smart Direct Memory Access (SDMA) Core...............................................................................................................469 6.5.1 6.5.2 6.5.3 SDMA On Chip Emulation Module (OnCE) Feature Summary.................................................................469 Other SDMA Debug Functionality..............................................................................................................470 Embedded Cross Trigger Interface (SDMA)...............................................................................................471

6.6 6.7 6.8

External Memory Controller (EXTMC).......................................................................................................................471 Debug Visibility - IOMUX...........................................................................................................................................472 ARM Platform Peripherals...........................................................................................................................................472 6.8.1 6.8.2 6.8.3 Image Processing Unit (IPU).......................................................................................................................472 Video Processing Unit (VPU)......................................................................................................................473 GPU3D.........................................................................................................................................................473

6.9 6.10 6.11

Supported Tools............................................................................................................................................................473 Interrupt Visibility .......................................................................................................................................................473 Miscellaneous...............................................................................................................................................................473 6.11.1 6.11.2 SoC-level Bus Trace....................................................................................................................................473 Clock / Reset / Power...................................................................................................................................474 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011


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Section Number6.11.3

Title

Page

RVI connection Settings..............................................................................................................................474

Chapter 7 System Boot7.1 7.2 Introduction...................................................................................................................................................................477 Boot Modes...................................................................................................................................................................478 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 Boot Mode Pin Settings...............................................................................................................................478 High Level Boot Sequence..........................................................................................................................479 Internal Boot (BOOT_MODE[1:0] = 0b00)................................................................................................480 Boot From Fuses (BOOT_MODE[1:0] = 0b10)..........................................................................................480 Mode: Serial Downloader (BOOT_MODE[1:0] = 0b11)............................................................................481 Boot Security Settings..................................................................................................................................482

Device Configuration....................................................................................................................................................482 7.3.1 7.3.2 7.3.3 Boot eFUSE Descriptions............................................................................................................................482 GPIO Boot Overrides...................................................................................................................................484 Device Configuration Data..........................................................................................................................485

7.4

Device Initialization......................................................................................................................................................485 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 Internal ROM /RAM Memory Map.............................................................................................................486 Boot Block Activation ................................................................................................................................487 Clocks at Boot Time....................................................................................................................................488 Enabling MMU and Caches.........................................................................................................................492 Exception Handling......................................................................................................................................492 Interrupt Handling During Boot...................................................................................................................493 Persistent Bits...............................................................................................................................................493

7.5

Boot Devices (Internal Boot)........................................................................................................................................494 7.5.1 NOR Flash/OneNand using EIM Interface..................................................................................................494 7.5.1.1 7.5.1.2 7.5.1.3 NOR Flash Boot Operation......................................................................................................495 OneNAND Flash Boot Operation............................................................................................495 IOMUX Configuration for EIM Devices.................................................................................496


Section Number7.5.2

Title

Page

NAND Flash................................................................................................................................................497 7.5.2.1 7.5.2.2 7.5.2.3 7.5.2.4 NAND eFUSE Configuration..................................................................................................497 NAND Flash Boot Flow..........................................................................................................499 Bad Block Marker Swapping...................................................................................................502 IOMUX Configuration for NAND..........................................................................................503

7.5.3

Expansion Device........................................................................................................................................503 7.5.3.1 7.5.3.2 7.5.3.3 7.5.3.4 7.5.3.5 Expansion Device eFUSE Configuration................................................................................504 MMC and eMMC Boot............................................................................................................505 SD and eSD..............................................................................................................................511 IOMUX Configuration for SD/MMC......................................................................................511 Redundant Boot Support for Expansion Device......................................................................512

7.5.4

Hard Disk and SSD......................................................................................................................................513 7.5.4.1 7.5.4.2 7.5.4.3 7.5.4.4 Hard Disk and SSD eFUSE Configuration..............................................................................513 IOMUX Configuration for PATA............................................................................................514 IOMUX Configuration for SATA............................................................................................515 Redundant Boot Support for Hard Disk and SSD....................................................................515

7.5.5

Serial ROM through SPI and I2C................................................................................................................517 7.5.5.1 7.5.5.2 Serial ROM eFUSE Configuration..........................................................................................517 I2C Boot...................................................................................................................................518 7.5.5.2.1 7.5.5.3 I2C IOMUX Pin Configuration........................................................................519

CSPI Boot................................................................................................................................519 7.5.5.3.1 ECSPI/CSPI IOMUX Pin Configuration..........................................................521

7.6

Program Image..............................................................................................................................................................522 7.6.1 Image Vector Table and Boot Data..............................................................................................................522 7.6.1.1 7.6.1.2 7.6.2 Image Vector Table Structure..................................................................................................523 Boot Data Structure..................................................................................................................524

Device Configuration Data (DCD)..............................................................................................................524 7.6.2.1 7.6.2.2 Write Data Command..............................................................................................................525 Check Data Command.............................................................................................................527


Section Number7.6.2.3 7.7 7.8

Title

Page

NOP Command........................................................................................................................529

Plugin Image.................................................................................................................................................................529 Serial Downloader (BOOT_MODE[1:0] = 0b11)........................................................................................................530 7.8.1 USB..............................................................................................................................................................531 7.8.1.1 7.8.1.2 7.8.2 USB Configuration Details......................................................................................................531 IOMUX Configuration for USB..............................................................................................532

UART...........................................................................................................................................................532 7.8.2.1 IOMUX Configuration for UART...........................................................................................532

7.8.3

Serial Download Protocol............................................................................................................................533 7.8.3.1 7.8.3.2 7.8.3.3 7.8.3.4 7.8.3.5 7.8.3.6 Get Status.................................................................................................................................533 Read Memory...........................................................................................................................534 Write Memory..........................................................................................................................534 Re-enumerate...........................................................................................................................535 Write File.................................................................................................................................535 Completed................................................................................................................................536

7.9 7.10

Watchdog Reset Boot Mode.........................................................................................................................................536 High Assurance Boot (HAB)........................................................................................................................................537 7.10.1 7.10.2 ROM Vector Table Addresses.....................................................................................................................538 SRTC Initialization......................................................................................................................................538

7.11

Examples.......................................................................................................................................................................538 7.11.1 7.11.2 NAND eFuse Configuration Example.........................................................................................................538 DCD Example..............................................................................................................................................539

Chapter 8 Multimedia8.1 8.2 The Video/Graphics Sub-System..................................................................................................................................541 Image Processing Unit (IPU)........................................................................................................................................544 8.2.1 External Ports-IPU.......................................................................................................................................547 8.2.1.1 Camera Port..............................................................................................................................547


Section Number8.2.1.2

Title

Page

Display Ports............................................................................................................................548 8.2.1.2.1 Access Modes...................................................................................................548 8.2.1.2.1.1 8.2.1.2.1.2 8.2.1.2.2 Synchronous Access.................................................................548 Asynchronous Access ..............................................................549

The Interface.....................................................................................................549 8.2.1.2.2.1 Connecting To Display Devices...............................................550

8.2.2

Processing-IPU.............................................................................................................................................551 8.2.2.1 8.2.2.2 8.2.2.3 8.2.2.4 Display Processor (DP)............................................................................................................553 Video Deinterlacer (VDIC)......................................................................................................553 Image Converter (IC)...............................................................................................................554 Image Rotator (IRT).................................................................................................................555

8.2.3 8.3

Automatic Procedures..................................................................................................................................555

LVDS Display Bridge (LDB).......................................................................................................................................557 8.3.1 External Ports-LDB......................................................................................................................................560 8.3.1.1 8.3.1.2 8.3.1.3 8.3.1.4 8.3.2 Input Parallel Display Ports.....................................................................................................560 Output LVDS Ports..................................................................................................................561 Control Signals.........................................................................................................................561 Clock Sources..........................................................................................................................561

Processing-LDB...........................................................................................................................................562 8.3.2.1 LDB Data Input Logic.............................................................................................................562 8.3.2.1.1 Mapping of Input Data Busses..........................................................................562 8.3.2.1.1.1 8.3.2.1.1.2 8.3.2.1.2 8.3.2.2 8.3.2.3 8.3.2.4 Channel Mapping.....................................................................562 Input Bus Split..........................................................................563

Bit Mapping......................................................................................................563

LDB Control ...........................................................................................................................564 LDB Tx Clock .........................................................................................................................564 PHY..........................................................................................................................................564

8.4

Video Processing Unit (VPU).......................................................................................................................................565 8.4.1 Basic Structure.............................................................................................................................................566 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011


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Section Number8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 8.4.12 8.4.13 8.4.14 8.4.15 8.4.16 8.4.17 8.5

Title

Page

Feature Summary.........................................................................................................................................567 Other Features of VPU.................................................................................................................................568 Architectural Overview................................................................................................................................568 Interfaces......................................................................................................................................................569 Operating Frequencies.................................................................................................................................570 Architectural Features..................................................................................................................................571 Memory Requirements ................................................................................................................................571 Internal Memory (iRAM).............................................................................................................................571 External Memory (SDRAM).......................................................................................................................572 VPU Integration into SoC............................................................................................................................573 External Bus Connection.............................................................................................................................573 Other Signals Connection............................................................................................................................574 Clocking Architecture..................................................................................................................................574 Power Management......................................................................................................................................575 Interrupt........................................................................................................................................................575 Reset.............................................................................................................................................................576

OpenGL/ES Graphics Processing Unit 3D (GPU3D)..................................................................................................577 8.5.1 8.5.2 GPU3D Overview........................................................................................................................................577 GPU3D Features..........................................................................................................................................577 8.5.2.1 8.5.3 8.5.4 Capabilities...............................................................................................................................578

GPU3D Block Diagram...............................................................................................................................579 GPU3D Performance...................................................................................................................................584 8.5.4.1 GPU3D Memory Accesses......................................................................................................585

8.5.5

GPU3D Clocking.........................................................................................................................................586 8.5.5.1 GPU3D Clock Gating .............................................................................................................586

8.5.6 8.5.7 8.5.8 8.5.9

GPU3D Resets.............................................................................................................................................587 GPU3D Interrupts........................................................................................................................................587 Debug...........................................................................................................................................................587 Software.......................................................................................................................................................587 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011

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Section Number8.6

Title

Page

Graphics Processing Unit 2D (GPU2D).......................................................................................................................588 8.6.1 8.6.2 GPU2D Overview........................................................................................................................................588 GPU2D Features..........................................................................................................................................589 8.6.2.1 8.6.2.2 8.6.3 8.6.4 2D Bitmap Graphics (Separate 2D unit)..................................................................................589 Vector Graphics.......................................................................................................................590

GPU2D Block Diagram...............................................................................................................................591 GPU2D Performance...................................................................................................................................593 8.6.4.1 GPU2D Memory Accesses......................................................................................................593

8.6.5

GPU2D Clocking.........................................................................................................................................593 8.6.5.1 GPU2D Clock Gating..............................................................................................................593

8.6.6 8.6.7 8.7

GPU2D Resets.............................................................................................................................................594 GPU2D Interrupts........................................................................................................................................594

Audio Subsystem..........................................................................................................................................................594 8.7.1 8.7.2 Overview......................................................................................................................................................594 Audio Subsystem Block Diagram................................................................................................................595 8.7.2.1 8.7.2.2 8.7.3 8.7.4 8.7.5 Standard Serial Interface Controller (SSI)...............................................................................596 Digital Audio MUX (AUDMUX)............................................................................................597

Enhanced Serial Audio Interface (ESAI).....................................................................................................599 Sony/Philips Digital Interface (SPDIF).......................................................................................................599 Asynchronous Sample Rate Converter (ASRC)..........................................................................................600

Chapter 9 Power Management9.1 9.2 Overview.......................................................................................................................................................................605 Power Saving Methodology..........................................................................................................................................606 9.2.1 9.2.2 9.3 9.4 Active Power Savings..................................................................................................................................606 Leakage Power Savings...............................................................................................................................606

Block Connectivity for Low Power Modes..................................................................................................................607 Low Power Modes........................................................................................................................................................608 9.4.1 Low Power Mode Inputs to Blocks in i.MX53............................................................................................609 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011


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Section Number9.4.2 9.4.3 9.5 9.6

Title

Page

Power Down Sequence................................................................................................................................609 Power Up Sequence.....................................................................................................................................610

RAM Memory Supply Connections ............................................................................................................................610 Dynamic Voltage and Frequency Scaling (DVFS) ......................................................................................................611

Chapter 10 System Security10.1 Introduction...................................................................................................................................................................613

Chapter 11 ARM Cortex A8 Platform (ARM Platform)11.1 11.2 Introduction...................................................................................................................................................................615 Overview.......................................................................................................................................................................615 11.2.1 Core Platform Sub-Blocks...........................................................................................................................618 11.2.1.1 11.2.1.2 11.2.1.3 11.2.1.4 11.2.1.5 11.2.1.6 11.2.1.7 11.2.1.8 11.2.1.9 11.2.1.10 11.2.2 ARM platform..........................................................................................................................618 Instruction Fetch......................................................................................................................619 Instruction Decode...................................................................................................................620 Instruction Execute..................................................................................................................620 Load/Store................................................................................................................................620 L2 Cache..................................................................................................................................621 NEON.......................................................................................................................................621 Processor Debug Unit..............................................................................................................621 Embedded Trace Marcocell (ETM).........................................................................................622 Cross Trigger Interface 0 (CTI0).............................................................................................622

Summary of Remaining Platform Components...........................................................................................622 11.2.2.1 11.2.2.2 Platform Controller .................................................................................................................622 Debug Sub-Blocks...................................................................................................................623 11.2.2.2.1 11.2.2.2.2 11.2.2.2.3 11.2.2.2.4 Embedded Trace Buffer (ETB).........................................................................623 AMBA Trace Bus (ATB) Replicator................................................................624 Cross Trigger Interface 1 (CTI1)......................................................................624 Cross Trigger Matrix - CTM.............................................................................624


Section Number11.2.2.2.5 11.2.2.3 11.2.3 11.2.4 11.2.5

Title

Page

Advanced Peripheral Bus - APB Debug Bus....................................................625

Asynchronous Wrapper............................................................................................................625

Configuration...............................................................................................................................................625 Endian Modes..............................................................................................................................................625 Bus Interfaces...............................................................................................................................................625 11.2.5.1 11.2.5.2 11.2.5.3 11.2.5.4 AMBA AXI Interface..............................................................................................................626 APB CoreSight Interface.........................................................................................................626 ATB CoreSight Interface.........................................................................................................626 Peripheral Interface (IP Bus)....................................................................................................626

11.3

Memory Map and Register Definition..........................................................................................................................626 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 Platform Version ID (ARM_PVID).............................................................................................................627 General Purpose Control (ARM_GPC).......................................................................................................628 Low Power Control (ARM_LPC)................................................................................................................630 NEON Low Power Control (ARM_NLPC).................................................................................................631 Internal Clock Generation Control (ARM_ICGC)......................................................................................632 ARM Memory Configuration (ARM_AMC)..............................................................................................634 NEON Monitor Control (ARM_NMC).......................................................................................................635 NEON Monitor Status (ARM_NMS)..........................................................................................................636

11.4 11.5

Platform Clocks............................................................................................................................................................636 Platform Power Management.......................................................................................................................................637 11.5.1 Voltage and Frequency Scaling...................................................................................................................637 11.5.1.1 11.5.1.2 11.5.2 Asynchronous Interface Logic.................................................................................................637 Level Shifting between SoC-logic and ARM-logic.................................................................638

Power Gating in the ARM platform.............................................................................................................638 11.5.2.1 11.5.2.2 11.5.2.3 11.5.2.4 11.5.2.5 Isolation Circuitry at the ARM platform Interface..................................................................638 Power Gating the Memory Peripheries....................................................................................638 Retaining the State of the ARM platform Registers................................................................638 Power Gating the ARM platform High Performance Logic Gates..........................................639 Power Gating the L2 Bit Arrays..............................................................................................639


Section Number11.5.2.6 11.5.2.7 11.5.3

Title

Page

Controlling Power Gating using the General Power Controller (GPC) ..................................639 Power Gating the NEON Block...............................................................................................640

Modes of Operation.....................................................................................................................................643

Chapter 12 ARM Platform Debug12.1 Introduction ..................................................................................................................................................................645 12.1.1 12.1.2 Overview......................................................................................................................................................645 ARM Debug Blocks.....................................................................................................................................646 12.1.2.1 Processor Debug Unit..............................................................................................................647 12.1.2.1.1 12.1.2.1.2 12.1.2.1.3 12.1.2.2 12.1.2.3 12.1.2.4 12.1.2.5 12.1.2.6 12.1.2.7 12.1.2.8 Halting Debug-Mode Debugging.....................................................................647 Monitor Debug-Mode Debugging....................................................................647 Programming the Debug Unit...........................................................................647

ARM embedded trace macrocell (ARM ETM).......................................................................648 CoreSight Embedded Trace Buffer (CSETB)..........................................................................649 CoreSight Replicator (CSREPLICATOR)...............................................................................650 CoreSight trace port interface unit (CSTPIU)..........................................................................650 CoreSight cross trigger interface (CSCTI)...............................................................................651 CoreSight Cross Trigger Matrix (CSCTM).............................................................................653 Debug Access Port (DAP).......................................................................................................653 12.1.2.8.1 DAP_SYS.........................................................................................................654

12.1.3

Modes of Operation.....................................................................................................................................655 12.1.3.1 12.1.3.2 12.1.3.3 12.1.3.4 ARM Invasive Debug Mode....................................................................................................655 ARM Non-Invasive Debug Mode (Real-time Trace)..............................................................655 Normal Operating Modes.........................................................................................................656 Low Power Modes...................................................................................................................656

12.2

Memory Map and Register Definition..........................................................................................................................656 12.2.1 Register Summary........................................................................................................................................657 12.2.1.1 12.2.1.2 DAP JTAG DP Registers.........................................................................................................658 DAP ROM Register Summary.................................................................................................658


Section Number12.2.1.3

Title

Page

Processor Debug Unit Register Summary...............................................................................659 12.2.1.3.1 12.2.1.3.2 Coprocessor Registers Summary......................................................................659 Memory Mapped Registers Summary..............................................................660

12.2.1.4 12.2.1.5 12.2.1.6 12.2.1.7 12.2.2 12.2.3

ETB Register Summary...........................................................................................................661 ETM Register Summary..........................................................................................................663 CSCTI Register Summary.......................................................................................................665 TPIU Register Summary..........................................................................................................667

Clocks...........................................................................................................................................................670 Reset.............................................................................................................................................................670

Chapter 13 Multi-Layer AHB Crossbar Switch (AHBMAX)13.1 13.2 Overview.......................................................................................................................................................................673 Features.........................................................................................................................................................................675 13.2.1 13.2.2 13.3 Limitations...................................................................................................................................................675 General Operation........................................................................................................................................675

AHBMAX Interface Signals.........................................................................................................................................677 13.3.1 AHBMAX Signal Descriptions...................................................................................................................677 13.3.1.1 13.3.1.2 max_halt_request.....................................................................................................................677 max_halted...............................................................................................................................677

13.4

Programmable Registers...............................................................................................................................................677 13.4.1 13.4.2 13.4.3 Master Priority Register for Slave port n (AHBMAX_MPRn)...................................................................679 General Purpose Control Register for Slave port n (AHBMAX_SGPCRn)...............................................681 General Purpose Control Register for Master port n (AHBMAX_MGPCRn)............................................683

13.5 13.6

Coherency.....................................................................................................................................................................684 Detailed Functional Description...................................................................................................................................684 13.6.1 Arbitration....................................................................................................................................................684 13.6.1.1 13.6.1.2 13.6.1.3 Arbitration During Undefined Length Bursts..........................................................................684 Fixed Priority Operation..........................................................................................................685 Round-Robin Priority Operation..............................................................................................686


Section Number13.6.2 13.6.3

Title

Page

Priority Assignment.....................................................................................................................................686 Master Port Functionality.............................................................................................................................686 13.6.3.1 13.6.3.2 13.6.3.3 13.6.3.4 13.6.3.5 Master Port General Information.............................................................................................686 Master Port Decoders...............................................................................................................689 Master Port Capture Unit.........................................................................................................689 Master Port Registers...............................................................................................................689 Master Port State Machine.......................................................................................................689 13.6.3.5.1 13.6.3.5.2 Master Port State Machine States.....................................................................689 Master Port State Machine Slave Swapping.....................................................690

13.6.4

Slave Port Functionality...............................................................................................................................691 13.6.4.1 13.6.4.2 13.6.4.3 13.6.4.4 Slave Port General Information...............................................................................................691 Slave Port Muxes.....................................................................................................................692 Slave Port Registers.................................................................................................................693 Slave Port State Machine.........................................................................................................693 13.6.4.4.1 13.6.4.4.2 13.6.4.4.3 13.6.4.4.4 13.6.4.4.5 Slave Port State Machine States.......................................................................693 Slave Port State Machine Arbitration...............................................................694 Slave Port State Machine Master Handoff........................................................694 Slave Port State Machine Parking.....................................................................697 Slave Port State Machine Halt Mode................................................................699

13.7 13.8

Initialization/Application Information..........................................................................................................................700 AHBMAX Interface......................................................................................................................................................700 13.8.1 13.8.2 AHBMAX Interface Overview....................................................................................................................700 Master Ports-AHBMAX Interface...............................................................................................................700 13.8.2.1 13.8.2.2 13.8.2.3 13.8.2.4 13.8.3 Terminated Accesses................................................................................................................700 Taken Accesses........................................................................................................................700 Stalled Accesses.......................................................................................................................701 Error Response Terminated Accesses......................................................................................701

Slave Ports-AHBMAX Interface.................................................................................................................701


Section Number

Title Chapter 14 AHB to IP Bridge (Trust Zone) (AIPSTZ)

Page

14.1

Introduction...................................................................................................................................................................703 14.1.1 Features........................................................................................................................................................703

14.2

General Operation.........................................................................................................................................................703 14.2.1 14.2.2 14.2.3 AIPSTZ Registers........................................................................................................................................704 Overview......................................................................................................................................................704 Control Registers..........................................................................................................................................705

14.3

Register Descriptions....................................................................................................................................................706 14.3.1 14.3.2 Master Privilege Registers...........................................................................................................................706 Off-Platform Peripheral Access Control Registers (AIPSTZ_OPACRs)....................................................707

14.4 14.5 14.6 14.7

Functional Description..................................................................................................................................................708 Access Protections........................................................................................................................................................708 Access Support..............................................................................................................................................................709 Initialization Information..............................................................................................................................................709 14.7.1 Security Block..............................................................................................................................................709

Chapter 15 Asynchronous Sample Rate Converter (ASRC)15.1 Introduction ..................................................................................................................................................................713 15.1.1 15.1.2 15.1.3 Overview......................................................................................................................................................715 Features........................................................................................................................................................716 Modes of Operation.....................................................................................................................................717 15.1.3.1 Data Transfer Schemes............................................................................................................717 15.1.3.1.1 15.1.3.1.2 15.1.3.2 Data Input Modes..............................................................................................717 Data Output Modes...........................................................................................718

Word Alignment Supported.....................................................................................................719 15.1.3.2.1 15.1.3.2.2 Input Data Alignment Modes............................................................................719 Output Data Alignment Modes.........................................................................719


Section Number15.2

Title

Page

Programmable Registers...............................................................................................................................................720 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.2.6 15.2.7 15.2.8 15.2.9 15.2.10 15.2.11 15.2.12 15.2.13 15.2.14 15.2.15 15.2.16 15.2.17 15.2.18 15.2.19 15.2.20 15.2.21 15.2.22 15.2.23 15.2.24 15.2.25 15.2.26 15.2.27 15.2.28 ASRC Control Register (ASRC_ASRCTR)................................................................................................723 ASRC Interrupt Enable Register (ASRC_ASRIER)...................................................................................725 ASRC Channel Number Configuration Register (ASRC_ASRCNCR)......................................................726 ASRC Filter Configuration Status Register (ASRC_ASRCFG).................................................................728 ASRC Clock Source Register (ASRC_ASRCSR).......................................................................................730 ASRC Clock Divider Register 1 (ASRC_ASRCDR1)................................................................................734 ASRC Clock Divider Register 2 (ASRC_ASRCDR2)................................................................................735 ASRC Status Register (ASRC_ASRSTR)...................................................................................................736 ASRC Parameter Register n (ASRC_ASRPMnn).......................................................................................739 ASRC ASRC Task Queue FIFO Register 1 (ASRC_ASRTFR1)...............................................................740 ASRC Channel Counter Register (ASRC_ASRCCR).................................................................................741 ASRC Data Input Register for Pair x (ASRC_ASRDIn).............................................................................742 ASRC Data Output Register for Pair x (ASRC_ASRDOn).........................................................................742 ASRC Ideal Ratio for Pair A-High Part (ASRC_ASRIDRHA)..................................................................743 ASRC Ideal Ratio for Pair A -Low Part (ASRC_ASRIDRLA)..................................................................743 ASRC Ideal Ratio for Pair B-High Part (ASRC_ASRIDRHB)...................................................................744 ASRC Ideal Ratio for Pair B-Low Part (ASRC_ASRIDRLB)....................................................................744 ASRC Ideal Ratio for Pair C-High Part (ASRC_ASRIDRHC)...................................................................745 ASRC Ideal Ratio for Pair C-Low Part (ASRC_ASRIDRLC)....................................................................745 ASRC 76kHz Period in terms of ASRC processing clock (ASRC_ASR76K)............................................746 ASRC 56kHz Period in terms of ASRC processing clock (ASRC_ASR56K)............................................747 ASRC Misc Control Register for Pair A (ASRC_ASRMCRA)..................................................................748 ASRC FIFO Status Register for Pair A (ASRC_ASRFSTA)......................................................................750 ASRC Misc Control Register for Pair B (ASRC_ASRMCRB)..................................................................751 ASRC FIFO Status Register for Pair B (ASRC_ASRFSTB)......................................................................753 ASRC Misc Control Register for Pair C (ASRC_ASRMCRC)..................................................................754 ASRC FIFO Status Register for Pair C (ASRC_ASRFSTC)......................................................................756 ASRC Misc Control Register 1 for Pair X (ASRC_ASRMCR1n)..............................................................757 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011

20


Section Number15.3 15.4 15.5

Title

Page

Interrupts.......................................................................................................................................................................758 DMA requests...............................................................................................................................................................758 Functional Description..................................................................................................................................................759 15.5.1 Algorithm Description.................................................................................................................................759 15.5.1.1 15.5.1.2 Signal Processing Flow............................................................................................................759 Operation of the Filter..............................................................................................................763 15.5.1.2.1 Support of Physical Clocks...............................................................................763

15.6

Startup Procedure..........................................................................................................................................................765

Chapter 16 Digital Audio Multiplexer (AUDMUX)16.1 Overview.......................................................................................................................................................................771 16.1.1 16.1.2 16.2 16.3 Features........................................................................................................................................................773 Modes and Operations.................................................................................................................................773

External Signal Description..........................................................................................................................................773 Default Register Configuration.....................................................................................................................................774 16.3.1 Default Port Configuration...........................................................................................................................774

16.4

Programmable Registers...............................................................................................................................................775 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.4.7 16.4.8 16.4.9 16.4.10 16.4.11 Port Timing Control Register 1 (AUDMUX_PTCR1)................................................................................776 Port Timing Control Register 2 (AUDMUX_PTCR2)................................................................................779 Port Timing Control Register 3 (AUDMUX_PTCR3)................................................................................782 Port Timing Control Register n (AUDMUX_PTCRn)................................................................................785 Port Data Control Register 1 (AUDMUX_PDCR1)....................................................................................778 Port Data Control Register 2 (AUDMUX_PDCR2)....................................................................................781 Port Data Control Register 3 (AUDMUX_PDCR3)....................................................................................784 Port Data Control Register 4 (AUDMUX_PDCR4)....................................................................................787 Port Data Control Register 5 (AUDMUX_PDCR5)....................................................................................788 Port Data Control Register 6 (AUDMUX_PDCR6)....................................................................................789 Port Data Control Register 7 (AUDMUX_PDCR7)....................................................................................791


Section Number16.5

Title

Page

Functional Description..................................................................................................................................................792 16.5.1 Operating Modes..........................................................................................................................................792 16.5.1.1 Port Receive Data Modes.........................................................................................................793 16.5.1.1.1 16.5.1.1.2 16.5.1.1.3 16.5.1.2 16.5.1.3 Normal Mode....................................................................................................794 Internal Network Mode.....................................................................................794 Transmit Data Output Enable Assertion...........................................................800

Tx/Rx Switch and External Network Mode.............................................................................801 Timing Modes..........................................................................................................................802 16.5.1.3.1 16.5.1.3.2 Synchronous Mode (4-Wire Interface).............................................................802 Asynchronous Mode (6-Wire Interface)...........................................................804

16.5.2

Connectivity Between Ports.........................................................................................................................807 16.5.2.1 16.5.2.2 16.5.2.3 16.5.2.4 Internal Port to External Port Connectivity..............................................................................808 External Port to External Port Connectivity............................................................................809 Internal Port to Internal Port Connectivity...............................................................................809 Loopback Connectivity............................................................................................................810

16.5.3

AUDMUX Clocking....................................................................................................................................810 16.5.3.1 16.5.3.2 16.5.3.3 AUDMUX Clock Inputs..........................................................................................................810 AUDMUX Clock Diagram......................................................................................................810 Clocking Restrictions...............................................................................................................811

Chapter 17 Clock Amplifier (CAMP)17.1 Introduction...................................................................................................................................................................813 17.1.1 17.1.2 17.1.3 Overview......................................................................................................................................................813 Features........................................................................................................................................................814 Modes of Operation.....................................................................................................................................814 17.1.3.1 17.1.3.2 17.1.3.3 Normal Mode...........................................................................................................................814 Power Down Mode..................................................................................................................814 Test Mode (Fault Bypass or Scan)...........................................................................................814


Section Number17.2

Title

Page

External Signal Description..........................................................................................................................................814 17.2.1 17.2.2 Signals Overview.........................................................................................................................................814 Detailed Signal Description.........................................................................................................................815 17.2.2.1 17.2.2.2 17.2.2.3 17.2.2.4 17.2.2.5 17.2.2.6 17.2.2.7 CKIH - External Clock Input...................................................................................................815 VDD - Power supply................................................................................................................815 VSS - Ground...........................................................................................................................815 IPT_SCAN_MODE - Scan Signal...........................................................................................815 PWD - Power Down Signal.....................................................................................................816 FAULT_BYP - Control Signal for Test Mode........................................................................816 CAMP_OUT - Clock Output from CAMP..............................................................................816

17.3 17.4

Memory Map/Register Definition.................................................................................................................................816 Functional Description..................................................................................................................................................816 17.4.1 CAMP Sub-Blocks.......................................................................................................................................816 17.4.1.1 17.4.1.2 17.4.1.3 17.4.2 Main Clock Amplifier..............................................................................................................816 Output Buffer...........................................................................................................................817 Level Shifter.............................................................................................................................817

CAMP Modes of Operation.........................................................................................................................817 17.4.2.1 17.4.2.2 17.4.2.3 Normal Mode...........................................................................................................................817 Power Down Mode..................................................................................................................817 Test Mode................................................................................................................................817

17.5

Initialization/Application Information..........................................................................................................................818

Chapter 18 Clock Control Module (CCM)18.1 Overview.......................................................................................................................................................................819 18.1.1 18.1.2 18.2 Features........................................................................................................................................................819 CCM Block Diagram...................................................................................................................................820

Programmable Registers...............................................................................................................................................822 18.2.1 18.2.2 CCM Control Register (CCM_CCR)...........................................................................................................824 CCM Control Divider Register (CCM_CCDR)...........................................................................................826 i.MX53 Multimedia Applications Processor Reference Manual, Rev. 1A, 03/2011


23

Section Number18.2.3 18.2.4 18.2.5 18.2.6 18.2.7 18.2.8 18.2.9 18.2.10 18.2.11 18.2.12 18.2.13 18.2.14 18.2.15 18.2.16 18.2.17 18.2.18 18.2.19 18.2.20 18.2.21 18.2.22 18.2.23 18.2.24 18.2.25 18.2.26 18.2.27 18.2.28 18.2.29 18.2.30 18.2.31

Title

Page

CCM Status REgister (CCM_CSR).............................................................................................................827 CCM Clock Swither Register (CCM_CCSR)..............................................................................................828 CCM Arm Clock Root Register (CCM_CACRR).......................................................................................830 CCM Bus Clock Divider Register (CCM_CBCDR)...................................................................................831 CCM Bus Clock Multiplexer Register (CCM_CBCMR)............................................................................834 CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)....................................................................836 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)....................................................................839 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)............................................................................842 CCM SSI1 Clock Divider Register (CCM_CS1CDR)................................................................................845 CCM SSI2 Clock Divider Register (CCM_CS2CDR)................................................................................846 CCM D1 Clock Divider Register (CCM_CDCDR)....................................................................................848 CCM HSC Clock Divider Register (CCM_CHSCCDR).............................................................................850 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)............................................................................851 CCM Serial Clock Divider Register 3 (CCM_CSCDR3)............................................................................853 CCM Serial Clock Divider Register 4 (CCM_CSCDR4)............................................................................854 CCM Divider Handshake In-Process Register (CCM_CDHIPR)...............................................................855 CCM DVFS Control Register (CCM_CDCR).............................................................................................857 CCM Low Power Control Register (CCM_CLPCR)........................

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