improving system performance and longgyevity with a new ... · nand block size trend epm = 128...

Improving System Performance and Longevity with a New NAND Flash g yArchitecture

Jin-Ki KimVi P id t R h & D l tVice President, Research & Development

MOSAID Technologies Inc.

Santa Clara, CA USAAugust 2009 1

Agenda

Background

Technical InnovationsTechnical Innovations

Solutions for Emerging Applications

Summary


NAND Technology Timeline

NAND Cell Invented

2Mb NAND Prototype & 1st Specification

Entered Gb Flash Era(1Gb NAND Flash Developed in 90nm)

SSD Emerged(8Gb SLC & 16Gb MLC in 50nm)

1984 1987 1992 1995 2002 2005 2007 2009

MCL (2bits/cell) for Mainstream

Confirmed NAND Technology

Key Circuit Techniques (Self boosting ISSP)

3bits/cell & 4bits/cell(32Gb MLC in 34nm)Mainstream

(4Gb SLC & 8Gb MLC in 65nm)

NAND Technology& Manufacturability

(Self-boosting, ISSP) Reported(32Mb NAND Developed)

(32Gb MLC in 34nm)

NAND Flash ProgressionDensity

The single-minded focus on bit density

32Gb MLC

improvements has brought Flash technology to current multi-Gb NAND devices

8Gb MLC

16Gb MLC

2Gb SLC

4Gb MLC

1Gb SLC1Gb SLC


120nm 90nm 73nm 65nm 51nm 34nm

Process Technology

NAND Architecture Trend

Primary focus is density for cost and market adoptionadoptionPage-based program and block-based erase

1 2 4B: # of Bitline/Page Buffer

1 2 3A: # of Bit/Cell 4

512B 2KB 4KB 8KB 16KBD: Page Size

8 16 32 64C: # of Cell/NAND String

512B 2KB 4KB 8KB 16KBD: Page Size

Block Size = (A * B * C) * D


( )Erase Program Mismatch (EPM) = A*B*C

NAND Block Size Trend

EPM = 128 (SLC) & 256(MLC)

Erase Program Mismatch (EPM) is a key parameter to degrading write efficiency (i.e. increase write amplification factor)

512KB

8Gb/16Gb/32GbMLC

• 64 cells/NAND• 8KB Page Buf.• 2 BLs/PB

512KB

8Gb/16Gb/32GbMLC


256(MLC)factor)

256KB

2Gb/4Gb/8GbMLC

256KB

2Gb/4Gb/8GbMLC

EPM = 64 (SLC) & 128(MLC)

128KB4Gb/8Gb/16Gb

128KB4Gb/8Gb/16Gb

EPM = 16

EPM = 32

4KB8KB

16KB

8Mb/16Mb 32Mb/64Mb128Mb/256Mb/512Mb

1Gb/2Gb/4Gb

4KB8KB

16KB

8Mb/16Mb 32Mb/64Mb128Mb/256Mb/512Mb

1Gb/2Gb/4GbEPM = 8


90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 • 8 cells/NAND• 512B Page Buf.

• 16 cells/NAND• 512B Page Buf.

• 16 cells/NAND• 512B Page Buf.• 2 BLs/PB



90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 07 08 09 10 • 8 cells/NAND• 512B Page Buf.

• 16 cells/NAND• 512B Page Buf.

• 16 cells/NAND• 512B Page Buf.• 2 BLs/PB



NAND Challenges in Computing Apps

100KSLC (1bit/cell)

Cell Endurance: # of Reprogram Cycles

10years

Data Retention: Ability to Retain Charge

100K

MLC (2bi / ll)

10years

10K

5K

MLC (2bits/cell)

2.5years

5years

2002 2006 2007 2008 2009 2010

90 60 0 40 30 20

3K

1K

Year 2002 2006 2007 2008 2009 2010

90 60 0 40 30 20

1years

Year

90nm 60nm 50nm 40nm 30nm 20nmTech. 90nm 60nm 50nm 40nm 30nm 20nmTech.

Reliability degradation combined with the current NAND architecture trend introd ces a negati e impact on comp ting applications


trend introduces a negative impact on computing applications

Flash System Lifetime Metric

System lifetime heavily relies on NAND hit t d f tarchitecture and features

Write Efficiency = Total Data Written by Host

Total Host Writes = NAND Endurance Cycle

Total Data Written to NAND

Total Host Writes NAND Endurance Cycle* System Capacity* Write Efficiency* Wear Leveling Efficiencyg ff y

System Lifetime = Total Host WritesHost Writes per Day


Host Writes per Day

NAND Architecture Innovation Current NAND Flash ArchitectureCurrent NAND Flash Architecture

Unit Block

Plane 1 Plane 2

Shared Page Buffer

A: # of Bit/CellD: Page (buffer) Size

# f / ff


C: # of Cell/NAND StringB: # of Bitline/Page Buffer

Block Size = (A * B * C) * D

NAND Architecture Innovation FlexPlane with 2-tier Row Decoder SchemeFlexPlane with 2 tier Row Decoder Scheme

Smaller & Flexible Page Size (2KB/4KB/6KB/8KB)Smaller & Flexible Erase SizeLower power consumption due to segmented pp-wellExtend system lifetime

Fl PlFlexPlane

NAND Cell Array on Sub PP-Well

t Row

Dec

oder


t Row

Dec

oder


t Row

Dec

oder


t Row

Dec

oder

Row

Dec

oder

Seg

men

t

Seg

men

t

Seg

men

t

Seg

men

tG

loba

l

Santa Clara, CA USAAugust 2009

10

2KB Page Buffer 2KB Page Buffer 2KB Page Buffer 2KB Page Buffer

FlexPlane Operations

NAND Architecture Innovation2-Dimensional Page Buffer Scheme2-Dimensional Page Buffer Scheme

Higher Performance

Upper PlaneLower Power ConsumptionHigher Yield

2-Dimensional Page Buffer(Shared Page Buffer)

Lower Plane0.5x Bitline Length compared to conventional NAND architecture


Micron 32Gb NAND Flash in 34nm, 2009 ISSCC

NAND Core InnovationPage-pair & Partial Block ErasePage-pair & Partial Block Erase

Minimize Erase Program Mismatch (EPM)Improve write efficiency

Block Erase Partial Block Erase Page-pair Erase

• MOSAID’s Erase Scheme*


* Jin-Ki Kim, “Low Stress Program and Single Wordline Erase Schemes for NAND Flash Memory”, IEEE NVSMW Aug. 2007.

NAND Core InnovationLower Operating VoltageLower Operating Voltage

2.7 ~ 3.6V 2.7 ~ 3.6V 3.3V

H.V. Gen

Core and Peri.

H.V. Gen

Core and Peri.

H.V. Gen

Core and Peri.

1.8V

Core and Peri.

I/O

Core and Peri.

I/O

1.8VCore and Peri.

I/O

• MOSAID’s Low Stress Program Scheme*


* Jin-Ki Kim, “Low Stress Program and Single Wordline Erase Schemes for NAND Flash Memory”, IEEE NVSMW Aug. 2007.

HyperLink (HLNAND™) Flash

Monolithic HLNAND• Device interface • Fully independent bank operations

NewDevice

independent of memory technology and density

• Packet protocol with low pin count

• Configurable data width link hit t

• Multiple, simultaneous data transactions

• Data throughput independent of core operations

• Device architecture for performance DeviceArchitecture

architecture • Flexible modular command

structure• Simultaneous Read and

Write• EDC for command and

and longevityFlexPlane ArchitectureTwo-dimensional Page BufferTwo-tier Row Decoder

New LiArch ew W

rite

eme• EDC for command and ECC for registers

• Daisy-chain cascade with point-to-point connection of up to virtually Unlimited number of devices

• NAND flash cell technology• Page/multipage erase function• Partial block erase function• Low stress program scheme

Linkrchitecture

NewSchem

MCP HLNAND

p g• Random page program in SLC• Low Vcc operations


MCP HLNAND

HyperLink Interface

Point-to-point ring topology• Synchronous DDR signaling with source termination only• Up to 255 devices in a ring without speed degradation• Dynamically configurable bus width from 1-8 bitsy y g• HL1 parallel clock distribution to 266MB/s• HL2 source synchronous clocking to 800MB/s, backward

compatible to HL1

HLNAND HLNAND

ControllerHostInterface

HLNAND HLNAND


64Gb MLC HLNAND MCP

HLNAND bridge chip MCP with 4-NANDs stackedHL1 (DDR-200/266) using NAND in MCP - fully compliant to HLNAND spec


12 x 18 100-Ball BGA

HLNAND Flash Module (HLDIMM)

Use cost effective DDR2 SDRAM 200-pin SO-DIMM f f t d k tDIMM form factor and sockets 8 x 64Gb or 8 x 128Gb HLNAND MCP (4 on each side)each side)


HLDIMM Port Configuration

Four independent HyperLink interface (266MB/s)Aggregate bandwidth of 1066MB/s regardless of # of module


HLDIMM Pin Assignment

All high speed signals fully shielded with 1:1 ratio between signal and power/groundbetween signal and power/ground6 Vss, 3 Vdd (1.8V), 3 Vdd3 (3.3V) per channel in/outVref and Reset pins shared by all channelsp y5 pin SPD interfaceForward compatible to HL2 800MB/s source synchronous clocking

r 1 r 2 r 3 r CK

O#

r KO r 4 r 5 r 6 r 7 r ncC

SO r 0r DSO

pow

eD

1/Q

1po

we

D2/

Q2

pow

eD

3/Q

3po

we

CK

#/C

pow

e

CK

/CK

pow

eD

4/Q

4po

we

D5/

Q5

pow

eD

6/Q

6po

we

D7/

Q7

pow

eC

E#/n

CSI

/Cpo

we

D0/

Q0

pow

eD

SI/D


channel input/output pin assignment

System Configurations with HLDIMM

CH0 i HL1HL1 HL1HL1

Non-Interleave - 1066MB/s Aggregate Throughput

CH0 in MCPsMCPs

CH0 out HL1MCPsHL1

MCPs

CH1 in HL1MCPsHL1

MCPs

MCPsMCPs

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

CH0 in HL1MCPsHL1

MCPs

CH0 out HL1MCPsHL1

MCPs

CH1 i HL1HL1

controller

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1 MCPsMCPs

CH1 out HL1MCPsHL1

MCPs

HLDIMM

MCPsMCPs

HL1MCPsHL1

MCPs

HLDIMMHLDIMM

Loop-around empty socket

CH1 in HL1MCPsHL1

MCPs

CH1 out HL1MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HLDIMM

CH0 in HL1MCPsHL1

MCPsHL1

MCPsHL1

MCPsHL1

MCPsHL1

MCPsHL1

MCPsHL1

MCPs

HL1MCPs

HL1MCPs

HL1MCPs

CH0 in HL1MCPs

CH0 out HL1MCPs

HL1MCPsCH2 in

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

CH0 in HL1MCPsHL1

MCPs

CH0 out HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPsCH2 in

Interleave - 2133MB/s Aggregate Throughput

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

HL1MCPs

HL1MCPs

HL1MCPs

HL1MCPs

HL1

CH1 in HL1MCPs

CH1 out HL1MCPs

HL1MCPs

HL1MCPs

HL1

CH2 out

CH3 in

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

CH1 in HL1MCPsHL1

MCPs

CH1 out HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1MCPsHL1

MCPs

HL1HL1

CH2 out

CH3 in


CH0 out HL1MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HLDIMM

HL1MCPs

HLDIMM

HL1MCPs

HLDIMM

CH3 outHL1

MCPsHL1

MCPs

HLDIMM

HL1MCPsHL1

MCPs

HLDIMM

CH3 out

HLDIMM PerformanceCapacity, Bandwidth and Random IOPSCapacity, Bandwidth and Random IOPS

Capacity & Bandwidth vs. # of Modules Random IOPS vs. # of Modules


HLDIMM Packing Density

Fully populated memory capacity of 512GB or 1TB i hi d i 64GB d 128GB1TB is achieved using 64GB and 128GB HLDIMM modules within only 60cm2 of motherboard areamotherboard area.


Summary

The driving forces in future Flash memory are the memory architecture & feature innovation that will support emerging system

hit t d li tiarchitectures and applications

Using HLNAND Flash Storage Class MemoryUsing HLNAND Flash, Storage Class Memory is viable today using proven NAND flash technologytechnology


Resource for HLNAND Flashwww.HLNAND.comwww.HLNAND.com

Available• 64Gb MLC MCP sample• 64GB HLDIMM sample6 G sa p e• Architectural Specification• Datasheets

White papers• White papers• Technical papers• Verilog Behavioral model


improving system performance and longgyevity with a new ... · nand block size trend epm = 128...

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