improvement of the operating efficiency and initial costs of a utility-scale photovoltaic

8/12/2019 Improvement of the Operating Efficiency and Initial Costs of a Utility-Scale Photovoltaic

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A Thesis

entitled

Improvement of the Operating Efficiency and Initial Costs of a Utility-Scale Photovoltaic

Array through Voltage Clamping

by

Penghao Chen

Submitted to the Graduate Faculty as partial fulfillment of the requirements for the

Master of Science Degree in Electrical Engineering

___________________________________Dr. Roger King, Committee Chair

_____________________________________Dr. Thomas Stuart, Committee Member

_____________________________________Dr. Richard Molyet, Committee Member

______________________________________Dr. Patricia R. Komuniecki, Dean

College of Graduate Studies

The University of Toledo

May 2012


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Copyright 2012, Penghao Chen

This document is copyrighted material. Under copyright law, no parts of this

document may be reproduced without the expressed permission of the author.


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An Abstract of

Improvement of the Operating Efficiency and Initial Costs of a Utility-Scale

Photovoltaic Array through Voltage Clamping

By

Penghao Chen

Submitted to the Graduate Faculty as partial fulfillment of the requirements for theMaster of Science Degree in Electrical Engineering

The University of ToledoMay 2012

The utility-scale PV array systems must be designed to operate normally at maximum

power point VMPP, but must also withstand the very high voltage level of open-circuit

voltage VOCwhich seldom occur in reality operation, if they are shut down or otherwise

power grid unable to receive the full output power from PV array. According to the

characteristics of solar cells, the necessity for safe withstand of a voltage level about 50-

percent greater than the normal operating level exacts penalties in the costs of the

ancillary components; in particular, in the inverter.

The proposed project is to design build and test an electronic shorting switch suitable

for use in a PV utility-scale power generation application. The electronic shorting switch

can able to prevent the output voltage of PV system increasing too far from V MPP.

Therefore, it is anticipated that the ability to design the PV system for a maximum

voltage only marginally greater than the normal operating voltage VMPPwill reduce the

initial installation cost of PV array system.


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For my parents, family, and friends


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Acknowledgements

I sincerely thank my advisor Dr. Roger King for giving me the opportunity to pursue

my research under his guidance. It has been a great learning experience working with

him. I would also like to express my deepest gratitude towards him for offering

instructive advice at all times, treating me with endurance, and constantly pushing me to

do better every time.

Last, but not the least, I thank my parent, family, and friends who have been a

constant source of encouragement and support for me throughout my journey in the

Masters Degree program.


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Table of Contents

Abstract...iii

Acknowledgements ............................................................................................................. v

Table of Contents ............................................................................................................... vi

List of Tables ..................................................................................................................... ix

List of Figures .................................................................................................................... ix

List of Acronyms .............................................................................................................. xii

1 Introduction ............................................................................................................... 1

1.1 Background ................................................................................................ 1

1.2 Research Objectives .................................................................................. 3

1.3 Structure of the Thesis............................................................................... 4

2 Solar Panel Characteristics ....................................................................................... 5

2.1 Key Types of Solar Cell ............................................................................ 5

2.1.1 Crystalline Materials ...................................................................... 5

2.1.2 Thin Film Materials ....................................................................... 7

2.2 I-V Characteristics of Solar Cell ............................................................... 9

2.2.1 Maximum Power Point Tracking ................................................... 9

2.2.2 PV Array under Different Conditions .......................................... 10

2.2.3 I-V Characteristics of Other Kind of Solar Cells ......................... 13


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3 Utility-Scale PV Array Organization ...................................................................... 15

3.1 Introduction of Solar Array ..................................................................... 15

3.2 PV System Architecture .......................................................................... 18

3.2.1 Centralized Inverters .................................................................... 18

3.2.2 String Level Inverters .................................................................. 19

3.2.3 Multistage Inverter ....................................................................... 20

3.2.4 Micro- Inverters ........................................................................... 20

3.3 Array Voltage Level .............................................................................. 21

3.3.1 Rating Requirement ..................................................................... 21

3.3.2 Conduction Loss .......................................................................... 22

4 Proposed Electronic Shorting Switch ..................................................................... 24

4.1 Proposed the ESS to Restrict Voltage Range ........................................ 27

4.2 Design the string level Electronic Shorting Switch ............................... 29

4.2.1 Main Power Circuit Design ........................................................ 31

4.2.2 Drive Circuit of SCR and IGBT ................................................. 33

4.2.3 Power Supply Circuit .................................................................. 34

4.2.4 Microcontroller Design....34

5 Testing of Proposed Circuit ...................................................................................... 38

5.1 The Test System ..................................................................................... 38

5.2 Results and waveforms .......................................................................... 39

6 Conclusion and Future Work .................................................................................. 45

6.1 Conclusion..45


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6.2 Future Works.....46

References..48

A Schematic of string-level electronic shorting switch.53

B Program listing for microcontroller...54


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List of Tables

2.1 PV panel voltage characteristics .......................................................................... 13

2.2 PV panel current characteristics ........................................................................... 14

3.1 Fuse price of different voltage-rated and current from Digikey .......................... 22

3.2 International rectifier IGBT parameter.....23

5.1 Parameter of the testing system ........................................................................... 39


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List of Figures

1-1 The Nextronex Ray-Max system is a utility-scale solar array ............................... 2

2-1 Currentvoltage and powervoltage characteristics of solar cell ........................... 9

2-2 I-V characteristics of a Solarex MSX polycrystalline silicon photovoltaic module

for various values of irradiance S at a temperature of 25 C. ..................................... 11

2-3 I-V characteristics of a Solarex MSX polycrystalline silicon photovoltaic module

for various values of temperature T at an irradiance of 1000 W/m2. .......................... 12

3-1 Structure of a PV module with 72 cells connected in series [28] ........................ 16

3-2 Structure of a PV string [28] ................................................................................ 16

3-3 Structure of PV array using PV strings and combiner box [28] .......................... 17

3-4 The three types of PV array configuration .......................................................... 18

3-5 Central inverter with large scale array configuration .......................................... 19

3-6 Layout of the string inverter ................................................................................ 19

3-7 Multistage inverter configuration of PV modules ............................................... 20

3-8 Micro-inverter connected to each PV modules ................................................... 21

4-1 Design maximum voltage in I-V curve of solar cell ........................................... 25

4-2 Schematics of PV System with electronic shorting switches at each PV string.. 26

4-3 Schematic of PV system with electronic shorting switch (ESS) at inverter side 27

4-4 Schematic of electronic shorting switch ............................................................... 28

4-5 Schematic of the main power circuit ................................................................... 30


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4-6 Schematic of drive circuit of SCR ....................................................................... 32

4-7 Schematic of drive circuit of IGBT ..................................................................... 33

4-8 Schematic of power supply circuit ...................................................................... 34

4-9 Schematic of microcontroller .............................................................................. 35

4-10 Flowchart of program ........................................................................................ 37

5-1 Schematic of ESS testing system......................................................................... 39

5-2 Waveform of ESS when SCR fires, channel 1: solar string voltage, 200 V/div,

channel 2: string current, 10 A/div, time division: 1 ms/div ...................................... 40

5-3 Waveform of ESS when IGBT trigger, channel 1: solar string voltage, 100V/div,

channel 2: capacitor C1current, 5A/div, time division: 50 s/div .............................. 41

5-4 Waveform of SCR fired, channel 1: DC gate current of SCR Igt, 500 mA/div,

channel 2: Anode Current of SCR, 10 A/div, time division 10 s/div ....................... 41


channel 2: anode current of SCR, 10 A/div, time division 50 s/div ......................... 43


channel 2: voltage at C3, 5 V/div, time division 50 s/div ........................................ 43


channel 2: anode-cathode voltage, 200 V/div, time division 50 s/div ...................... 44


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List of Abbreviations

a-Si .............................Amorphous SiliconA/D .............................Analog to DigitalAC ..............................Alternating Current

BL array .....................Bridge-Linked Array

c-Si .............................Single-crystal silicon

CdTe ...........................Cadmium TellurideCuInSe2, or CIS ..........Copper Indium Diselenide

DC ..............................Direct Current

ESS .............................Electronic Shorting Switch

GaAs ..........................Gallium Arsenide

IMPP.............................Maximum Power Point CurrentISC...............................Short Circuit CurrentIGBT ..........................Insulated Gate Bipolar Transistor

MPP............................Maximum Power PointMPPT .........................Maximum Power Point Tracking

poly-Si ........................Polycrystalline siliconP&O ...........................Perturb and ObservePV ..............................Photovoltaic

SCR ............................Silicon Controlled RectifierSP array ......................Series-Parallel ArraysSTC ............................Standard Test Condition

TCT array ...................Total-Cross-Tied Array

VMPP...........................Maximum Power Point VoltageVOC.............................Open Circuit VoltageV-I Characteristics .....Voltage-Current Characteristics


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Chapter 1

Introduction

The sun provides the light and maintains the essential energy cycles on earth. As a

ubiquitous source of energy, sunlight can be used in electricity production as well.

Photovoltaic (PV) or solar cells convert light into electricity by using the photoelectric

effect.

1.1 Background

In recent years, the interest in electrical power generation from renewable-energy

sources, like photovoltaic (PV) has boomed [1] [2].Since it is essentially inexhaustible

and environment-friendly, the benefits of power generation from this source are widely

accepted. Renewable-energy sources from which it is possible to obtain electricity has

been one of the most active research areas in the past decades, both for grid-connected

and stand-alone applications [3] [4]. A PV array is a flexible power generation method

which is applicable to both small and large power generation plants; i.e., plants that

generate from less than 3 kW to more than 100 kW [5]. Photovoltaic conversion of solar

energy will be one of the most promising ways of meeting the increasing energy demand

in the future.


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Research over the past decades has been directed at the utility-scale solar array. This

has resulted in development, design, construction, and operation of utility-scale solar

arrays such as that shown in Figure 1.1 [6]. The term utility-scale is used to refer to

arrays of solar panels with ratings exceeding hundreds of kilowatts electrical power, and

designed for direct interface to the electric grid, indicative of the potential for

photovoltaic as a source of electrical power generation.

Figure 1.1 The Nextronex Ray-Max system is a utility-scale solar array

The utility solar PV array farms have those major advantages:

Solar energy is ideal power resource for satisfying the demand which utilities require

peak power generators. When air-conditioning loads are ponderous in the hot summer

afternoon, solar power reaches to maximum outputs at the same time.

The utility power generators are extremely large. If one of these traditional generators

failed for some reasons, the entire grid can be affected tremendously. However, due to

distributed nature of solar generators, the effect on the entire grid is minimal, if one PV

panel goes down. [7].


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Solar generators are much cleaner than conventional combustion generators. Solar

farms may be built very close to city load centers because their presence is minimally

harmful to the local environment. They not only reduce the transmission line burden, but

increase the efficiency because of minimizing the conduction losses [8].

1.2 Research Objectives

Most of the cost of electricity from solar array is the capital cost of installation. The

operating costs are much smaller. Because of the very high power level of the utility scale

solar array which is measured in megawatts, the equipment and components need to be

designed to operate under very high voltage. In the PV system all the equipment like

inverters, disconnect switches, fuses, diodes and other components must withstand the

full open-circuit voltage of the array. The high voltage level rating exacts penalties in the

costs and efficiencies of the ancillary components. People will need to pay the extra

money on those components, although most of the time the voltage of the PV array

wouldnt reach to that point in normal operation.

This motivation of this thesis is to design an electronic shorting switch which

prevents the array from operating at a voltage much higher than the normal rated voltage

of the system. When the power grid is not able to receive array power output for reasons

which may include grid failure, inverter failure, or shut-down for maintenance, the

electronic shorting switch turns on. The array voltage is clamped to zero; the array

current is its short circuit current under the prevailing condition. It is anticipated that

addition of the shorting switch will allow to design of the system for a maximum voltage

only marginally greater than the normal operating voltage. The benefit of narrowing the


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range between the VMPPand VOCincludes increasing the energy collection efficiency and

minimizing the copper conduction losses.

1.3 Structure of the Thesis

Chapter 2 provides an overview of basic theory surrounding the principal topics about

characteristics of solar cell. Chapter 3 discusses the organization of the PV system

including the configuration of PV array and different types of PV inverters. Chapter 4

discusses the problem of high voltage, proposes a novel method for solving the problem

by the electronic shorting switch and thoroughly explains how to design the electronic

shorting switch including the circuit board and C code. Chapter 5 shows the testing

system and waveform of electronic shorting switch. Conclusions and future work are

documented in Chapter 6.


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Chapter 2

Solar Panel Characteristics

2.1 Key Types of Solar Cell

Solar cells are the most fundamental element in PV array system, which are made of

different semiconductor materials. The major types of material are crystalline materials

and thin films. Because of their various natural characteristics of material, they are

varying from each other in terms of light absorptivity, energy conversion efficiency, and

cost of production [9].

2.1.1 Crystalline Materials

a. Single-crystal silicon (c-Si)

The most common material of solar cell is single-crystal silicon sell, which has

dominated the market in last decades [10]. Because of the uniform molecular structure of

single-crystal silicon, it has very high energy conversion efficiency ranging between 15-

20%. Beside the efficient energy conversion, single-crystal silicon modules are very

reliable for outdoor power application. However the manufacturing cost of single-crystal


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silicon cell is extremely high because of its time-consuming and costly technique in

manufacturing processes.

b. Polycrystalline Silicon (poly-Si)

Polycrystalline silicon is a material consisting of multiple small grain silicon crystals,

separated by the grain boundaries. The flow of the electrons impeded by the small grain

boundaries in polycrystalline silicon, thus the efficiency of polycrystalline silicon cell is

lower than the single crystalline silicon cell [11]. The energy conversion efficiency of

polycrystalline silicon cell ranges between 10-14%. Because polycrystalline silicon

material is stronger compared with single-crystalline silicon, it can be cut into one-third

the thickness of single-crystalline silicon material. This can reduce the cost but this

advantage is offset by the lower cell conversion efficiency [12].

c. Gallium Arsenide (GaAs)

The compound semiconductor GaAs has a crystal structure similar to that of silicon,

is made of two elements: gallium (Ga) and arsenic (As). GaAs solar cell has high level of

light absorptivity and very high energy conversion efficiency about 25% to 30%.

However the cost of GaAs solar cell is extremely expensive, because of it needs to grown

on a very expensive single crystal substrate which makes the manufacturing cost higher

than crystalline silicon. Due to its high resistance to heat and strong resistance to

radiation damage, GaAs solar cell has been widely used in concentrator system and the

space applications [13].


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2.1.2 Thin Film Materials

In the thin-film PV cell technology, because a very thin layer of semiconductor

materials is deposited on a low-cost supporting substrate, the less PV semiconductor

material and cheaper substrate save the manufacturing cost significantly comparing to the

crystalline silicon [14]. Thin-film materials have higher light absorption efficiency than

crystalline materials. However the energy conversion efficiency is the main drawback

because of lacking the one single crystal structure.

a. Amorphous Silicon (a-Si)

Amorphous silicon PV solar cell has dominated the thin-film material recently,

because of its advantages. Amorphous silicon has very high level light absorptivity, thus

only an extremely thin layer of a-Si material needs to be deposited on very cheap

substrate, like plastic, glass and metal. Beside the manufacturing process is easier and

uses less energy than the single crystalline silicon. Thus the total materials costs and

manufacturing costs are lower than those of crystalline silicon cells [15].

Despite its promising economic advantages, the amorphous silicon solar cell suffers

from the poor cell energy conversion efficiency ranging between 5-9%. It is the main

drawback that needs to be overcome. And another drawback of a-Si is not very reliable

operating outdoor, since the energy efficiency degrades during long time of exposure to

direct sunlight [16].


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b. Cadmium Telluride (CdTe)

A compound semiconductor made of two elements: cadmium (Cd) and tellurium (Te),

CdTe is also widely used in the world. It has a high level light absorptivity which can

absorb 90% of the solar spectrum by just using a micrometer thick of CdTe [17]. It can be

mass manufactured by relatively easy and cheap processes such as high-rate evaporation,

spraying or screen printing. However, CdTe thin film share the same problem with the a-

Sic thin film: low energy conversion efficiency. The energy efficiency of a CdTe

commercial module is about 9%. And the instability of module performance also is one

of the major drawbacks of using CdTe for PV arrays.

c. Copper Indium Diselenide (CuInSe2, or CIS)

CIS thin film has been paid much attention in the thin-film industry recently, which is

compound of copper, indium and selenium. Due to its not only very high level light

absorptivity, like a-Si and CdTe thin-film, but high energy conversion efficiency closing

to the polycrystalline silicon solar cell, CIS thin film is one of the best candidate among

all the existing thin materials to manufacture PV module or array [18].

CIS thin film solar cell is a promising and competitive choice for the future solar

industry, because the high energy conversion efficiency and reliable operating outdoor

during long time. However, CIS is a complex material which is difficult to manufacture.

Also, an extremely toxic gas which is harmful to human health can be involved in the

manufacturing process.


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2.2 I-V Characteristics of Solar Cell

2.2.1 Maximum Power Point Tracking

In order to harvest the maximum possible power, during moment to moment

variations of temperature, irradiance, shading and other factors, we need to adjust

automatically to get maximum power point in the use of solar panels [19] [20]. Since the

solar cells have a complex relationship between solar irradiation, temperature and other

factors, it has a unique non-linear output characteristic known as the "I-V curve" in

Figure 2.1. It is the purpose of the MPPT system to sample the output of the solar cells

and adjust the operating point to obtain maximum power for any environmental

conditions [21].

Figure 2.1 Currentvoltage and powervoltage characteristics of solar cell

The Figure 2.1 shows us classical characteristics of power curve for a polycrystalline

silicon PV cell. The maximum power point tracking (MPPT) problem is to automatically

find the voltage VMPP or current IMPPso that the PV array will operate at the maximum

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0

0.5

1

1.5

2

2.5

3

3.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

CellPower(W)

CellCurrent(A)

Cell Voltage (V)

Current

Power


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power point output MPPunder a given temperature and irradiance [22]. For example, the

perturb and observe (P&O) technique is widely used in maximum power point tracking

[23]. The method is based on the fact that if the power point laid on the left of the MMP,

incrementing the voltage increases the power, and on the right of MMP, decrementing the

voltage increase the power. The process is repeated periodically until the MPP is reached,

and then the system oscillates about the MPP.

2.2.2 PV Array under Different Conditions

The electrical characteristics of a PV array will show significant variance with

temperature and insolation. Date sheets typically describe performance at standard test

condition (STC) of 25 C and 1000 W/m2of insolation. A PV array design must consider

the full range of expected environment conditions [24].

a. Insolation

PV solar module performance is irradiance dependent. The terms one sun are ways to

describe the irradiance conditions at STC (1000 W/m2). Sunlight intensity varies from

zero to one sun or a little more than one sun in some locations during one day. This

means that PV output current can vary from zero to full array current rating or more in

everyday, depending on different situation, like season, weather conditions, and dust,

irradiance. The short-circuit current of polycrystalline silicon solar module can increase

almost 5 times for changing the irradiance S changes from 200 W/m 2 to 1000 W/m2 in

Figure 2.2. However, the open circuit voltage only increases by 7.4% under the same

condition [25].


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Figure 2.2 I-V characteristics of a Solarex MSX polycrystalline silicon photovoltaicmodule for various values of irradiance S at a temperature of 25 C.

b. Temperature

The open-circuit voltage (VOC) varies with temperature, increasing as temperature

decreases, and showing in Figure 2.3 [26]. It is plausible that the PV array works at the

normal operating temperature of 40-50 C or higher when ambient temperature is around

25 C, and works at operating temperature significantly below 0 C in the winter [27].

For example, a typical polycrystalline silicon module will have a voltage coefficient of -

0.29%/C. A PV system with an open-circuit voltage of 1000 volts at 25 C might be

exposed to ambient temperatures of -30 C in winter. It can generate open-circuit

voltages of 1160 volts. This voltage which may occur at a cold sunny day substantially


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exceeds the capability of 1000-volt. It will require design for higher than 1000 V, even

though this condition will seldom occur in normal operation. In polycrystalline silicon

PV modules, the short circuit current increases with the ambient temperature increases. A

classical temperature coefficient might be 0.1%/C. If the module operating temperature

was 75 C, the short-circuit current would be 5% greater than the rated value.

Figure 2.3 I-V characteristics of a Solarex MSX polycrystalline silicon photovoltaicmodule for various values of temperature T at an irradiance of 1000 W/m2.


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2.2.3 I-V Characteristics of Other Kind of Solar Cells

VMPPis the design voltage for PV array system. The most frequently occurring range

of temperature under full load and insolation must be considered here. The worst-case for

VOCoccurs when arrays themselves are unloaded at lowest expected ambient temperature.

Not only the polycrystalline silicon solar cell has the non-linear I-V characteristics, but

also other six kinds of material solar cells have the similar I-V characteristics. So their

unique I-V characteristics cause the same voltage issue with the polycrystalline silicon

solar cell.

Table 2.1 PV panel voltage characteristicsType of Solar Cells VMPP

(45 C)

VOC

(-30 C)

VOC/ VMPP

c-Si (AstroPower AP-1106) 14.1V 25.4V 1.8

poly-Si (Solarex MSX 5) 15.2V 25.0V 1.65

GaAs (Spectorlab GaAs/Ge SingleJunction Solar Cell)

0.862V 1.12V 1.3

a-Si (DuPont Apollo DA100) 69V 116.5V 1.69

CdTe (First Solar FS-270) 62.2V 97.7V 1.57

CIS (Wrth Solar WS 11007/80) 33.9V 52.75V 1.56

In the reality, when the PV array system operates, the ambient temperature will

increased by conduction heat. Then the normal operating voltage will be lower than the

maximum power point voltage under the STC. And in the cold sunny day, PV array will

reach the worst-case open-circuit voltage at the extremely cold ambient temperature and

no load condition, which may be 1.5 times higher than the normal operating voltage in

the Table 1. Therefore, all of the solar array systems not only need to operate efficiently


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under the normal operating voltage, but also need to withstand the worst-case open-

circuit voltage.

Table 2 shows the current data of the same PV panels used in the Table 1, which

illustrates that the PV short circuit current are not excessively greater than their IMMP. DC

bus conductors will generally be sized for low energy loss at IMPP, so it is likely that ISC

will be well within the thermal limits for the bus. These observations lead to the proposed

method of achieving a shutdown condition for a solar array in full sunlight by application

of a short-circuit using a shunt switch, rather than requiring the dc bus to withstand the

open-circuit voltage.

Table 2.2 PV panel current characteristicsType of Solar Cells IMPP

(45 C)

ISC

(45 C)

ISC / IMPP

c-Si (AstroPower AP-1106) 6.60A 7.51A 1.14

poly-Si (Solarex MSX 5) 0.27A 0.294A 1.09

GaAs (Spectorlab GaAs/Ge SingleJunction Solar Cell)

28.6mA 30.9mA 1.08

a-Si (DuPont Apollo DA100) 1.34A 1.69A 1.26

CdTe (First Solar FS-270) 1.07A 1.24A 1.16

CIS (Wrth Solar WS 11007/80) 2.22A 2.53A 1.14


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Chapter 3

Utility-Scale PV Array Organization

Utility-scale PV systems use large number of solar panels and large amounts of land

area, which are laid out physically to minimize shadowing effects. They have the

concerns of lowering installation and maintenance costs by using the simplest possible

wiring structure and providing accessible test points for performance monitoring.

Because utility-scale PV systems are organized for relatively high operating voltage to

reduce copper cost and ohmic losses in the wiring, they are usually installed in areas with

restricted access. Thus, they have safety, standard compliance and fault protection

requirements which differ from roof-mounted, commercial or residential PV systems.

3.1 Introduction of Solar Array

3.1.1 Photovoltaic Modules

Because the power output of single PV cell is very small, PV cells are need to

connected together to form larger units called PV modules or panels in Figure 3.1. A PV

module consists of many PV cells connected in series to produce a higher voltage, and

then in parallel to increase current [28]. In order to protect solar module from water or


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dust, the module is sealed in an aluminum frame with glass on the top surface and

waterproof material on the back surface. And some commercial PV module paralleled

with a diode in the back to minimize the effect of shading.

Figure 3.1 Structure of a PV module with 72 cells connected in series [28]

3.1.2 Photovoltaic Strings

In order to reach the array operating voltage needed for utility scale, PV strings have

many PV modules connected in series to form a PV string in Figure 3.2. In the utility-

scale PV system, the output voltage of one PV string can reach to 1000V.

Figure 3.2 Structure of a PV string [28]

3.1.3 Photovoltaic Arrays

A PV Array consists of a number of individual PV strings that have been wired

together in a series to reach the normal operating voltage level a particular system


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requires. These strings are then paralleled at combiner boxes, with the buses serving these

further paralleled to achieve the capacity of the complete PV array. A PV array is defined

here as the group of panels connected together for the purpose of MPP tracking. A typical

array is shown in Figure 3.3.

Figure 3.3 Structure of PV array using PV strings and combiner box [28]

Some novel array wiring practices have been proposed in [29] [30], but are not yet

used in practice to the nowadays technology. The series-parallel (SP) array

configuration of Figure 3.3 is most basic structure widely used nowadays. A total-cross-

tied (TCT) array is obtained from the simple SP array by connecting ties across each

row of junctions. The bridge-linked (BL) array is interconnected in bridge rectifier

fashion, as shown in the Figure 3.4. TCT and BL arrays can reduce the mismatch and

shading effects effectively, and minimize the appearance of local maxima around the

MPP in the power-voltage curve of the array. Simulation studies of the two novel arrays

suggest significant improvement of array energy harvesting. However, the installation


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appears too complicated to apply in the utility-scale array, and they also bring some

issues in the fault protection of the strings.

(a) A 2x6 series parallel array (b) A 2x6 total-cross-tied array

(c) A 2x6 bridge-linked array

Figure 3.4 The three types of PV array configuration

3.2 PV System Architecture

3.2.1 Centralized Inverters

The centralized inverter is the widely used circuit topology in the utility scale PV

array, as shown on Figure. 3.5. In this topology, the photovoltaic system includes a series

parallel connection arrangement, which is connected to a single large power inverter (or

multiple inverters) for the transfer the higher amount power to grid. Inverters are

connected to the PV array, via a network of DC runs, combiners, DC trunk lines, and re-

combiners. All strings are then connected in parallel to support high power to output. Its

cost is lowest in the utility scale PV array system technology. However, this technology

suffers from disadvantageous issues, including mismatch losses because of central

MPPT, low upgradability, and the difficulty of detecting a bad panel [33].


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...PV

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...

DC

AC

GridPV PV PVPV PV

PV PV PV PVPV PV

+

-

Central

Inverter

~

~

Figure 3.5 Central inverter with large scale array configuration

3.2.2 String Level Inverters

String level inverters are evolved from the centralized inverter topology, shown in

Figure. 3.6. This technology has a string level of PV modules connected in series with an

inverter. Because each string operates at its own MPP, the string level inverters can

reduce the mismatch power loss and increase the energy harvesting capability. However,

the increasing initial cost is the tradeoff of adding extra inverters in the PV array system,

comparing to the centralized inverter.

...PV

DC

AC

GridPV PV PVPV PV

+

-

String Inverter

~

~

...PV

DC

AC

PV PV PVPV PV

+

-

String Inverter

...PV

DC

AC

PV PV PVPV PV

+

-

String Inverter

Figure 3.6 Layout of the string inverter


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3.2.3 Multistage Inverter

The multi-string inverter can upgrade by adding a DC/DC converter at each string in the

centralized inverter topology, showing in Figure 3.7. It has the some advantages, when

different types PV panel, different power PV panel or different orientation are combined.

However, this situation usually wont happen in the utility-scale PV system, showing in

Figure 3.7. Since multiple power electronics stage happen in this topology, the multistage

inverter has some main disadvantages, like high cost and low reliability [32].

...PV

DCDC

PV PV PVPV PV

+

-

~

~

...PV

DC

DC

PV PV PVPV PV

+

-

DC

AC

Inverter

Figure 3.7 Multistage inverter configuration of PV modules

3.2.4 Micro- Inverters

In the micro-inverter topology, shown in Fig. 3.8, the inverter integrated with PV

module into one electrical device. Because MPP tracking operates at each individual PV

module, this inverter architecture can easily solve the mismatch problem and increase the

energy harvesting ability. This technology is seldom appropriate for utility-scale PV

array, because partial shading is not a critical issue. And due to its distributed installation,

the micro-inverter architecture is more complex and more expensive. Another drawback

is that it is too difficult to maintain [33].


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Grid

~

~

DC

AC

+-

Micro-

Inverters

DC

AC

+-

Micro-

Inverters

DC

AC

+-

Micro-

Inverters

DC

AC

+-

DC

AC

+-

Micro-

Inverters

DC

AC

+-

Micro-

Inverters

Figure 3.8 Micro-inverter connected to each PV modules

3.3 Array Voltage Level

Although there are some advantages for both the large array/central inverter and the

small array/distributed inverter approaches, this thesis concentrates on the large utility

scale PV array system, one composed of large numbers of panels connected by parallel

and series in both the x and y dimensions in an large open area. Because the total copper

volume required is proportional to the square of the operating current, there is a good

reason to design the system voltage as close as possible to the limits set by the panel

manufacturers or any applicable safety standards, thus minimizing the required current

and decreasing the conduction power losses.

3.3.1 Rating Requirement

The normal operation of PV system is at VMPP, which tends to spend much time at

elevated array temperature. However, the PV system must survive the worst case VOC,

which occurs at no load and low array temperature. One key requirement of V MPP is


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maximal power conversion efficiency, which means minimal inverter losses at this

operating point. High efficiency at utility power level suggests designing array for the

highest possible voltage. This implies the voltage difference between VMPPand VOCcan

become significant to increased design voltage requirements on all of the system

components.

Table 3.1 Fuse price of different voltage-rated and current from Digikey

Voltage

Current600V

1000V

15A $5.79 $31.59

20A $5.79 $34.83

Table 3 shows us a penalty caused by increasing rating voltage. We can see that the

price of fuse rises along with increasing rating voltage. And if the rating voltage

continues rising, the corresponding price of the fuse goes up certainly. And the number of

fuses will increase along with the power of PV array. Only the penalty cost of fuses

which is caused by the wide rating voltage is significant, not including the other

equipment and components, such as switches, circuit breakers and inverters.

3.3.2 Conduction Loss

The higher voltage rating will cause more conduction power losses because of the

characteristic of high power components, which semiconductors with higher voltage

ratings tend to have higher conduction voltage drop. It will hinder people to get pay back

from initial cost of PV array. It means that the power losses will increase the cost in

another way.


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From Table 4, it shows us that the power losses of the similar IGBT, which is the key

part in inverter, are rising according to the increasing VCE. Due to the increasing of VCE

from 330 V to 1200 V of the similar IGBT, VCE (ON), when they are conducting, will

changing from 1.35 V to 3.45 V, and the power losses are rising from 78 W to 330 W .

These conduction power losses will happen on the other components in the PV array

system.

Table 3.2 International rectifier IGBT parameter

Part

VCES

(V)

VCE(ON)

(V)

IC @ 25C

(A)

IC @ 100C

(A)

PD @25C

(W)

IRG7R313U 330 1.35 40 20 78

IRG4BC40WL 600 2.50 40 20 160

IRGP20B120U-E 1200 3.45 40 20 330
https://ec.irf.com/v6/en/US/adirect/ir?cmd=catSearchFrame&domSendTo=byID&domProductQueryName=IRG7R313Uhttps://ec.irf.com/v6/en/US/adirect/ir?cmd=catSearchFrame&domSendTo=byID&domProductQueryName=IRG4BC40WLhttps://ec.irf.com/v6/en/US/adirect/ir?cmd=catSearchFrame&domSendTo=byID&domProductQueryName=IRGP20B120U-Ehttps://ec.irf.com/v6/en/US/adirect/ir?cmd=catSearchFrame&domSendTo=byID&domProductQueryName=IRGP20B120U-Ehttps://ec.irf.com/v6/en/US/adirect/ir?cmd=catSearchFrame&domSendTo=byID&domProductQueryName=IRG4BC40WLhttps://ec.irf.com/v6/en/US/adirect/ir?cmd=catSearchFrame&domSendTo=byID&domProductQueryName=IRG7R313U


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Chapter 4

Proposed Electronic Shorting Switch

4.1 Proposed the ESS to Restrict Voltage Range

PV system will operate at the VMPP at most of time. However, in some special

condition, the output voltage from the PV array will reach the open circuit voltage VOC,

showing in Figure 4.1. In utility-scale solar array, all the equipment will need to

withstand of worst-case open-circuit voltage VOC which may be 50% higher than the

normal operating voltage. So the PV systems need to design based on V OC rather than

VMPP, which is the normal design operating condition for PV system and reach the PMPP.

The thesis is proposed to design the system for operation at or below the design

maximum voltage. An automatic shunt connected shorting switch is proposed to prevent

exceeding design Vmax.

Using a high voltage SCR as an electronic shorting switch to prevent the occasional

high voltage from happening, which also need to withstand the current rating, we can

limit the voltage range in a high voltage PV array. The shorting switch removes the

shaded part of Figure 4.1 from concern in the design process. The electronic shorting


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switch is designed for a predictable and manageable short current ISC, is typically not

dramatically bigger than IMPP.

Design

Max

Voltage

VMPP VOC

Figure 4.1 Design maximum voltage in I-V curve of solar cell

Because the I-V characteristic of the solar cell, if the DC current of PV array reach

the short current ISC, the voltage of PV array will decrease to zero, from Figure 2.1 in

Chapter 2. In a PV system, in order to get maximum power efficiency, the DC wirings

are needed to give low voltage drop, and all wirings, disconnects, and over current

devices have current ratings that exceed the short-circuit currents by at least 25%. It will

typically have no problem with ISC.Thus the ability of the system to operate at ISCis not a

cost factor.

Figure 4.2 shows us a reasonable location for installing electronic shorting switches

(ESS) on each PV string, and each string need to connect with a power diode in series if

not already present, which prevent ESS from shorting entire system, if only one fired.

When PV array operates improperly, the voltage goes high beyond the VMPP, the

electronic shorting switch will work at this point, and it will short out PV strings without

blowing the fuse. The bus voltage can be clamped until the PV system restarts in a


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26

midday shutdown. The advantage of this location is that the electronic shorting switches

provide a convenient means of disconnecting individual strings, and by their distributed

nature allow easy dissipation of their on-state conduction losses. The electronic shorting

switch can prevent the each PV string from the reaching the worst-case open circuit

voltage, and then make sure the whole PV array system around the VMPP. And this of

kind topology is also easy for people to find which one PV string need to be changed and

maintained.

......

......

......

......

......

......

.

.

.

PV

PV

PV

PV

PV

PV

-

Inverter

To GridDC

ACFilter

Transformer

ESSESS

...

+

.

.

.

PV

PV

PV

PV

PV

PV

......

......

......

......

......

......

.

.

.

PV

PV

PV

PV

PV

PV

ESSESS

.

.

.

PV

PV

PV

PV

PV

PV

......

......

......

......

......

......

.

.

.

PV

PV

PV

PV

PV

PV

ESSESS

.

.

.

PV

PV

PV

PV

PV

PV

Figure 4.2 Schematics of PV System with electronic shorting switches (ESS) at each PVstring

The Figure 4.3 shows us another topology for installing the ESS at the inverter side. It

can be installed into the inverter cabinet which can protect the switch safely, and the


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27

wiring is easier compare to the PV string level ESS, which can save the installment cost

dramatically. When the voltage increase beyond the VMPP, the entire PV system can be

clamped, however, it requires a larger current rating, which is difficult to dissipate the on-

state power loss when the switch remains closed for an indefinite time.

.

.

.

PV......

......

......

......

......

......

.

.

.

PV

PV

PV

PV

PV

PV

PV

PV

PV

PV

PV

-

Inverter

To GridDC

ACFilter

Transformer

...

+

ESS

.

.

.

PV......

......

......

......

......

......

.

.

.

PV

PV

PV

PV

PV

PV

PV

PV

PV

PV

PV

.

.

.

PV......

......

......

......

......

......

.

.

.

PV

PV

PV

PV

PV

PV

PV

PV

PV

PV

PV

Figure 4.3 Schematic of PV system with electronic shorting switch (ESS) at inverter side

4.2 Design the string level Electronic Shorting Switch

An electronic shorting switch (ESS) was designed for use in a system having normal

operation voltage 400V, open-circuit voltage 600 V and short current 13 A for one string.

The ESS was programmed to limit the actual system voltage to a Vmaxof 500 V, which

allows safe operation with 600 V rated components. Adopting the microcontroller to

control the ESS, we use the SCR to clamp the bus when the bus voltage rises to the


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trigger design maximum voltage Vmax. The whole schematic of electronic shorting switch

is presented in Figure 4.4.

The general requirements for the shunt switching device are summarized:

1) It must be very reliable, and preferably fail in a short-circuit condition.

2) Only unidirectional voltage block and current conduction is needed.

3) Switching and conduction losses are not relevant, except for design of its heat

removal system.

4) Low off-state leakage current.

5) Low (or zero) on-state gate power requirements.

Figure 4.4 Schematic of electronic shorting switch


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Several electronic devices were considered, but they each had some drawbacks.

Using just one IGBT, it can be turned on and off successfully provided there is a stable

source of power. Batteries or ultra-capacitors were considered, but neither was selected

due to concern about their ability to maintain bus clamping during a day-long utility grid

outage.

MCT is also the candidates of electronic shorting switch. It has some advantage to

clamp the voltage, because it can easily controlled by the external trigger and able to

maintain a latched condition without auxiliary power source. However, due to the

limitation of todays technology, we cannot find proper parts to satisfy this particular

design. The power JFET is also a promising candidate because of depletion-mode

characteristics, which allow it to be on with zero gate voltage.

4.2.1 Main Power Circuit Design

The Figure 4.5 shows the main circuit of the electronic shorting switch. The SCR Q1

is the ESS which needs to support the highest working bus voltage, and when triggered,

safely handle the panel short-circuit current. When the bus voltage of solar array rises

beyond the Vmax, the sensor circuit R1 and R2 will send signal to turn on the SCR, then

the voltage of bus will be clamped to zero. When the solar arrays operate normally, the

capacitor C1 has 20V voltage drop because the R5 and voltage divider circuit R20 and

R21. Therefore, the diode D2 will block the capacitor current flowing through parallel

diode of IGBT Q2, when SCR Q1 fires. The switching speed of the thyristor is not

important to this application, so the more rugged rectifier grade devices may be used.

Sufficient heat removal for sustained operation at ISCis needed.


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Figure 4.5 Schematic of the main power circuit

After normal operation of the array is to be restored from a midday grid outage, the

SCR Q1 can be turnoff by the following process. The DC bus needs to be energized to a

portion of its normal level by an auxiliary rectifier, which provides control power for the

controller. The capacitor C1 is charged to the dc bus voltage, and the controller detects

that C1 is fully charged. When the controller receives an external command from manual

input or central controller, it provides a gating pulse to IGBT Q2. The pulsed turn-on of

Q2 forces a reverse voltage on SCR Q1 equal to the capacitor voltage VC. The capacitor

C1 is then discharged by the string short-circuit current until SCR Q1 is no longer reverse

biased. This event would only occur at a time when the ac grid is stabilized at its normal

voltage level, so the energy for charging the capacitor C1 is available from the utility side

power source by back-feeding the inverter-side bus. We use the diode D1 block current


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flow in to the switch from the inverter side. The size of the capacitor is very important to

commutate the SCR Q1 off. The minimum value of the capacitor decide by

(1)

Vco is the initial capacitor voltage and toffis the turnoff time provided to the thyristor.

The event of shunt switch turnoff is not very frequent, so the time constant of R1 and C1

is not critical. A lengthy charging time minimizes the current which must be supplied to

the dc bus for turnoff of the shunt switches. Because this technique imposes momentary

reverse voltage on the panel string, if panel shunt diodes are being used in the PV array

system, C1 will discharged by the panel shunt diode rather than the SCR, when providing

a gating pulse to the IGBT. Thus, the SCR cannot be forced commutated successfully. In

this case, a GTO thyristor can be used instead or other turnoff strategies need to be

designed. IGBT Q1 is selected with voltage and current ratings determined by the

maximum bus voltage and string short-circuit current, but due to its infrequent use, will

not need a heat removal system.

4.2.2 Drive Circuit of SCR and IGBT

In order to turn on the SCR and IGBT, we need to design the drive circuit for each.

So next we will discuss the drive circuit we use in the electronic shorting switch.

a. Drive Circuit of SCR

The control circuit must contain a sufficient energy store to reliably fire the thyristor

when rising bus voltage necessitates activation of the shunt switch. This can be

implemented by including sufficient bypass capacitance C2 in the control circuits low-


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voltage power supply to provide the energy for a single gate firing pulse strong enough to

achieve the thyristors full di/dt rating. Any insolation sufficient to produce a string-level

ISC greater than the thyristor holding current will maintain the shunt switch activated

indefinitely, without any other source of auxiliary power. The Figure 4.6 shows us the

circuit we design for the drive circuit of SCR. The energy stores in the Capacitor C3,

after the circuit gets a signal from microcontroller pin RC0 sending to R8, the transistor

Q3 and Q4 will turn on, and then the energy will transfer from C3 to C2. The SCR will

be fired to clamp to bus voltage. The voltage divider circuit of R18 and R19 senses the

voltage of capacitor C3 to make sure that it has enough energy to fire the SCR. The

varistor is the backup to fire the SCR, if the microcontroller fails to trigger the SCR.

Figure 4.6 Schematic of drive circuit of SCR

b. Drive Circuit of IGBT

By using the IGBT driver IR2118 connecting with the microcontroller U1, we can

easy accomplish to drive the IGBT in Figure 4.7. When the R11 getting the signal from

microcontroller pin RC1, IGBT driver U2 can generate the current and voltage necessary

to turn IGBT on and off from the logic output of a microcontroller pin RC1.


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Figure 4.7 Schematic of drive circuit of IGBT

4.2.3 Power Supply Circuit

The purpose of the controller is activation of the shunt switch when needed, primarily

at the moment of ac grid failure and inverter shutdown. Low-voltage control power may

be derived from the dc bus with a simple, but inefficient, shunt regulator. The standby

current drain of the control power supply will also be a design criterion because it

impacts the array energy collection efficiency. Additional current drains are indicated in

Fig. 4.5, due to the voltage dividers producing signals. These signals are needed by the

control circuit to monitor the dc bus voltage and the energy store in C1, and may add

significantly to the standby drain of the control circuit.

We can connect the 10V zener diode and shunt voltage regulator TLV431A in series

to get the 5V for microcontroller and 15V for drive circuit from PV array, in Figure 4.8.

Output voltage of TLV431A can be set to any value between Vref and 6V with two

external resistors. Here we set the electronic shorting voltage regulator to very accurate

5V power to microcontroller by 100K and 34K resistors. The microcontroller and driver

circuit need 1.8 mA totally for typical operation. The value of R3 is determined by the

voltage of PV string, and we choose 220K in this design.


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Figure 4.8 Schematic of power supply circuit

4.2.4 Microcontroller Design

a. Microcontroller Circuit

The controller itself should be designed to use a minimal standby current, allowing a

simple shunt regulator to give adequate standby power consumption. The controller needs

to monitor the dc bus voltage, and respond to an excursion beyond its trip point with a

response time in accordance with the highest dvBUS/dt deemed possible. The controller

must also monitor the voltage on C1 so switch turnoff is not attempted prematurely,

dissipating the charge in C1. Low-cost micro controllers are available to address these

requirements quite well. The shunt switch controller is also a good point at which to

implement string level monitoring and communications with a central control point. The

microcontroller is the brain of the electronic shorting switch. We use the 14 pin

microcontroller PIC16F684 operating with 4Mhz clock frequency in Figure 4.9.

MCP1541 provides a precise output voltage of 4.096V as reference voltage for A/D

converter. The chip MCP111-475 is CMOS voltage detector which designed to keep


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microcontroller in reset until the system voltage has stabilized at the appropriate level for

reliable system operation. The microcontroller can be turned on when the output voltage

of power supply circuit reaches 4.63V. The push-button switches simulate a completed

array system in which an array master controller may send commands directly to the ESS.

Figure 4.9 Schematic of microcontroller

b. Controller Response Time Requirement

The time requirement for the controllers response to a rising bus voltage is very

critical in this design. The electronics shorting switch is able to clamp the bus voltage

before it reach to the dangerous level. In other word, the slew rate of the rising DC bus

voltage decides the response speed of the electronic switch. Thus, the clock frequency of

microcontroller needs to be high enough to achieve the goal. The rate-of-rise of the bus

voltage can be estimated by a conservative method, which is the array short-circuit

current divided by the bus capacitance (primarily the inverter-supplied CO).

(2)


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In the equation (2), CO is the inverter capacitance, andISC is the string current and mis

number of thestrings. The purpose for CO is bypassing the inverter switching-frequency

currents.

As an example application of (2), if the short circuit current is allowed on one PV

string, with an inverter capacitance of 100F. A controller response time of 100s would

allow a bus-voltage overshoot of only 10 V. The low cost and low power microcontroller

PIC can finish this job without any difficulty.

c. Code Design

The Figure 4.10 shows us the flowchart of the software. After the initial function set

the initial value for the microcontroller, the analog-to-digital converter (ADC) allows

conversion of an analog input signal to a 10-bit binary representation of that signal. The

microcontroller can sense the bus voltage momentary to prevent bus voltage rising to

dangerous levels. Once the bus voltage is closed to the dangerous level and the capacitor

C3 has large enough energy to fire the thyristor, the corresponding pins of

microcontroller will generate a pulse to fire the SCR, and the bus voltage can be clamped

by the shorting switch. Then, the microcontroller will be dead due to the outage of PV

array bus. The SCR also can be triggered by an external command.

When PV array revives from a midday shutdown, the dc bus can be energized by a

small auxiliary rectifier to a portion of its normal voltage level, and the microcontroller

will restart to turnoff SCR. After the capacitor C1 is sufficiently charged, the external

command can trigger the IGBT on, and the energy stored in the C1 will go through the

IGBT to generate reverse current to commutate the SCR. Then bus voltage of solar array


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will be back to normal operating condition. The microcontroller will sense the bus

voltage again to protect the PV system.

NO

Yes

Start

Initial ()

A/D

Conversionfor Bus Voltage

Save A/D

Conversion

Result for Bus

voltage

Pulse IGBT

160s

A/D

Conversionfor C3

Save A/D

Conversion

Result for C3

Save A/D

Conversion

Result for C1

Return

Yes

Yes

NO

NO

Is C3 Full

Charge?

Turn on SCR

50 s

A/D

Conversionfor C1

External Reset

Command

Bus Voltage >

VMaxor

External

Command

Yes

Yes

NO

Is C1 Full

Charge?

Figure 4.10 Flowchart of program


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Chapter 5

Testing of Proposed Circuit

5.1 The Test System

The purpose of this test is to verify that the electronic shorting switch clamp the

output voltage when the power of solar array increase beyond the VMPP, and it will

unclamp to normal operation.

Due to lab limitations, we cannot test the electronic shorting switch using the real PV

array. Thus we simulate PV string using two 300 V DC power supplies in series and 23

ohm resistor, and use a 200 V DC power supply to provide energy to circuit for forced

commutation of the SCR in Figure 5.1. The 45 ohm resistor simulates the normal load

provided by an inverter feeding an active ac power grid. The switch S1 is the IGBT

electronic switch. When S1 is open, it can prevent the energy dissipated as the electric

arc, or it will lower the slew rate of rising voltage. We use the 100 F capacitor to

simulate the bus capacitance of inverter. The Table 4 shows the values of parameters in

the testing system.


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Figure 5.2 Waveform of ESS when SCR fires, channel 1: solar string voltage, 200 V/div,

channel 2: string current, 10 A/div, time division: 1 ms/div

To return the PV string back to normal, the capacitor C1 will be charged by the 200 V

DC power supply. When C1 is fully charged to 200 V and the microcontroller receives

the external command, the microcontroller will trigger the IGBT. Then the energy stored

in C1 will go through the IGBT to generate the reverse current, it will be forced

commutate the SCR. After the SCR turns off, the bus voltage will go back to normal very

slowly, because of the current limiting of power supply, showing in Figure 5.3.

Figure 5.4 shows us a clear detail of anode current of SCR when it fires. The DC gate

current from capacitor C3 triggers the SCR and the anode current instantly increase to

around 26 A during the 0.6s. The rate-of-rise of on-state current di/dt is 42.6 A/s in the

Figure 5.4. The maximum di/dt of Sk040R SCR is 175 A/ s, so it wont burn out the

component. The on state current and gate controlled turn-on time is the critical factor to

determine the di/dt in the reality condition.


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Figure 5.3 Waveform of ESS when IGBT trigger, channel 1: solar string voltage,

100V/div, channel 2: capacitor C1current, 5A/div, time division: 50 s/div

Figure 5.4 Waveform of SCR fired, channel 1: DC gate current of SCR Igt, 500 mA/div,channel 2: Anode Current of SCR, 10 A/div, time division 10 s/div

As we discuss required value of C1 in Chapter 4, we choose the 10 F capacitor to

commutate the SCR. And commutated turn-off time is 35s, thus the minimum

commutate voltage is


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(3)

where I is the short circuit current. In our design, we program 180V to successfully

turn off the SCR. After the power grid returns to normal operation, when the

microcontroller senses C1 rising to 180 V, the external command will send to

microcontroller, and SCR turns off. So PV array will operate normally again.

If the microcontroller receives an external trigger signal before the capacitor C1

charged to minimum turn-on voltage, the energy stored in the capacitor cannot

commutate SCR, it will need to wait C1 charged again to turn off SCR successfully.

When the SCR be fired by the open-circuit voltage or the external command, Figure

5.5, 5.6 and 5.7 show the detail of the SCR. In Figure 4.5, Q3 and Q4 has turned on by

the signal sending from microcontroller, the energy in the C3 will transfer to C2 generate

0.75 A DC gate current to fire the SCR. In Figure 5.8, the voltage of C3 drop 5V in very

short time, and the DC gate current will fire the SCR. The voltage between anode and

cathode drops to 0V and anode current increase to ISC.

Power for the micro controller and its associated gate drivers is derived directly from

the dc bus using a dissipative shunt regulator. The total standby current drain on the dc

bus for the power supplies and the metering circuits is 1.8 mA at 400 V. The voltage trip

points are readily re-programmable.


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Figure 5.5 Waveform of SCR fired, channel 1: DC gate current of SCR Igt, 500 mA/div,

channel 2: anode current of SCR, 10 A/div, time division 50 s/div

Figure 5.6 Waveform of SCR fired, channel 1: DC gate current of SCR Igt, 500 mA/div,channel 2: voltage at C3, 5 V/div, time division 50 s/div


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Figure 5.7 Waveform of SCR fired, channel 1: DC gate current of SCR Igt, 500 mA/div,

channel 2: anode-cathode voltage, 200 V/div, time division 50 s/div


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Chapter 6

Conclusion and Future Work

6.1 Conclusion

The large scale PV system will be one of the most important renewable energy

resources in the future. However, it still has some major problems we need to solve, like

low energy collection efficiency and energy cost per watt. The improving economics of

PV panels need to be matched with improvements in the first cost, reliability and energy

efficiency of the dc bus components and inverter. Further reduction in installed cost and

operating losses may be gained by maintaining the working bus voltage as high as

possible, without exceeding limits set by component ratings or operating standards.

An experimental system rated for 600 V was considered. It could only operate at 400

V, with no margin of safety, due to its high open-circuit voltage. Adding the proposed

voltage clamp easily added a 100-V margin of safety to the system. These results suggest

that with the added voltage clamp, the number of panels in a string, and thus VMPP, could

be substantially increased. This pays off by improving the inverter utilization and

lowering ohmic losses (or lowering copper costs) throughout the dc system.


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The electronic shorting switch can prevent the inverter from burning out, when some

unexpected condition, like inverter shut down, grid failure or other malfunction of PV

system. When those condition happen, the output voltage of PV array increases very

sharply, because of no load in the PV system. The electronic shorting switch can able to

be fire, when the voltage just rises marginally higher than VMPP.

The proposed voltage clamp system provides a useful increase in margin of safety for

the operating voltage of the dc system, or alternatively, allows the operating voltage to be

set closer to the system limits for a reduction in ohmic losses.

The cost of electronic shorting switch is not very high, if it can be manufacture on a

large scale. But it can substantially decrease the initial cost in the installation and

maintenance in normal operation. Thus people can earn back the initial cost as soon as

possible. The concept of electronic shoring switch offers a cheaper and safer method to

build the utility-scale solar array in future.

6.2 Future Work

The electronic shorting switch has been verified in the lab, but tests still need to be

performed on the large scale utility scale array above 100kW. The next project is to

design build and test the electronic shorting switch suitable for use in a PV utility-scale

power generation application. The specific design will be based upon a 100-kW field

using First Solar modules.

This thesis just presents a string level electronic shorting switch adopting in the

series-parallel (SP) PV array with the large centralized inverter; the ESS using in inverter

side is also need to investigate. There are still several topics we need to concern about the


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other type of configurations of PV array, like total-cross-tied (TCT) array and bridge-

linked (BL) array, and various topologies of the inverter, such as micro-inverter and

multi-string inverter in future. A useful avenue for future investigation is the use of this

clamp in a protection system to extinguish arcing in the dc bus. This may prove necessary

as utility-scale systems evolve towards higher dc operating voltages.

The ultimate of goal of the electronic shorting switch is that to decrease the initial

cost of the whole PV array system, and keep the PV system operating under the safe

voltage according to the different weather condition.


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References

[1] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E. Galvan, R. C. Portillo Guisado,M. A. M. Prats, J. I. Leon, and N. Moreno-Alfonso, Power-electronic systems for the

grid integration of renewable energy sources: A survey, IEEE Trans. Ind. Electron.,

vol. 53, no. 4, pp. 1002 1016, Jun. 2006.

[2] F. Blaabjerg, Z. Chen, and S. B. Kjaer, Power electronic as efficient interface indispersed power generation systems, IEEE Trans. Power Electron, vol. 19, no. 5, pp.

11841194, Sep. 2004.

[3] E. Roman, R. Alonso, P. Ibanez, S. Elorduizapatarietxe, and D. Goitia, IntelligentPV module for grid-connected PV systems, IEEE Trans. Ind. Electron., vol. 53, no.

4, pp. 10661073, Jun. 2006.

[4] R.-J. Wai, W.-H. Wang, and C.-Y. Lin, High-performance stand-alone photovoltaicgeneration system, IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 240250, Jan.

2008.

[5] Bo Yang, Wuhua Li, Yi Zhao, and Xiangning He, Design and analysis of a grid-connected photovoltaic power system IEEE Trans. Power Electron, vol. 25, no. 4,

pp. 992-1000, Apr 2010.


61/69

49

[6] Toshihisa Shimizu, Osamu Hashimoto, and Gunji Kimura, A novel high-performance utility-interactive photovoltaic inverter system IEEE Trans. Power

Electron, vol. 18, no. 2, pp. 704-711, Mar 2003.

[7] Aimee E. Curtright1 and Jay Apt The character of power output from utility-scalephotovoltaic systems Progress in photovoltaics: Research and applations. Appl.

2008, vol. 16, no, 3, pp241247 Published online 4 September 2007 in Wiley

InterScience (www.interscience.wiley.com) DOI: 10.1002/pip.786.

[8] Utility-scale solar tehcnologies Renewable energy development in the Californiadesert, UM School of natural resources & environment report 2010. available:

http://webservices.itcs.umich.edu/drupal/recd/sites/webservices.itcs.umich.edu.drupal

.recd/files/Introduction%20and%20Methodology_0.pdf

[9] Olivia Mah Fundamentals of photovoltaic materials NSPRI national solar powerreasearch institute, Inc.12/21/98.http://userwww.sfsu.edu/~ciotola/solar/pv.pdf

[10]Sandra Bermejo, Pablo Ortega and Luis Castaer c-Si photovoltaic arrays. MNT,Department of Electronic Engineering, Universitat Politecnica de Catalunya UPC

Barcelona, Spain, 2009. available: http://upcommons.upc.edu/e-

prints/bitstream/2117/9889/1/getPDF.pdf

[11]K. H. Lee, J. K. Park, and Jin Jang A high-performance polycrystalline silicon thinfilm transistor with a silicon nitride gate insulator IEEE Trans. Electron Devices,

vol. 45, no.12, pp. 258-2551, Dec 1998.

[12]Goetzberger, Adolf., Knobloch, Joachim., and Voss, Bernhard. "Crystalline siliconsolar cells. England: John Wiley & Sons, 1998.
http://webservices.itcs.umich.edu/drupal/recd/sites/webservices.itcs.umich.edu.drupal.recd/files/Introduction%20and%20Methodology_0.pdfhttp://webservices.itcs.umich.edu/drupal/recd/sites/webservices.itcs.umich.edu.drupal.recd/files/Introduction%20and%20Methodology_0.pdfhttp://webservices.itcs.umich.edu/drupal/recd/sites/webservices.itcs.umich.edu.drupal.recd/files/Introduction%20and%20Methodology_0.pdfhttp://userwww.sfsu.edu/~ciotola/solar/pv.pdfhttp://userwww.sfsu.edu/~ciotola/solar/pv.pdfhttp://upcommons.upc.edu/e-prints/bitstream/2117/9889/1/getPDF.pdfhttp://upcommons.upc.edu/e-prints/bitstream/2117/9889/1/getPDF.pdfhttp://upcommons.upc.edu/e-prints/bitstream/2117/9889/1/getPDF.pdfhttp://upcommons.upc.edu/e-prints/bitstream/2117/9889/1/getPDF.pdfhttp://upcommons.upc.edu/e-prints/bitstream/2117/9889/1/getPDF.pdfhttp://userwww.sfsu.edu/~ciotola/solar/pv.pdfhttp://webservices.itcs.umich.edu/drupal/recd/sites/webservices.itcs.umich.edu.drupal.recd/files/Introduction%20and%20Methodology_0.pdfhttp://webservices.itcs.umich.edu/drupal/recd/sites/webservices.itcs.umich.edu.drupal.recd/files/Introduction%20and%20Methodology_0.pdf


62/69

50

[13]Ming-Chun Tseng, Ray-Hua Horng, Yu-Li Tsai, Dong-Sing Wuu, and Hsin-Her Yu"Fabrication and characterization of GaAs solar cells on copper substrates" IEEE

Electron Device Letters, vol. 30, no. 9, pp.940-942, Sep 2009.

[14]J.F Nijs, J Szlufcik, J Poortmans, S Sivoththaman, R.P Mertens Advanced cost-effective crystalline silicon solar cell technologies Solar Energy Materials and Solar

Cells, vol 65, no.10, pp. 249-259, Jan 2001.

[15]Ruud E. I. Schropp and Miro Zeman New developments in amorphous thin-filmsilicon solar cells IEEE Trans. Electron Devies, vol. 46, no. 10, pp. 2086-2092, Oct

1999.

[16]Roberto Galloni Amorphous silicon solar cells Renewable Energy, Vol 8, no 14,pp. 400404, MayAug 1996.

[17]J.U. Trefny, D. Mao, V. Kaydanov, T.R. Ohno,D.L. Williamson, R. Collins, and T.E.Furtak Polycrystalline thin-film cadmium telluride solar cells fabricated by

electrodeposition Jan1999.http://www.nrel.gov/docs/fy99osti/26009.pdf

[18]Nicolas Matome Thantsha On the characterisation of copper indium dieslenide basedphotovoltaic devices" Jan 2006.

[19]Mummadi Veerachary, Tomonobu Senjyu, Katsumi Uezato Voltage-basedmaximum power point tracking control of PV system IEEE trans. Aerospace and

Electronic Systems, vol 38, no. 1. pp.262-270, Jan 2002

[20]Theodoros L. Kottas, Yiannis S. Boutalis, and Athanassios D. Karlis, Newmaximum power point tracker for PV arrays using fuzzy controller in close

cooperation with fuzzy cognitive networks IEEE Trans. Energy Conversion, vol. 21,

no. 3, pp. 793-803, Sep 2006.
http://www.nrel.gov/docs/fy99osti/26009.pdfhttp://www.nrel.gov/docs/fy99osti/26009.pdfhttp://www.nrel.gov/docs/fy99osti/26009.pdf


63/69

51

[21]Nobuyoshi Mutoh, Masahiro Ohno, and Takayoshi Inoue A method for MPPTcontrol while searching for parameters corresponding to weather conditions for PV

generation systems IEEE Trans. Industrial Electronic, vol. 53, no. 4, pp. 3049-3099,

Aug 2006.

[22]Hiren Patel and Vivek Agarwal, Maximum power point tracking scheme for PVsystems sperating under partially shaded conditions IEEE Trans. Industrial

Electronic, vol. 55, no. 4, pp. 1689-1698, Apr 2008.

[23]Trishan Esram, and Patrick L. Chapman, "Comparison of photovoltaic arraymaximum power point tracking techniques" IEEE Trans. Energy Conversion, vol.

22, no. 2, pp. 439-449, Jun 2007

[24]Nicola Femia, Giovanni Petrone, Giovanni Spagnuolo, and Massimo VitelliOptimization of Perturb and Observe Maximum Power Point Tracking Method

IEEE Trans. Power Electronics, vol. 20, no. 4, pp. 963-973, Jul 2005.

[25]Gwinyai Dzimano, B.S. Modeling of photovolatic systems The Ohio StateUniversity, 2008

[26]John Wiles Photovoltaic power systems and the national electrical code: suggestedpractices Dec 1996.

[27]David L. King, Jay A. Kratochvil,and William E. Boyson Temperature coefficientsfor PV modules and arrays: measurement methods, difficulties, and results Sep

1997.

[28]Ian Woofenden "Photovoltai cell, module, string, array" 2006. available:http://homepower.com/view/?file=HP113_pg106_WordPower
http://homepower.com/view/?file=HP113_pg106_WordPowerhttp://homepower.com/view/?file=HP113_pg106_WordPowerhttp://homepower.com/view/?file=HP113_pg106_WordPower


64/69

52

[29]Narendra D. Kaushika and Nalin K. Gautam "Energy yield simulations ofinterconnected solar PV arrays" IEEE Trans. Energy Conversion, vol. 18, no. 1, pp.

127-134, Mar 2003.

[30]Engin Karatepe , Mutlu Boztepe, Metin C,olak "Development of a suitable model forcharacterizing photovoltaic arrays with shaded solar cells" Solar Energy, vol. 81, no.

8, pp. 977-992, August 2007.

[31]Soeren Baekhoej Kjaer, et. al, A review of single-phase grid-connected inverters forphotovoltaic modules IEEE Trans. on Industrial Applications, vol. 41, no. 5, pp.

1292-1306.2005.

[32]Gabriele Grandi, Claudio Rossi, Darko Ostojic, and Domenico Casadei, " A newmultilevel conversion structure for grid-connected PV applications" IEEE Trans.

Industrial Electronics, vol. 56, no. 11, pp. 4416-4426, Nov 2009.

[33]Mervin Johns, Hanh-Phuc Le and Michael Seeman "Grid-connected solar electronic"University of California at Berkeley Department of EECS. Available:

http://www.eecs.berkeley.edu/~phucle/EE_290N/290N_report.pdf
http://www.eecs.berkeley.edu/~phucle/EE_290N/290N_report.pdfhttp://www.eecs.berkeley.edu/~phucle/EE_290N/290N_report.pdf


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Appendix B

Program listing for microcontroller


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improvement of the operating efficiency and initial costs of a utility-scale photovoltaic

Documents