implementing electrical and simulation rule checks to ensure signal quality
DESCRIPTION
Join Matthew Harms as he discusses a unique multi-tiered strategy to board analysis & verification designed to enable designers of all skill levels to analyze their PCB designs early in the development cycle when the cost of change is the lowest. Matthew will show how Cadence has created a multi-tier analysis environment that lets designers start with a set of pre-defined Electrical Rule Checks (ERC) that can be run on the board to quickly identify areas of interest or concern all without the need for any complex models or configurations. Based on these initial 1st order results Matthew will show how design teams can then effectively target critical nets with 2nd order (Simulation Rule Checks) and 3rd order (Power Aware Signal Integrity) analysis as needed to simulate with greater detail and achieve complete electrical design signoff.TRANSCRIPT
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OrCAD Now! AnaheimSignal Integrity Presentation
Matthew Harms
Field Applications Engineer
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Advanced layout check
Coupling
overlay in
layout
Coupling plot
Coupling table
ERCElectrical rule check
SRCSimulation rule check
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• SI metrics check is a simulation-based PCB check
• It can be done at 3 levels, based on considerations of trace/via couplings and non-ideal PDN effects
Three levels of SI/PI simulations
SI / PI
simulation
level
Trace coupling Via coupling Power-aware(non-ideal PDN)
SI/PI effects captured
Level 1 NoWithin pair trace coupling
for diff pairs included
NoWithin pair via coupling
for diff pairs included
No
Delay;
Reflection;
Loss
Level 2 Yes Yes No Crosstalk
Level 3 Yes Yes Yes
Return path
discontinuity;
SSO
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Electrical Rule Check (ERC)
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ERC – Electric rule check
• ERC is a power-aware PCB check in geometry
domain for
– Electrical length
– Trace impedance
– Trace coupling
– Trace upper/lower layer, and coplanar references, or the
lack thereof
– Differential routing in phase, or out of phase
– Via coupling
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Two trace segments example
DRC – Simplified view
• 2 trace segments, same trace width, same impedance
trace9048
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Two trace segments example
• DDR3 SODIMM
• 2 trace segments for net DQ0 on
layer3
trace9047 trace9048
Zoom in on 2 trace
segments on
Layer3
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Two trace segments example
If you look close enough…
• Trace9047: one uniform
impedance section
• Trace9048: 4 impedance
sections
trace9048
Signal layer + plane
layers directly above
and below
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Two trace segments example
ERC – Impedance
• ERC results also shows
trace9047 has one
impedance section
• But trace9048 actually
has 5 impedance
sections when all layers
are considered
1
2
3
4
5
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Two trace segments example
ERC – Trace coupling
• Trace9047
broken into 5
sections based
on trace coupling
1
2
3
4
5
1
23
4
5
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Two trace segments example
ERC – Trace upper/lower layer reference
• Based on upper/lower layer
references
– Trace9047 one section
– Trace9048 5 sections
trace9048
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Two trace segments example
ERC – Trace coplanar reference
• Both trace do not
have coplanar
reference shapes trace9048
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Two trace segments example
From 2 trace segments to entire board
Oh, no!
• If ERC results are useful, can you image doing that for the
entire PCB?
• At larger scale, you will need ERC to help you
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Whole board ERC does not get any easier
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1. Load spd file
2. Select option ‘Check all nets’
3. Run simulation
(cont.)
1
2
3
As easy as
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Results in 6 tables
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ERC with NetGroups
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Impedance/Coupling PlotCollapsed
18
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Impedance/Coupling PlotExpanded
19
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Simulation Rule Check (SRC)
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1. Comprehensive and practical for board level electrical design check
2. Easy and fast setup– Simple Tx voltage stimulus and Rx termination models
– Net groups are automatically generated for different interfaces
3. Simulation levels: level1 to level3
4. Results automatically post processed– Rx/Tx/FEXT/NEXT waveform results
– SI performance metrics (using Rx and FEXT waveforms)
– Check report (files, setup, and results)
Simulation Rule Check Overview
Example:
• 1 CPU
• 4 memory channels,
• 8 DIMM
• 420 nets
• Setup time 3 min with 8
automatically generated net
groups
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• A DDR design is used in this tutorial– Controller U0, 4 DRAMs U1-U4
Board for tutorial
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SRC – Simulation Rule Check
Time-domain waveforms
• The ckt and waveforms and ckt
Rx/Tx/FEXT/NEXT
waveforms
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• Waveforms
Rx waveform
FEXT waveform
xtkIntISIInt
sigIntratioSN
xtkIntISIIntsigIntdifferenceSN
dttfextxtkInt
dttRxdttRxISIInt
dttRxsigInt
t
i
t
t
t
t
t
__
__
____
)(_
)()(_
)(_
max
max
2
1
2
1
0
0
)()(
)()(
tnexttNEXT
tfexttFEXT
i
i
• SI metrics are defined using magnitudes
of Rx and FEXT
SRC – Simulation rule check
SI metrics
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SRC – Simulation rule check
Net-level performance ranking
Ranking by SI
Metrics
Ranking by xtalk
levels
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General SI Workflow
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General SI Simulation (GSI) workflow is a newly introduced general purpose Level-1 and Level-2 SI analysis workflow
• Layout based
• Ideal power/ground
• Easy to set up
• Fast simulation
ASI16.63 new: General SI Simulation workflow
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How GSI workflow works
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• Enable all nets except power net VTT_REF
• Check diff pairs and polarities
Step 1: Select Nets
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• Assign power nets voltage
• Voltages for gnd nets are assumed to be 0v
Step 2: Assign power net voltage
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• About a component and its models– Component name (from layout file)
– Component part name (from layout file)
– Component types (auto assigned, user can re-assign it)
– Component models (user assigned)
Step 3: Assign component models
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Step 4: Set up SI simulation options
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• Un-select waveform at driver pins (all pins for U0)
• Leave all receiver pins at DRAMs selected
Step 5: Set up probes
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• Check ‘Shape Processing’ if shown– If not shown, the shapes have been
processed and saved
• Check ‘Error Checking’
Step 6: Save
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• Layout and simulation setup is loaded to simulator spdsim
• After trace/pad parameters extraction, simulation will start one net/pair at a time– A differential pair is handled in one simulation
Step 7 Running Simulations
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• Both pin and pad waveforms are available
Step 8: View results
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Simulation considering non-ideal PDN
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• SI metrics check is a simulation-based PCB check
• It can be done at 3 levels, based on considerations of trace/via couplings and non-ideal PDN effects
Three levels of SI/PI simulations
SI / PI
simulation
level
Trace coupling Via coupling Power-aware(non-ideal PDN)
SI/PI effects captured
Level 1 NoWithin pair trace coupling
for diff pairs included
NoWithin pair via coupling
for diff pairs included
No
Delay;
Reflection;
Loss
Level 2 Yes Yes No Crosstalk
Level 3 Yes Yes Yes
Return path
discontinuity;
SSO
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• Large signal degradation due to non-ideal PDN effect
• Level-2 simulation failed to show it
AddCmd results @U103
Level-1
Level-3
Level-2
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Power Integrity Analysis
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current density with temperature
awareness
temperature due to Joule (copper) and component heating
PowerDC
• Electrical resistance increases at higher temperatures
• Component leakage power dissipation increases at higher temperatures
Iterate
until
converged
Thermal Simulationtemperature
Electrical Simulationcurrent density
• Copper (Joule) heating will affect temperature distributions
PowerDCIntegrated Electrical & Thermal Co-Simulation
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Electrical Results
42
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• OptimizePI is a highly
automated board AC
frequency analysis
solution
• Supports pre and
post-layout decap
studies and identifies
impedance issues
• Decap
implementations are
optimized for
performance and cost.
OptimizePIOverview
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Original Design
Scheme29 (15cents
saving)
78mV
68mV
12% noise
improved
21% cost
saving
Correlation to Time DomainBetter performance at less cost
44
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• PowerSI is an
advanced signal
integrity, power
integrity and
design-stage EMI
solution
• Supports S-
parameter model
extraction and
provides robust
frequency domain
simulation for entire
PCB design
PowerSIOverview
45
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• Identify impedance
“hot spots”
• Place decoupling
capacitors in areas
exceeding target
impedance
• Analyze power /
ground resonance
• Minimize
component costs
with optimized
decoupling
PowerSIAnalyze Decoupling Capacitor Selection and Placement
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