Implementation & Structure of Page Table

AgendaPage Table DefinitionImplementation of Page Table

Hardware SupportPaging Hardware With TLBMemory Protection

Page Table StructureHierarchical PagingShared PagesInverted Page TablesHashed Page Tables

Page Table Definition

A page table is the data structureused by a virtual memory systemin a computer operating system to store the mapping between virtual addresses and physical addresses

Two concern to discussImplementation of Page Table

concerning about the access time of page table and load it to main memory

Page Table Structureconcerning about the page table size & structure implementation

Implementation of Page Table(Hardware Support)

The hardware implementation of the page table can be done in several ways.

In the simplest case, the page table is implemented as a set of dedicated registers. These registers should be built with very high-speed logic to make the paging-address translation efficient.

Problem with page size…..

Hardware SupportPage table is kept in main memory.Page-table base register (PTBR) points to the

page table.Page-table length register (PRLR) indicates

size of the page table.In this scheme every data/instruction access

requires two memory accesses. One for the page table and one for the data/instruction

Problem with access time…..

Paging Hardware With TLBThe CPU's memory management unit (MMU) stores a

cache of recently used mappings from the operating system's page table. This is called the translation look a side buffer (TLB).

Paging Hardware With TLBThe TLB may reside between the CPU and

the CPU cache, between the CPU cache and primary storage memory, or between levels of a multi-level cache.

The TLB is typically implemented as content-addressable memory (CAM).

The TLB is associative, high-speed memory. Each entry in the TLB consists of two parts:a key (or tag) and a value.

Paging Hardware With TLBAssociative memory – parallel search

Address translation (A´, A´´)If A´ is in associative register, get frame # out. Otherwise get frame # from page table in

memory

Page # Frame #

Paging Hardware With TLBTLB HitTLB MissIf the TLB is already full of entries, the

operating system must select one for replacement

address-space identifiers (ASIDs)Page fault

Paging Hardware With TLB

Paging Hardware With TLBEffective Access Time

Associative Lookup = time unitAssume memory cycle time is 1 microsecondHit ratio – percentage of times that a page

number is found in the associative registers; ration related to number of associative registers.

Hit ratio = Effective Access Time (EAT)

EAT = (1 + ) + (2 + )(1 – )= 2 + –

Paging Hardware With TLBSuppose:

TLB lookup takes 5 nano sec. Memory access time is 100 nano sec. Hit ratio (probability to find page number in TLB) is ?

Effective Access Time = (5+100)* ? +( 5+100+100)*(1- ?)

Suppose ? = 80% (for example, TLB size = 16) EAT = 105*.8 + 205*.2 = 125 nano sec. Suppose ? = 98% (for example, TLB size = 64) EAT = 105*.98 + 205*.02 = 107 nano sec

Memory ProtectionMemory protection implemented by

associating protection bit with each frame.- One bit can define a page to be read-\Write or read-only

Valid-invalid bit attached to each entry in the page table:“valid” indicates that the associated page is in the process’

logical address space, and is thus a legal page.“invalid” indicates that the page is not in the process’ logical

address space.page-table length register (PTLR), to indicate the size of the

page table.

Memory Protection

Page Table StructureMost modern computer systems support a

large logical address space(2^32 to 2^64). In such an environment, the page table itself becomes excessively large. For example, consider a system with a 32-bit logical address space. If the page size in such a system is 4 KB (212 ), then a page table may consist of up to 1 million entries (2^32/2^12). Assuming that each entry consists of 4 bytes, each process may need up to 4 MB of physical address space for the page table alone.

Hierarchical Page TablesKnowing as Multilevel PagingThe page table might be too big to fit in a

contiguous space, so we may have a hierarchy with several levels

Break up the logical address space into multiple page tables.

A simple technique is a two-level page table, three-level page table.

Two-Level Page-Table Scheme

Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is

divided into: a page number consisting of 20 bits. a page offset consisting of 12 bits.

Since the page table is paged, the page number is further divided into: a 10-bit page number. a 10-bit page offset.

Thus, a logical address is as follows:

where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table.

page number page offset

pi p2 d

10

10

12

Three-Level Paging ExampleA logical address (on 64-bit machine with 4K page size) is divided into:

The next step Would be a four-level paging scheme,

Address-Translation SchemeAddress-translation scheme for a two-

level 32-bit paging architecture

Performance of Hierarchical PagingSuppose:

Three level paging TLB lookup takes 5 nano sec. Memory access time is 100 nano sec. Hit ratio (probability to find page number in TLB) is ?

Effective Access Time = (5+100)* ? +( 5+300+100)*(1- ?) Suppose ? = 80% (for example, TLB size = 16) -EAT = 105*.8 + 405*.2 = 165 nano sec. Suppose ? = 98% (for example, TLB size = 64) -EAT = 105*.98 + 405*.02 = 111 nano sec.

Shared PagesShared code

One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems).

Shared code must appear in same location in the logical address space of all processes.

Private code and data Each process keeps a separate copy of the code

and data.The pages for the private code and data can appear

anywhere in the logical address space.

Shared Pages Example

Inverted Page TableThe inverted page table (IPT) combines a page

table and a frame table into one data structure.One entry for each virtual page number & real

page of memory.Entry consists of the virtual address of the

page stored in that real memory location, with information about the process that owns that page.

Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs.

Inverted Page TableUse hash table to limit the search to one

— or at most a few — page-table entries.Say goodbye to sharing ?

-because there is only one virtual page entry for every physical page, one physical page cannot have two (or more) shared virtual addresses.

Inverted Page Table Architecture

Hashed Page TablesCommon in address spaces > 32 bits.The virtual page number is hashed into a page table.

This page table contains a chain of elements hashing to the same location.

Each element consists of three fields: (1) the virtual page number,(2) the value of the 111apped page frame,(3) a pointer to the next element in the linked list.

Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

Hashed Page Table

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