implementation chapter3 1
TRANSCRIPT
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Logic value 1
Undefined
Logic value 0
Voltage
V DD
V 1,min
V 0,max
V SS (Gnd)
Logic values as voltage levels.
- Positive/Negative logic system
-V0,max: max. voltage level that a
logic circuit recognizes as low- V1,min: min. voltage level that a
logic circuit recognizes as high
- Exact V0,max ,V1,min values depend
on used technology, normally 40%VDD and 60% VDD
Voltage Levels
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NMOS transistor as a switch.
Drain Source
x = "low" x = "high"
(a) A simple switch controlled by the input x
V D V S
(b) NMOS transistor
Gate
(c) Simplified symbol for an NMOS transistor
V G
Substrate (Body)
- Most popular used transistor is
MOSFET: NMOS & PMOS
- 4 electrical terminals. In logic
circuits the substrate terminal is
connected to Gnd for NMOS
- No physical difference betweensource and drain terminals
- By convention, the source
terminal is the node with lower
voltage for NMOS
NMOS
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- Silicon is an electrical semiconductor.
- A transistor is fabricated by creating areas in the silicon substrate
that have an excess of either positive or negative electrical charge.
- The gate terminal is made of poly-silicon which is preferable to
metal as it can be fabricated with extremely small dimensions.
- The gate is electrically isolated from the rest of transistor by a
layer of SiO2.
- Transistor’s operation is governed by electrical fields caused by
voltages applied to its terminal
Remarks
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NMOS transistor when turned off : back-to-back diodes represent
very high resistance (1012 ohm) between drain & source
++++++ ++++ ++++++ +++ ++++++++++++ ++++++ ++++++
+++++++++ +++++++++
+++++++++++ +++++++++++
Drain (type n)Source (type n)
Substrate (type p)
SiO2
(a) WhenV GS
= 0 V, the transistor is off
V S
0 V=
V G
0 V=
V D
++++++
++++++++++++
++++++
NMOS off
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++++++ ++++ +++ ++++++
++++++ ++++++
+++++++++ +++++++++++++++++++++ +++++++++++++++++
Channel (type n)
SiO2
V DD
(b) WhenV GS = 5 V, the transistor is on
++ +++++++
V D
0 V=
V G
5 V=
V S
0 V=
NMOS transistor when turned on: If the gate-to-source voltage
VGS is greater than a certain minimum positive voltage, called
VT (typically 0,2 VDD), then the switch is closed.
NMOS on
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-The positive voltage on the gate attracts free electrons existing in
the type-n source and drain terminals & other areas of the transistor
towards the gate. Because of SiO2 layer, electrons gather in region
of the substrate between source & drain terminals, which results
into channel connecting source & drain.
- The size of channel is determined by length L & width W
+
+
(a) Small transistor
L
W 1
L
W 2
(b) Larger transistor
Channel
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PMOS transistor as a switch.
Gate
x = "high" x = "low"
(a) A switch with the opposite behavior
V G
V D V S
(b) PMOS transistor
(c) Simplified symbol for a PMOS transistor
V DD
Drain Source
Substrate (Body)
- Most popular used transistor is
MOSFET: NMOS & PMOS
- 4 electrical terminals. In logic
circuits the substrate terminal is
connected to to V DD for PMOS
- No physical difference betweensource and drain terminals
- By convention, the source
terminal is the node with higher
voltage for PMOS
PMOS
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NMOS and PMOS transistors in logic circuits.
(a) NMOS transistor
V G
V D
V S = 0 V
V S = V DD
V D
V G
Closed switch
whenV G = V DD
V D = 0 V
Open switch
whenV G = 0 V
V D
Open switch
whenV G = V DD
V D
V DD
Closed switch
whenV G = 0 V
V D = V DD
V DD
(b) PMOS transistor
- When the NMOS transistor is
turned on, its drain is pulled down
to Gnd
- When the PMOS transistor is
turned on, its drain is pulled up to
to V DD
Operations
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A NOT gate built using NMOS technology.
x f
(c) Graphical symbols
x f
V x
V f
R
+
-
(a) Circuit diagram
5 V
(b) Simplified circuit diagram
V x
V f
V DD
R
- VX=0V, tr is turned off -->
Vf =5V
- When VX=5V, tr is turned on,
its drain is pulled down to Gnd
--> Vf =0V
- Exact Vf depends on R & tr.,
typically is 0.2V
- R is used to limit the currentduring turning on of tr.
( problem?)
NMOS NOT
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NMOS realization of a NAND gate.
V f
V DD
(a) Circuit
(c) Graphical symbols
(b) Truth table
f f
0
0
1
1
0
1
0
1
1
1
1
0
x 1 x 2 f
V x 2
V x 1
x 1
x 2
x 1
x 2
- Series connection of NMOS to
create the logic AND function
- VX1= VX2=5V, tr is turned off -->Vf =5V
- When VX=5V, trs are turned on,
their drains are pulled down to
Gnd --> Vf will be closed to 0V
- If only one of trs is turned off,
then Vf will be pulled up to 5V
- R is used to limit the current
during turning on of tr. ( problem?)
NMOS NAND
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NMOS realization of a NOR gate.
V x1V x2
V f
V DD
(a) Circuit
(c) Graphical symbols
(b) Truth table
f
00
1
1
01
0
1
10
0
0
x1
x2 f
f
x1
x2
x1
x2
- Parallel connection of NMOS
to create the logic NOR
function- Either VX1= 5V or VX2=5V,
Vf will be closed to 0V
- If both Vx =0V --> Vf will be
pulled up to 5V
NMOS NOR
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NMOS realization of an AND gate.
(a) Circuit
(c) Graphical symbols
(b) Truth table
f f
0
0
1
1
0
1
0
1
0
0
0
1
x 1 x 2 f
V f
V DD
A
V x 1
V x 2
x 1
x 2
x 1
x 2
V DD
- AND realization by following a
NAND gate with an Inverter
NMOS AND
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NMOS realization of an OR gate.
(a) Circuit
(c) Graphical symbols
(b) Truth table
f
0
0
1
1
0
1
0
1
0
1
1
1
x1 x2 f
f
V f
V DD
V x2V x1
x1 x
2
x1
x2
V DD
- OR realization by following
a NOR gate with an Inverter
NMOS OR
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Structure of an NMOS circuit.
V f
V DD
Pull-down network V x1
V xn
(PDN)
- All mentioned structures can be
characterized by a block diagram withPDN (pull-down network)
PDN Structure
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Structure of a CMOS circuit.
V f
V DD
Pull-down network
Pull-up network
V x1
V xn
(PUN)
(PDN)
- All mentioned structures can be
characterized by a block diagram withPDN (pull-down network)
- The CMOS concept: replacing the
pull-up device with a pull-up network
(PUN) that is built using PMOS tr.(PDN & PUN networks are
complements of each other)
- For any given values of the inputs,
either the PDN pulls Vf down to Gnd
or the PUN pulls Vf up to VDD
- The PDN & PUN have equal
numbers of trs. (the networks are dualsof one another)
- Whenever the PDN has NMOS trs.
in series, the PUN has PMOS trs. in
parallel, and vice versa
PDN-PUN
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CMOS realization of a NOT gate.
(b) Truth table and transistor states
on
off
off
on
1
0
0
1
f x T 1 T 2
(a) Circuit
V f
V DD
V x
T 1
T 2
NMOS realization of NOT gate
V x
V f
V DD
R
- When Vx= 0V, T1 is ON &
T2 is OFF, Vf = 5V. Since T2 is
OFF, no current flows throughtrs.
- When Vx= 5V, T2 is ON &
T1 is OFF, Vf
= 0V. Since T1 is
OFF, no current flows through
trs.
- KEY: no current flows in
CMOS Inverter
CMOS NOT
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CMOS realization of a NAND gate.
(a) Circuit
V f
V DD
(b) Truth table and transistor states
on
on
on
off
0
1
0
0
1
1
0
1
off
off
on
off
off
on
f
off
on
1
1
1
0
off
off
on
on
V x1
V x2
T 1 T 2
T 3
T 4
x1 x2 T 1 T 2 T 3 T 4
2121 x x x x f +==Logic expression of NAND gate:
Look at Truth Table, f=1 when either x1 or x2 = 0, thus PUN mustbe active in this case (pull up V f to “1”), and two PMOS transistors
must be connected in parallel.
The PDN must implement the complement of f :
Since !f=1 when both x1 and x2 = 1, PDN must
have two NMOS trs. connected in series.
21 x x f =
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(a) Circuit
V f
V DD
(b) Truth table and transistor states
on
on
on
off
0
1
0
0
1
1
0
1
off
off
on
off
off
on
f
off
on
1
0
0
0
off
off
on
on
V x1
V x2
T 1
T 2
T 3 T 4
x1 x2 T 1 T 2 T 3 T 4
CMOS realization of a NOR gate.
2121 x x x x f =+=
21! x x f +=
CMOS NOR
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CMOS realization of an AND gate:
connecting a AND gate to an Inverter
V f
V DD
V x1
V x2
V DD
CMOS AND
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Consider the following function:
Since all variables appear in theircomplemented form, we can directly
derive the PUN: 1 PMOS tr. controlled by
x1
in parallel with a series combination of
2 PMOS trs. controlled by x2 & x3
For PDN, take complemented form of f which leads to result as shown in Fig.
V f
V DD
V x1
V x2
V x3
321 x x x f +=
( )321321 x x x x x x f +=+=
Example 3.1
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Consider the following function :
Build a circuit using CMOS to implement this functionality
( 4321 x x x x f ++=
Example 3.2
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Consider the following function :
Step 1: Build PUN
Step 2: Build PDN
V f
V DD
V x1
V x2
V x3
V x4
( 4321 x x x x f ++=
(4321 x x x x f ++=
( )4321! x x x x f +=
Example 3.2
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Voltage levels in the NAND gate
(a) Circuit
V f
V DD
(b) Voltage levels
L
H
L
L
H
H
L
H
H
H
H
L
V x1
V x2
V x1V x2
V f
Voltage Levels
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Positive logic system: higher voltages represent logic value
1 & lower voltages represent logic value 0
Negative logic systems: the association between voltages
and logic values is reversed
(a) Positive logic truth table and symbol of NAND gate
(b) Negative logic truth table and symbol of NAND gate
1
10
0
1
01
0
0
00
1
x 1 x 2 f
f x 1
x 2
f 00
1
1
01
0
1
11
1
0
x 1 x 2 f
x 1
x 2
Voltage Levels
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Large variety of chips that implement various functions that are
useful in the design of digital hardware
The chips range from very simple ones with low functionality to
extremely complex chips
Eg. A digital hardware product may require a µP to perform
some arithmetic operations, memory chips to provide storage
capability, and interface chips that allow easy connection to inputand output devices
Three main types of chips:
Standard chips
Programmable logic devices Custom chips
Integrated Circuit Chips
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Circuit Complexity
Gives measure of number of transistors or gates
Within single packageFour general categories
SSI - Small Scale IC
< 12 gates or so
MSI - Medium Scale IC
< 100 gates or so
LSI - Large Scale IC
< 1000 gates or soVLSI – Very Large Scale IC
> 1000 gates or so
Characterizing Standard Chips: Digital ICs
characterized several ways as follows:
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Circuit Topology
Describes the input and output structure of the deviceThree general categories
TTL - Transistor Transistor Logic
Bipolar transistors on input and output
Output section looks like described circuitReferred to as totem pole output
ECL - Emitter Coupled Logic
BipolarLogic done in emitter circuitry rather than collector
High speed
MOS - Metal Oxide Semiconductors
MOS transistors on input and output
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SSI Circuits
Let’s look now at some SSI circuits
Referred to as glue logic in today’s design
Most designs highly integrated
VLSI
Gate arraysArray logics
Glue logic provides means of interconnection
SSI circuits fall into 3 general categories
Basic gatesSimple combinations of gates
Buffer and driver gates
Basic Gates
These implement fundamental logic functionsAND OR
NAND NOR
NOT
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A 7400-series chip.
(a) Dual-inline package
(b) Structure of 7404 chip
V DD
Gnd
Standard Chip Examples
- 74LS00 is built by TTL te.- 74HC00 is fabricated by CMOS te.
- Most popular chips used today are
the CMOS variants
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An implementation of
V DD
x 1
x 2
x 3
f
7404
7408 7432
3221 x x x x f +=
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The 74244 buffer chip comprises 8 tri-state buffers
P i n
2
P i n
4
P i n
6
P i n
8
P i n
1
P i n
1 2
P i n
1 4
P i n
1 6
P i n
1 8
P i n
1 1
P i n
1 3
P i n
1 5
P i n
1 7
P i n
1 9
P i n
3
P i n
5
P i n
7
P i n
9
- Because of their low logic capacity, the standard
chips are seldom used in practice.- One exception: many modern products include
standard chips containing buffers (logic gates that are
usually used to improve the circuit speed)
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A non-inverting buffer
(a) Implementation of a buffer
V f
V DD
V x
x f
(b) Graphical symbol
- When a logic gate has to drive a large
capacitive load, buffers are often used
to improve performance: f = x- Buffers can be created with different
amounts of drive capability, depending
on the sizes of the transistors (will be
discussed later …)- As used for driving higher-than-
normal capacitive loads, buffers have
trs. that are larger than normal
- Not only for high speed performance,buffers are also used when high current
flow is needed to drive external devices
(e.g. use buffer to control LED)
Buffer
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-Inverting buffer produces the same output as an inverter but is builtwith relatively large transistors
- As shown in figure, for large values of n an inverting buffer could
be used for the inverter labeled as N1
Inverter that drives n other inverters
x f
n
To inputs of
n other inverters
N 1
Inverting Buffer
T i b ff h ddi i l l i ll d bl
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Tri-state buffer has additional control input, called enable, e
x f
e
(a) A tri-state buffer (c) Truth table
0
0
1
1
0
1
0
1
Z
Z
0
1
f e x
(b) Equivalent circuit
x f
e = 0
e = 1x f
Four types of tri-state buffers.
x f
e
(b)
x f
e
(a)
x f
e
(c)
x f
e
(d)
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An application of tri-state buffers: Multiplexer
f x 1
x 2
s
Multiplexer based on Logic gates
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(b) Truth table
Zx
01
f s
s 0=
s 1=
x
x
f = Z
f = x
(c) Equivalent circuit
(a) Circuit
f x
s
s
(d) Graphical symbol
f x
s
s
- A transmission gate: switch that connects x to f
- A switch is turned on by setting VS = 5V & V!S = 0V. Operations:
+ Vx= 0V: NMOS is turned
on, Vf = 0 (drain is pulled
down to Gnd – source)
+ Vx= 5V: PMOS is turnedon, Vf = 5V (drain is pulled
up to V DD – source)
f x
e
(e) Implementation
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A 2-to-1 multiplexer built using
transmission gates.
x 1
x 2 f
s
f x 1
x 2
s
A 2-to-1 multiplexer built using
tri-state buffers.
Truth table: Transmission gate
Zx
01
f s
Truth table: Tri-state buffer
0
0
1
1
0
1
0
1
Z
Z
0
1
f e x
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CMOS implementation
x 1
x 2
f x 1 x 2⊕=
CMOS Exclusive-OR (XOR) gate.
Truth table
0
0
1
1
0
1
0
1
0
1
1
0
x 1 x 2 f x 1 x 2⊕=
XOR Gate
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Logic gate based Exclusive-OR (XOR) gate.
(b) Graphical symbol(a) Truth table
0
0
1
1
0
1
0
1
0
1
1
0
x 1 x 2
x 1
x 2
f x 1 x 2⊕=
f x 1 x 2⊕=
(c) Sum-of-products implementation
f x 1 x 2⊕=
x 1
x 2
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An example of a NOR-NOR PLA.
V DD
V DD
V DD V DD V DD
S 1
S 2
S 3
NOR plane
NOR plane
f 1 f 2
x 1 x 2 x 3
PLD
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Programmable logic device as a black box.
Logic gatesand
programmableswitches
Inputs
(logic variables)Outputs
(logic functions)
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General structure of a PLA (Programmable Logic Array).
f 1
AND plane OR plane
Input buffers
invertersand
P1
Pk
f m
x 1 x 2 x n
x 1 x 1 x n x n
-Be realized in Sum-Of-Products form
- Each Pk is configured to implement any
AND function of xi
- Each f m is configured to implement any
OR function of Pk
PLA
x1 x2 x3
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Gate-level diagram of a PLA
How to implement ?f 1
P1
P2
f 2
x 1 x 2 x 3
OR plane
Programmable
AND plane
connections
P3
P4
32131211 x x x x x x x f ++=
x1 x2 x3
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- Customary schematic for the PLA in previous Figure
- Constraint: size of AND plane (only 4 product terms)
f 1
P1
P2
f 2
x 1 x 2 x 3
OR plane
AND plane
P3
P4
x 1 x 2 x 3
PAL
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- Programmable switches present 2 difficulties in manufacturing
- PAL (Programmable Array Logic): programmable AND plane,
fixed OR plane -> less flexibility than PLA
f 1
P1
P2
f 2
AND plane
P3
P4
PAL
Select
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Extra circuitry added to OR-gate to provide additional functionality
f 1
To AND plane
D Q
Clock
SelectEnable
Flip-flop
FF represent a memory element, depend on signal clock that the
OR gate output will be hold at certain time point
Multiplexer selects output either from OR gate or from Q output
of the D-FF.
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A SPLD programming unit (courtesy of Data IO Corp).
CPLD
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Structure of a Complex Programmable Logic Device (CPLD).
PAL-likeblock
I / O b
l o c k
PAL-likeblock
I / O b l o c k
PAL-likeblock
I / O b l o c k
PAL-likeblock
I / O b l o c k
Interconnection wires
CPLD
CPLD Section
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A section of the CPLD
D Q
D Q
D Q
PAL-like block (details not shown)
PAL-like block - A CPLD consists of many
PAL-like blocks
interconnected via switches
-A commercial CPLD has 2-
100 PAL-like blocks
- Each PAL-l.b. has 3
macrocells.
- Each macrocell some OR
gates ….
CPLD Section
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CPLD packaging and programming.
(a) CPLD in a Quad Flat Pack (QFP) package
Printed
circuit board
To computer
(b) JTAG programming
FPGA
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A field-programmable gate array (FPGA).
-FPGA differ from CPLD (no
AND OR gates)
- Use logic blocks to implement
required functions
- 3 main resources: logic
blocks, I/O blocks,interconnect. wires & switches
- LB: 2-d array
- Interconnection: h. & v.
routing channels
FPGA
LUT
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A two-input lookup table (LUT)
- Each L.B. typically has a small number of inputs & outputs.
- The most commonly used L.B. is LUT (lookup table) which contains
storage cells. The stored values (0/1) is produced as the output of the
storage cell.
- LUTs have various sizes which are defined by number of inputs
LUT
Gate Multiplexer
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( ) ( ) 21211221
2121212121 ),,(
sx xs x x xs x x xs
xsx x xs x xs x xs x xs f
+=+++=
+++=
From Truth Table, derive canonical SOP form
Gate Multiplexer
x1 LUT Multiplexer
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A two-input lookup table (LUT).
(a) Circuit for a two-input LUT
x2
f
0/1
0/1
0/1
0/1
0
0
1
1
0
1
0
1
1
0
0
1
x1
x2
(b) f 1 x1 x2 x1 x2+=
(c) Storage cell contents in the LUT
x1
x2
1
0
0
1
f 1
f 1
- A two-variable TT has 4 rows
needs 4 cells.
- Three multiplexers controlled by
x1 & x2
- Explain principle ?
LUT Multiplexer
Example
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A three-input LUT.
f
0/1
0/10/1
0/1
0/10/1
0/1
0/1
x 2
x 3
x 1
Try to check its function by
using Truth Table …
Example
LUT Extra Circuit
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Inclusion of a flip-flop in an FPGA logic block.
Out
D Q
Clock
Select
Flip-flopIn1
In2
In3LUT
- The FF is used to store the value of its D input under control of its
clock input.
LUT Extra Circuit
x3 f
LUT in FPGA
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Section of a programmed FPGA.
0
10
0
0
1
1
1
0
00
1
x1
x2
x2
x3
f 1
f 2
f 1 f 2
f
x1
x2
- Two-input LUTs
- Four wires in each
routing channel- Fig. shows
programmed states of
the L.Bs. & switches
+ Blue switches: ON
+ Black switches: OFF
21
322
211
f f f x x f
x x f
+==
=
LUT in FPGA
Remarks
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- Each logic function must be small enough to fit within a single L.B.
- User’s circuit is automatically translated into the required form by
using CAD tools
- When a circuit is implemented in an FPGA, the L.B. areprogrammed to realize the necessary functions, and the routing
channels are programmed to make the required interconnections
between L.Bs.
- The storage cells in the LUTs in an FPGA are volatile: they lose theirstored values whenever the power supply for the chip is turned off.
- Instead of being re-programmed every time, a small memory chip
that holds its data permanently, called PROM, is included on the
circuit board that houses the FPGA. The storage contents are
automatically loaded from PROM to FPGA when power is applied to
the chips
Provide largest no of logic gates highest circuit speed lowest power
Custom Chip
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A section in a standard-cell chip. Chips made using this technology
are called ASICs (application-specific integrated circuits)
f 1
f 2 x1
x3
x2
- Provide largest no. of logic gates, highest circuit speed, lowest power
- Whereas a PLD is prefabricated, a custom chip is created from scratch
- The process of defining where trs. & wires are placed on chip is called CHIP LAYOUT
- A typical chip has many long rows of logic gates with a large number of wires between rows
+ Blue wire on one layer/ Black wire on another layer
+ Blue square: hard-wired connection (via) between layers
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A sea-of-gates gate array
f 1