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Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling

Track-And-Hold Circuit

Magnus DahlbäckLiTH-ISY-EX-3448-2003Linköping 5 January 2004

Implementation And Evaluation Of An RF Receiver Architecture Using An Undersampling

Track-And-Hold Circuit

Examensarbete utfört i Elektroniksystemvid Linköpings tekniska högskola

av

Magnus DahlbäckLiTH-ISY-EX-3448-2003

Handledare: Mark VesterbackaExaminator Mark Vesterbacka

Linköping 2004-01-05

Avdelning, InstitutionDivision, Department

Institutionen för systemteknik581 83 LINKÖPING

DatumDate2003-12-18

SpråkLanguage

RapporttypReport category

ISBN

Svenska/SwedishX Engelska/English

LicentiatavhandlingX Examensarbete

ISRN LITH-ISY-EX-3448-2003

C-uppsats D-uppsats

Serietitel och serienummerTitle of series, numbering

ISSN

Övrig rapport ____

URL för elektronisk versionhttp://www.ep.liu.se/exjobb/isy/2003/3448/

TitelTitle

Implementation och utvärdering av en RF-mottagare baserad på en undersamplande track-and-hold-krets

Implementation and Evaluation of an RF Receiver Architecture Using an Undersam-pling Track-and-Hold Circuit

Författare Author

Magnus Dahlbäck

SammanfattningAbstractToday's radio frequency receivers for digital wireless communication are getting more and more complex. A single receiver unit should support multiple bands, have a wide bandwidth, be flexible and show good performance. To fulfil these requirements, new receiver architectures have to be developed and used. One possible alternative is the RF undersampling architecture.

This thesis evaluates the RF undersampling architecture, which make use of an undersampling track-and-hold circuit with very wide bandwidth to perform direct sampling of the RF carrier before the analogue-to-digital converter. The architecture’s main advantages and drawbacks are identified and analyzed. Also, techniques and improvements to solve or reduce the main problems of the RF undersampling receiver are proposed.

NyckelordKeywordRF, track-and-hold, undersampling, receiver, noise folding, harmonics aliasing

Magnus Dahlbäck5/1/04

Abstract

Todays’ radio frequency receivers for digital wireless communication are getting more and more complex. A single receiver unit should support multiple bands, have a wide bandwidth, be flexible and show good performance. To fulfil these requirements, new receiver architectures have to be developed and used. One possible alterna-tive is the RF undersampling architecture.

The RF undersampling architecture, which make use of an under-sampling track-and-hold circuit with very wide bandwidth to per-form direct sampling of the RF carrier before the analogue-to-digital converter, is evaluated in this thesis. The architecture’s main advan-tages and drawbacks are identified and analyzed. Also, techniques and improvements to solve or reduce the main problems of the RF undersampling receiver are proposed.


1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.1 Main Thesis Questions. . . . . . . . . . . . . . . . . . . . 21.2.2 Motivation For The GSM900 Choice . . . . . . . . . 2

1.3 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.1 Prestudy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.2 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 Disposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.6 Reading instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 RF Receiver Basics . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 RF Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 The Generic RF Receiver. . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Theory Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3.1 Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.3.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3.3 Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . 82.3.4 Intermodulation . . . . . . . . . . . . . . . . . . . . . . . . . 92.3.5 Third-Order Intercept Point. . . . . . . . . . . . . . . . . 11

3 Mixer-Based Receiver Architectures . . . . . . . . . 13

3.1 The Mixer - An Introduction . . . . . . . . . . . . . . . . . . . . . 133.1.1 Downconversion. . . . . . . . . . . . . . . . . . . . . . . . . 133.1.2 Image Response . . . . . . . . . . . . . . . . . . . . . . . . 143.1.3 LO Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.1.4 Half-IF Response . . . . . . . . . . . . . . . . . . . . . . . . 153.1.5 LO Spurious Responses . . . . . . . . . . . . . . . . . . 15

3.2 The Superheterodyne Architecture. . . . . . . . . . . . . . . . 163.2.1 Component Density . . . . . . . . . . . . . . . . . . . . . . 163.2.2 Sensitivity And Selectivity. . . . . . . . . . . . . . . . . . 16

3.3 The Direct-Conversion Architecture . . . . . . . . . . . . . . . 173.3.1 Noise and Distortion Performance . . . . . . . . . . . 173.3.2 Component Density . . . . . . . . . . . . . . . . . . . . . . 18

Table of Contents


4 The RF Undersampling Architecture . . . . . . . . . 19

4.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . 194.1.1 Undersampling . . . . . . . . . . . . . . . . . . . . . . . . . . 204.1.2 Downconversion By Undersampling . . . . . . . . . 22

4.2 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234.2.1 Less Analogue Processing. . . . . . . . . . . . . . . . . 234.2.2 Multiple Frequency Bands . . . . . . . . . . . . . . . . . 244.2.3 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Noise Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.3.1 SNR Degradation . . . . . . . . . . . . . . . . . . . . . . . . 264.3.2 Sample Frequency Considerations . . . . . . . . . . 274.3.3 Front-End Gain. . . . . . . . . . . . . . . . . . . . . . . . . . 284.3.4 Further Reduction Of Performance Loss . . . . . . 294.3.5 Clock Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.4 Harmonics Aliasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.4.1 Low-Pass Filtering . . . . . . . . . . . . . . . . . . . . . . . 344.4.2 Changing Sample Frequencies . . . . . . . . . . . . . 34

4.5 T/H and ADC Integration Considerations . . . . . . . . . . . 354.5.1 Sample Clocks Frequencies. . . . . . . . . . . . . . . . 354.5.2 Clocks Phase Difference . . . . . . . . . . . . . . . . . . 35

5 Measurement Results . . . . . . . . . . . . . . . . . . . . . 37

5.1 Measurements Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 375.1.1 The T/H Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 375.1.2 T/H Measurements Setup . . . . . . . . . . . . . . . . . 395.1.3 T/H And ADC Integration Measurement Setup . 40

5.2 T/H Measurement Results . . . . . . . . . . . . . . . . . . . . . . 425.2.1 Downconversion. . . . . . . . . . . . . . . . . . . . . . . . . 425.2.2 Noise Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2.3 Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . 465.2.4 Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . 465.2.5 Two-Tone Intermodulation Distortion . . . . . . . . . 48

5.3 T/H And ADC Integration Measurement Results . . . . . 495.3.1 Clocks Phase Difference . . . . . . . . . . . . . . . . . . 495.3.2 Spectrum Response. . . . . . . . . . . . . . . . . . . . . . 505.3.3 Spectrum Response With Intermediate Filtering 51

Table of Contents


6 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566.1.1 Differential Signalling . . . . . . . . . . . . . . . . . . . . . 566.1.2 Double Scanning . . . . . . . . . . . . . . . . . . . . . . . . 566.1.3 Variable Sample Frequencies . . . . . . . . . . . . . . 58

7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.1 Recommended Literature . . . . . . . . . . . . . . . . . . . . . . . 59

Table of Contents


Table of Contents


List of Figures

Figure 2-1. The front-end, the analogue-to-digital interfaceand the Digital processing hardware. ................... 6

Figure 2-2. Harmonic distortion. ............................................. 8Figure 2-3. Power changes for harmonic signals. .................. 9Figure 2-4. Second- and third-order intermodulation

products................................................................ 10Figure 2-5. Third-order IMD rejection ratio. ............................ 10Figure 2-6. Floor of in-band IMD products.............................. 11Figure 2-7. Distortion from adjacent channels. ....................... 11Figure 2-8. Third-order intercept point. ................................... 12Figure 3-9. Frequency translation in a mixer. ......................... 13Figure 3-10. The image signal.................................................. 14Figure 3-11. LO leakage to RF input. ....................................... 14Figure 3-12. Half-IF spurious response. ................................... 15Figure 3-13. LO spurious responses. ....................................... 15Figure 3-1. The typical superheterodyne architecture. ........... 16Figure 3-2. The typical direct-conversion architecture............ 17Figure 4-1. The RF undersampling architecture. .................... 19Figure 4-2. The wide-band track-and-hold in front of the

ADC...................................................................... 20Figure 4-3. Frequency response of Nyquist sampling. ........... 21Figure 4-4. Aliasing distortion. ................................................ 21Figure 4-5. Frequency spectrum before undersampling......... 22Figure 4-6. Downconversion by undersampling. .................... 22Figure 4-7. Functional diagram for support of multiple RF

bands.................................................................... 24Figure 4-8. Signal spectrum before noise folding. .................. 25Figure 4-9. Signal spectrum after noise folding. ..................... 25Figure 4-10. Modelled SNR degradation versus sample

frequency.............................................................. 27Figure 4-11. total noise figure versus T/H noise figure and

front-end gain. ...................................................... 29Figure 4-12. Modelled SNR degradation due to noise folding

versus difference between in-band and out-band noise power density.............................................. 30

Figure 4-13. Expected T/H output spectrum for GSM downlink. .............................................................. 32

Figure 4-14. Expected ADC output spectrum for GSM downlink. .............................................................. 33


Figure 4-15. Aliasing of second-order harmonics. .................... 33Figure 4-16. Elimination of harmonics aliasing by low-pass

filtering.................................................................. 34Figure 4-17. Changing clock frequency may solve harmonics

aliasing. ................................................................ 34Figure 4-18. T/H output and ADC sampling.............................. 35Figure 5-1. RTH010 functional diagram.................................. 37Figure 5-2. Close-up of the T/H PCB...................................... 39Figure 5-3. T/H measurements setup. .................................... 39Figure 5-4. TH1 and TH2 out-of-phase clocking..................... 40Figure 5-5. The MP4 PCI card mounted in a PC. ................... 41Figure 5-6. T/H and ADC clocking. ......................................... 41Figure 5-7. T/H output spectrum confirms downconversion by

undersampling...................................................... 42Figure 5-8. T/H output spectrum for GSM Downlink signal in

first nyquist zone when sample frequency is 204.8 MHz. ........................................................... 43

Figure 5-9. T/H output spectrum for GSM Downlink signal in first nyquist zone when sample frequency is 819.2 MHz. ........................................................... 44

Figure 5-10. Measured SNR degradation versus. sample frequency. ............................................................ 45

Figure 5-11. T/H output harmonics when sample frequency is 204.8 MHz. ........................................................... 47

Figure 5-12. T/H output harmonics when sample frequency is 819.2 MHz. ........................................................... 48

Figure 5-13. Two-tone intermodulation distortion. .................... 49Figure 5-14. T/H output spectrum DC - 1 GHz. ........................ 50Figure 5-15. ADC output spectrum........................................... 51Figure 5-16. Low-pass filter output spectrum DC - 1 GHz........ 52Figure 5-17. ADC output spectrum with filter............................ 53Figure 6-1. Mathematical description for elimination of

even-order harmonics. ......................................... 56Figure 6-2. First scan (unattenuated input signal). ................. 57Figure 6-3. Second scan (attenuated input signal). ................ 58


Terminology

ADCAnalog-to-Digital Converter

dBDecibel

dBcDecibel relative to carrier

dBmDecibel relative to 1 mW

GSM900The 900 MHz GSM band

IFIntermediate Frequency

IIP3Third-Order Input Intercept Point

IMDIntermodulation Distortion

I/QIn-phase and quadrature-phase signals used for demodulation

LOLocal Oscillator

NFNoise Figure

Nyquist RegionWhen sampling, the frequency spectrum is often divided into Nyquist regions. The first Nyquist region is DC to half the sample

=

2

110log10

P

PdB

= −310 10

log10P

dBm


frequency, the second Nyquist region is half the sample frequency to the sample frequency and so on.

PCBPrinted Circuit Board

RFRadio Frequency

SFDRSpurious-Free Dynamic Range

SNRSignal-to-Noise Ratio

SDRSoftware Defined Radio

T/HTrack-and-Hold


1 Introduction

This is the thesis for the Master of Science in Computer Science and Engineering at Linköping Institute of Technology, Sweden. It was carried out as a research project at Swedish Defence Research Agency (FOI), Linköping, Sweden.

1.1 BackgroundTo meet up with increasing performance requirements, improve flex-ibility and shorten the design time of radio-frequency receivers, it is desirable to design an all-round receiver - a receiver with support for several frequency bands, multiple standards and different applica-tions. Therefore, functionality is to a great extent moved from analo-gue hardware to software implemented on digital hardware. This approach gives much flexibility since the analogue-to-digital conver-ter (ADC) is moved closer to the antenna and the receiver can be digitally configured to meet the current needs. Software Defined Radio (SDR) is today a general term for these types of configurable and programmable RF receivers.

However, there are still many improvements to be made before the ideal SDR receiver becomes a reality. The main problem with SDR receivers today is that as functionality is moved from analogue hard-ware to software, the ADC and digital-signal-processing (DSP) per-formance requirements increases drastically, especially the ADC requirements. To ease the ADC and DSP requirements, the signal must be down-converted from the high-frequency RF carrier band to a lower frequency band before the ADC.

The conventional technique to perform this frequency downconver-sion is to use a mixer circuit, see section 2.3. The mixer is used in the very common superheterodyne and direct-conversion receiver archi-tectures, which are further explained in chapter 3. However, several problems are related to the mixer and its functionality. To reduce these problems, additional analogue hardware is required, which is not desirable.

Chapter 1: Introduction 1


1.2 AssignmentDue to the desire of reducing analogue hardware to increase flexibi-lity and to eliminate some of the mixer related problems, it is desira-ble to find other architectures. One possible solution is the RF undersampling architecture.

The main goal of the thesis was therefore to implement and evaluate the RF undersampling architecture. In this architecture, a wide-band undersampling T/H circuit is placed in front of the ADC . Due to the nature of undersampling, see section 2.2, the RF signal is downcon-verted to a lower frequency manageable by the ADC. In other words, the T/H and ADC integration should result in a wide-band high-performance ADC.

The main intention with the RF undersampling architecture is to reduce the analogue component count and to increase the band-width and flexibility.

1.2.1 Main Thesis Questions

Questions that the thesis should answer are:

• What advantages does the RF undersampling architecture have over conventional mixer-based architectures?

• What problems are specific to the RF undersampling architec-ture and how are these solved?

1.2.2 Motivation For The GSM900 Choice

Within the scope of this thesis, but not the report, a single-channel GSM receiver was implemented to support the GSM900 band. Most theoretical examples and measurements are therefore done for GSM900 signals.

The GSM900 band was chosen due to the following reasons:

• Easy to find suitable components• Easier measuring and testing because of the density of GSM sig-

nals in the ether• Different signal sources types:

▲ Strong remote base stations▲ Weak local transmitter units

Section 1.2: Assignment2


1.3 MethodThe thesis’ main goal was divided into three sub-goals: Pre-study, measurements and evaluation.

1.3.1 Prestudy

To start with, the advantages and disadvantages by using an under-sampling T/H followed by an ADC to perform the frequency down-conversion of the RF signals were identified.

The pre-study phase consisted of an exhaustive study on existing material about downconversion techniques in RF receivers and other RF receiver architectures. This material included research papers, books, web sites etc.

1.3.2 Measurements

Next, lab measurements were performed to enable evaluation of the RF undersampling architecture and to verify the theoretical perfor-mance calculations. The measurements were performed for GSM900 signals.

1.3.3 Evaluation

After the measurements were performed, the results were analyzed and compared with the modelled results. It was of special concern to compare the performance with the mixer-based architectures to see what advantages and problems the RF undersampling architecture has compared with the most common architectures used today.

1.4 LimitationsThe accuracy of the T/H performance measurements was not extre-mely important. Rather, the measurements were supposed to give an indication of the main performance problems of the evaluated archi-tecture. For more detailed measurements, see [7].

The measurements and evaluation were only performed for the GSM900 band, since the primarily application FOI is interested of is for that band.

There was no focus on creating a finished product in the sense that the final receiver created in this thesis should be usable in live scena-

Chapter 1: Introduction 3


rios and real applications. The goal was to create a prototype to ena-ble performance evaluation and field tests.

1.5 DispositionChapter 2Gives an introduction to RF receivers and the most important con-cepts and theory.

Chapter 3Presents existing receiver architectures and their advantages and disadvantages.

Chapter 4Presents the RF undersampling architecture and describes its basic structure and properties.

Chapter 5Presents all measurements performed to evaluate the RF under-sampling architecture. The measurement results are analyzed and then compared with the modelled results.

Chapter 6In this chapter, conclusions are drawn and the main thesis questions are answered. Also, future work to improve the RF undersampling architecture are proposed.

1.6 Reading instructionsThis report is intended to be read by students at a Master of Science programme, typically Computer Science or Electrical Engineering. Basic knowledge about radio communication and signal theory is required.

Section 1.5: Disposition4


2 RF Receiver Basics

An introduction to the subject of wireless RF receivers is presented in this chapter as well as the most important theory concepts used in this thesis.

2.1 RF OverviewRadio frequency (RF) refers to an electromagnetic field with charac-teristics such that it is suitable for wireless broadcasting and commu-nication. The frequencies of these electromagnetic signals constitutes a very wide range of the electromagnetic spectrum, often defined from 9 kHz to 3 GHz. Frequencies above 3 GHz are sometimes defi-ned as RF, but more often they are referred to as the microwave spec-trum.

The RF spectrum can be divided into several bands. For example, the spectrum from 300 MHz to 3 GHz is defined as the Ultra High Fre-quency (UHF) band. The UHF band is further devided into more bands, where each band is allocated by a specific service or system. One example is the GSM system, which operates in the bands 890 MHz - 960 MHz (GSM900) and 1710 MHz - 1880 MHz (GSM1800).

The RF spectrum is used by many wireless communication systems, such as cellular telephony, WLAN, cordless communication, radio- and television broadcasts and satellite communication.

2.2 The Generic RF ReceiverThe main purpose of the RF receiver is to detect RF signals within a specific band and to extract the baseband information carried in the detected RF signal. To do this, the incoming RF signal has to be pro-cessed and modified, both by the analogue and digital hardware. This includes tasks such as:

• Filtering• Amplification• Frequency downconversion• Demodulation

Chapter 2: RF Receiver Basics 5


The hardware of all existing RF receivers can be divided into three main blocks: The analogue front-end, the analogue-to-digital inter-face and the digital signal processing (DSP).

FIGURE 2-1. THE FRONT-END, THE ANALOGUE-TO-DIGITAL INTERFACE AND THE DIGITAL PROCESSING HARDWARE.

The main tasks of the front-end are band-selection filtering, amplifi-cation and frequency downconversion. However, in the RF under-sampling architecture evaluated in this thesis, the front-end does not perform any downconversion. Instead, this is performed by the ana-logue-to-digital block.

The analogue-to-digital interface converts the analogue signal to a digital representation, which is then further processed by the DSP. The DSP often performs demodulation, channel filtering and appli-cation-specific algorithms.

2.3 Theory ConceptsAll concepts presented in this chapter are further explained in [4].

2.3.1 Noise Figure

Each receiver component adds noise to the desired signal. The amount of added noise is defined by its noise figure:

EQUATION 1

where S is the power of the desired signal and N is the noise power. F is called the noise factor and is the linear representation of the noise figure. By this definition, it is clear that a low noise factor is better than a high noise factor.

Front-end AD Interface

DSP

F

NS

NS

NF

out

out

in

in

1010 log10log10 =

=

Section 2.3: Theory Concepts6


The noise figure for a set of cascaded components cannot be calcula-ted by just adding the individual noise figures together. Instead, Friis’ equation is used:

EQUATION 2

The noise factors and gains for all N cascaded components are in linear numbers, not in dB. Notice that the equation above concerns total noise factor. The total noise figure is the decibel value of Ftot.

One important conclusion that can be drawn from Friis’ equation is that the noise performance degradation due to a high noise figure of a certain component can be decreased by having higher gain in the components before that component. It is also clear that the noise per-formance of the first component in the system is very important.

2.3.2 Sensitivity

The sensitivity of a receiver or a chain of cascaded components defi-nes the minimum acceptable signal strength at the input to obtain a certain SNR at the ADC output. It is defined as:

EQUATION 3

MDS is the abbreviation of minimum-detectable signal, which is the minimum signal strength that a signal can have before disappearing into the noise floor. SNRreq is the required signal-to-noise ratio in dB after the ADC digitization. As given by the equation above, MDS is defined as:

EQUATION 4

where n0 is the thermal noise power in dBm and NF is the cascaded noise figure of the component set. The thermal noise power at room

∏−

=

−++−+−+= 1

1

21

3

1

21

1...

11N

ii

Ntot

G

F

GG

F

G

FFF

reqreq SNRNFnSNRMDSS ++=+= 0

NFnMDS += 0



temperature for a certain bandwidth can be calculated using the fol-lowing expression:

2.3.3 Harmonic Distortion

No analogue component is perfectly linear. This is of great concern in RF receiver design, since the non-linearity gives rise to many difficult problems. Examples of such problems are harmonic distortion and intermodulation.

When a signal is applied at the input of a non-linear circuit, the out-put signal will contain several harmonics of that input signal, see figure 2-2. Harmonics are non-desired signals located at multiples of the fundemental signal frequency. Assume that the signal frequency f is 10 MHz in the example below. Then the harmonics will appear at 20 MHz, 30 MHz, 40 MHz and so on.

FIGURE 2-2. HARMONIC DISTORTION.

An interesting property of harmonics is that the amplitude changes in a different manner than the amplitude of the desired signal. The power change of a certain harmonic is directly related to the order of that harmonic. The N:th-order harmonic power changes with N times the power change of the fundamental signal.

As an example, assume that the input signal has a power of 4 dBm. Further assume that the circuit gives rise to a -40 dBm second harmo-nic (2f) and a -60 dBm third harmonic (3f). If the input signal strength is decreased by 6dB to -2 dBm, the second harmonic decreases to -52

Bn 100 log10174 +−=

f

2 f

3 f



dBm (2*6=12 dB change) and the third harmonic decreases to -78 dBm (3*6=18 dB change).

FIGURE 2-3. POWER CHANGES FOR HARMONIC SIGNALS.

This well-known behaviour can be used to differentiate the desired signal from its harmonics.

2.3.4 Intermodulation

As mentioned, non-linearity also causes intermodulation. When sig-nals with different frequencies are applied to the input of the non-linear component, the non-linearity gives rise to spurious distortion signals on other frequencies.

Intermodulation between two signals with different frequencies is called the two-tone intermodulation distortion. The intermodulation distortion products appear at frequencies defined by equation 5.

EQUATION 5

where f1 and f2 are the frequencies of the two input signals. The order of a certain intermodulation signal is defined as the sum of M and N.

f

2f

3f

4 dBm -2 dBm

-40 dBm

-52 dBm -60 dBm

-78 dBm

6 dB

12 dB

18 dB

,...3,2,1,0,,21 =±±= NMNfMfIMD



Figure 2-4 shows the typical output spectrum of a non-linear device where second- and third-order IMD products are shown. The two input signals are f1 and f2.

FIGURE 2-4. SECOND- AND THIRD-ORDER INTERMODULATION PRODUCTS.

The even-order products (f1-f2 and f1+f2) can be filtered out be the band-selection filters. However, the odd-order products, mainly the third-order products, are often impossible to filter out as they are located inside the desired band.

The power difference between the desired signal and the IMD pro-ducts is called the IMD rejection ratio. The power difference between the desired signal and the n:th-order IMD products is therefore cal-led the n:th-order IMD rejection ratio. Third-order rejection ratio decrease 2 dB for each 1dB increase of input signal power. In other words, the third-order IMD products power increase 3 dB for each 1 dB input signal level increase.

FIGURE 2-5. THIRD-ORDER IMD REJECTION RATIO.

In an RF receiver, intermodulation distortion causes two types of problems:

• Increased in-band noise• Distortion from adjacent channels

f1 f2

2f2-f1 2f1-f2 f1+f2

2f1+f2 f1+2f2

Passband

f1-f2

f1 f2

2f2-f1 2f1-f2 3rd-Order IMD Rejection Ratio



All in-band signals will intermodulate with each other and generate a wide in-channel floor of IMD products, see figure 2-6.

FIGURE 2-6. FLOOR OF IN-BAND IMD PRODUCTS.

Another problem is that the IMD products created in adjacent chan-nels can fall into the channel of interest.

FIGURE 2-7. DISTORTION FROM ADJACENT CHANNELS.

If the signal power of the adjacent channels is high and the channel of interest is weak, there is a risk that the desired channel will be totally drowned by the IMD products generated from other channels. Therefore, the linearity performance is very important in an RF recei-ver.

2.3.5 Third-Order Intercept Point

When the input signal strength is increased to a certain level, the out-put power of the desired signal and the power of the third-order IMD products will equal, i.e. the third-order rejection ratio is zero. The input power at this point is defined as the third-order input inter-cept point (IIP3).

Non-linear System

Non-linear System

Ch. 3 Ch. 5 Ch. 7 Ch. 3 Ch. 5 Ch. 7



To calculate IIP3 for a certain component, the linear region of the third-order IMD and the desired signal are extrapolated and the vir-tual intersection between the two lines sets the IIP3, see figure 2-8.

FIGURE 2-8. THIRD-ORDER INTERCEPT POINT.

The following relationship between the third-order intercept point and the third-order rejection ratio is often used:

EQUATION 6

where OIP3 is the output third-order intercept point, that is, IIP3 + gain.

Fundamental

3rd IMD

IIP3

1 1

1

3

Pout

Pin

2

33 out

out

RRPOIP +=



3 Mixer-Based Receiver Architectures

As already stressed, the main purpose of this thesis is to evaluate the RF undersampling receiver. To do this, it is necessary to know about the alternatives and their respective benefits and drawbacks. Thus, the intention of this chapter is to present existing receiver architectu-res and their properties, good as bad.

3.1 The Mixer - An IntroductionThe receiver designed in this thesis does not use any mixer to per-form the signal downconversion from RF to a lower frequency band. However, it is still necessary to study the mixer circuit and its pro-perties to make it possible to draw conclusions on whether it is prefe-rable to use an undersampling T/H instead of the conventional mixing technique, which is used in the superheterodyne and direct-conversion architectures, see sections 3.2 and 3.3. Problems related to the mixer circuit are common problems in the architectures based on it.

3.1.1 Downconversion

In a mixer-based RF receiver, the mixer circuit is used to translate RF carrier frequencies to a lower intermediate frequency (IF) .The trans-lation is performed by mixing (multiplying) a local oscillator (LO) signal with the RF signal. This results in one lower frequency and one higher frequency component. Figure 3-9 illustrates this effect.

FIGURE 3-9. FREQUENCY TRANSLATION IN A MIXER.

LO

RF RF+LO LO-RF

Chapter 3: Mixer-Based Receiver Architectures 13


The mathematical description of this behaviour is given by equation 7.

EQUATION 7

3.1.2 Image Response

It is possible that another RF signal, called the image signal, also will mix with the LO signal and distort the desired IF output. The image and LO frequencies are spaced apart by an amount equalling the dif-ference between the desired RF signal and the LO. The mixing will cause the image signal to end up on the same IF frequency as the RF carrier. The image signal must be removed by an RF image-reject fil-ter before the mixer. The sharpness requirement of this filter depends on the sample frequency used.

FIGURE 3-10. THE IMAGE SIGNAL.

3.1.3 LO Leakage

Another common problem related to the mixer is LO leakage. Due to parasitic conductances between the LO and RF ports, the LO signal can “leak“ to the RF input and vice versa.

FIGURE 3-11. LO LEAKAGE TO RF INPUT.

The result of this leakage is that the LO signal is mixed with itself and the output will therefore suffer from a DC offset due to a large zero-frequency component. If unlucky, this DC offset saturates the mixer and following circuits, which can lead to a severe performance

( ) ( )( )ttAA

tAtAty RFLORFLOLORF ωωωωωω ++−=×= sinsin2

sinsin)( 2121

LO RF

Image Signal LO-RF

Distortion!

LO

RF DC Offset

Section 3.1: The Mixer - An Introduction14


degradation. If the LO signal also leaks to a prior amplifier, the DC component can be much larger than the desired signal.

3.1.4 Half-IF Response

The mixer suffers from a problem called half-IF spurious response, which is similar to the image response problem. The undesired half-IF signal, fu, is located exactly between the RF signal and the LO sig-nal, see figure 3-12. The LO and its second harmonic are shown with solid spectral lines. The half-IF and the desired RF signal and their respective second harmonics are both shown in solid spectral lines.

FIGURE 3-12. HALF-IF SPURIOUS RESPONSE.

The second harmonic of the half-IF signal, called the half-IF spur, mixes with the second harmonic of the LO signal. This mixing will also produce an IF signal, shown with a dotted spectral line, located exactly on the desired IF output, which will be distorted.

3.1.5 LO Spurious Responses

The problem of LO spurious responses is similar to the image response problem, but instead of image signals mixing directly with the LO signal, they are mixed with the LO harmonics. All RF signals located one IF distance away from an LO harmonic will mix with the respective harmonic to produce a distorting IF signal. This behaviour is illustrated in figure 3-13, where the second and third LO harmo-nics are included.

FIGURE 3-13. LO SPURIOUS RESPONSES.

LO RF

2RF

LO-RF

Distortion! 2LO

fu 2fu

2LO-2fu

RF 2LO LO-RF

Distortion!

3LO

LO



3.2 The Superheterodyne ArchitectureThe superheterodyne architecture is the “classical” receiver architec-ture. It was first devised during the first world war and is still today the definitely most commonly used architecture for RF receivers. It is currently being challenged by other architectures, such as the direct-conversion and the RF undersampling architectures.

The single-conversion superheterodyne receiver front-end is shown in figure 3-1.

FIGURE 3-1. THE TYPICAL SUPERHETERODYNE ARCHITECTURE.

The distinguishing feature of the superheterodyne architecture is that the downconversion from RF to baseband is performed using one intermediate frequency stage. The RF signal is down-converted by a mixer to an IF frequency, where additional signal processing is performed. It is then down-converted to baseband and separated into its I- and Q components by the second mixer pair.

3.2.1 Component Density

As a consequence of its great performance, the superheterodyne receiver requires many analogue components, especially in the multi-stage cases. A high analogue component density is not desira-ble, since it implies limited flexibility, increased design- and manu-facturing costs, a larger chip area and high overall complexity.

3.2.2 Sensitivity And Selectivity

The superheterodyne receiver offers excellent selectivity. Selectivity is the ability to isolate the desired signal, that is, rejecting all non-desired signals. The reason for this is that the superheterodyne recei-ver operates on lower (IF) frequencies, which makes selective filte-ring more effective. The selectivity is especially high in multi-stage (more than one IF stage) superheterodyne receivers.

90°

LO

LO

ADC

ADC

Section 3.2: The Superheterodyne Architecture16


Another benefit of the superheterodyne receiver is its good sensiti-vity. A proper choice of IF frequency or IF frequencies improves IF amplification and filtering, leading to great overall sensitivity.

3.3 The Direct-Conversion ArchitectureThe direct-conversion architecture is a special case of the superhete-rodyne architecture. Due to its properties, it is also called zero-IF and homodyne architecture. Figure 3-2 shows the typical direct-conver-sion receiver front-end.

FIGURE 3-2. THE TYPICAL DIRECT-CONVERSION ARCHITECTURE.

As shown by the figure, the significant feature of the direct-conver-sion receiver is that the RF signal is converted directly to baseband, thereby its name. The downconversion process also splits the base-band signal into its inphase (I)- and quadrature-phase (Q) compo-nents for demodulation.

3.3.1 Noise and Distortion Performance

Together with these sought-after properties, some problems are introduced, see [1] ,such as

• DC-offset• 1/f-noise• Even-order distortion• I/Q mismatch

One of the main problems of the direct-conversion receiver is that it suffers from time-varying DC offsets. Insufficient LO-RF isolation causes LO-leakage to the signal prior to the mixer. The LO signal lea-kage component is then self-mixed in the mixer, which generates DC as a mixing product at the mixer output. The DC offset interfere with

90° LO

ADC

ADC



the desired signal and may saturate following circuits, such as the ADC.

Another problem is the flicker noise, denoted 1/f-noise. 1/f-noise is a low-frequency noise device noise that can distort signals in the receiver chain. The 1/f-noise is especially serious in direct-conver-sion receivers, due to the baseband signal processing.

The third problem also has to do with low-frequency noise. Two adjacent signals present at the LNA input may be affected by inter-modulation and generate a low-frequency even-order distortion component interfering with the desired signal.

The problems related to the direct-conversion strategy can nowadays be partially solved by careful receiver design and by utilizing special baseband signal processing algorithms. For example, the second-order IMD products can be minimized by using differential circuits and balanced transmission lines. The DC offset problem is handled by measuring the DC component and executing special algorithms.

The separation into the I and Q components is performed at RF fre-quency. Due to the high input frequency, there is a risk of mismatch between the I and Q signals, which will degrade the SNR.

3.3.2 Component Density

The direct-conversion receiver eliminates the IF stage because it down-converts the RF signal directly to baseband.. This drastically reduces the number of components. Without the IF stage, there is no need for the IF mixer or the IF LO.

Direct-conversion also eliminates the image-rejection problem because the image is the channel itself. It is therefore possible to also remove the image-reject filter.

Due to the reduced component number and the fact that the off-chip image-reject filter can be removed, the direct-conversion architecture is suitable for designs where cost, power consumption and chip area are central design parameters. A direct-conversion receiver is prefer-red when the entire receiver is to be implemented on a single chip.

Section 3.3: The Direct-Conversion Architecture18


4 The RF Undersampling Architecture

In this chapter, the RF undersampling architecture is presented. It describes the basic structure and properties of the RF undersampling architecture and how the architecture is realized. Also, the main workhorse of the RF undersampling architecture, the track-and-hold circuit, is described.

4.1 Architecture OverviewThe superheterodyne and the direct-conversion architectures both have important advantages but they also suffers from unwanted drawbacks. The intention with the RF undersampling architecture is to combine the benefits from these two architectures and eliminate the main problems. Primarily, the performance of the superhetero-dyne receiver and the low component count and flexibility of the direct-conversion architecture are desired.

The RF undersampling architecture is simple and straight-forward. The analogue RF front-end consists of band-specific gain stages and band-pass filters. The front-end is followed by a wide-band digiti-zing block.

FIGURE 4-1. THE RF UNDERSAMPLING ARCHITECTURE.

To make digitization of RF signals possible in the RF undersampling architecture, the digitizing block in figure 4-1 needs to be very fast and have a wide bandwidth. However, few ADC circuits fulfil both these requirements today. ADC’s that are fast enough to digitize RF signals often have a poor SFDR. Instead, in the RF undersampling

Digitizing

Block

Band-specific

Chapter 4: The RF Undersampling Architecture 19


architecture, a fast track-and-hold circuit with very wide bandwidth is placed in front of the ADC, see figure 4-2.

FIGURE 4-2. THE WIDE-BAND TRACK-AND-HOLD IN FRONT OF THE ADC.

The undersampling and downconversion is performed by the track-and-hold circuit, which eases ADC bandwidth and sample rate requirements drastically. The T/H and ADC together results in a very wide-band and fast digitizing block, where the T/H interfaces the high-frequency RF signals and down-converts them to a fre-quency manageable for the digitizing ADC circuit. This is the unique property of the RF undersampling architecture and thereby its name.

This solution is possible because track-and-hold circuits, at least the one used in this thesis, can have a much wider bandwidth, offer bet-ter sample performance and are overall more flexible than most ADC circuits.

The majority of the signal processing is performed in the digital domain, such as downconversion to baseband, additional filtering and demodulation.

4.1.1 Undersampling

To really understand the functionality of the RF undersampling architecture, it is necessary to understand the concept of undersamp-ling.

The sampling theorem states that to avoid aliasing distortion and to enable correct signal reconstruction for a band-limited signal, the sampling rate (assumed uniform) must be at least twice as high as the maximum signal frequency, i.e.,

EQUATION 8

where fS is the sampling frequency and fh is the highest frequency component of the desired signal.

T/H ADC

Undersampling Oversampling

RF IF

hS ff 2≥

Section 4.1: Architecture Overview20


This minimum sample rate is defined as the Nyquist sample rate. Prac-tically, the sample rate should be at least 2.5 times greater than the maximum signal frequency to relax anti-alias filter requirements.

Figure 4-3 shows the frequency response of a signal sampled by a signal with frequency 2fh = 600 MHz. No aliasing distortion exists.

FIGURE 4-3. FREQUENCY RESPONSE OF NYQUIST SAMPLING.

However, if the maximum frequency of the original signal would have been 400 MHz, that is, greater than half the sample frequency, the aliases would interfere with each other and result in signal distor-tion.

FIGURE 4-4. ALIASING DISTORTION.

Generally, it is not possible to perform Nyquist sampling of RF sig-nals. Sampling at Nyquist rate or above would require extremely high sample rates. For example, a 2.4 GHz signal would require a sample rate of at least 4.8 GHz. A high sample rate leads to a very high data rate, expensive sample circuits, troublesome generation of high-frequency clock signals and so on. Nyquist sampling of RF sig-nals is therefore not practically feasible.

To overcome this problem, undersampling can be used. Undersamp-ling is a modification of the Nyquist theorem, saying that the sample rate must be greater than twice the information bandwidth, rather

fS

fh 600 300 MHz

fS

fh 600 350 MHz

Aliasing Distortion



than twice the maximum frequency. This is expressed by equation 9, see [1].

EQUATION 9

where fIF is the intermediate frequency, fS is the sample frequency and BW is the signal bandwidth. The intermediate frequency is limi-ted by the inequality in equation 10:

EQUATION 10

4.1.2 Downconversion By Undersampling

Undersampling is a useful technique that can be used effectively in certain applications. The sampling device, in this case the T/H, will behave like a mixer in that it can take a high-frequency RF signal and produce an image of that signal at a lower frequency. In other words, it behaves like a down-converter, see [5].

Figure 2 shows the spectrum of an RF signal before undersampling. The RF signal is centered at 26 MHz with a bandwidth of 2 MHz. This signal is undersampled with a sample rate of 6 MHz. The resul-ting spectrum is shown in figure 4-6.

FIGURE 4-5. FREQUENCY SPECTRUM BEFORE UNDERSAMPLING.

FIGURE 4-6. DOWNCONVERSION BY UNDERSAMPLING.

22

BWf

fIF

S +>

2

BWfIF >

fS

fS

desired

Section 4.1: Architecture Overview22


Image signals appear at 2 MHz, 4 MHz, 8 MHz, 10 MHz and so on. The original RF signal is periodically aliased on the frequency axis at frequencies defined by equation 11.

EQUATION 11

Each Nyquist region contains one alias of the original signal. The sig-nal is mirrored in each multiple of half the sample frequency. All odd Nyquist zones contain a correct image of the original signal, whereas the frequency content in all even Nyquist zones is inverted, see [6].

It is now possible to select an identical image of the original RF signal at a much lower frequency, i.e. the undersampling has resulted in a downconversion of the RF signal. In the example above, the 2 MHz alias could be selected and digitally processed.

4.2 AdvantagesThe RF undersampling architecture has many advantages over con-ventional radio architectures. The most important advantages are discussed in this section.

4.2.1 Less Analogue Processing

Another key advantage of the RF undersampling architecture is the significant reduce of analogue components and analogue signal pro-cessing. This is possible due to the direct sampling of RF signals, which eliminates the following components

• IF filters• IF gain stages• Mixers• High-frequency LO:s

As the architecture has no IF stage, all corresponding filters and amp-lifiers can be removed. Further, as no mixer circuits are used, there is no need to generate high-frequency signals from the LO’s. The elimi-nation of all these circuits results in a substantial decrease of analo-gue component density and many problems related to these

,...2,1,0=⋅−=

k

fkff SRFk



components no longer exist, such as LO-leakage, image-signal dis-tortion and LO-jitter sensitivity.

Compared with the superheterodyne architecture, especially the multi-stage variant, the difference in amount of analogue compo-nents is substantial.

Analogue component density reduction and analogue processing have many advantages, such as:

• Increased flexibility• Lower power consumption• Area reduction• IF off-chip filters removed

4.2.2 Multiple Frequency Bands

Because of the undersampling strategy and the wide T/H band-width, the RF undersampling architecture enables receiver designs with possibility to support multiple frequency bands and bands loca-ted at several GHz without using mixers.

The functional diagram of a multi-band receiver using the RF under-sampling architecture is shown in figure 4-7.

FIGURE 4-7. FUNCTIONAL DIAGRAM FOR SUPPORT OF MULTIPLE RF BANDS.

A certain RF band is supported by simply selecting the correspon-ding front-end. This selection could be performed manually or dyna-mically at run-time by the software. Depending on which bands to supports, it may be necessary to make the T/H clock frequency vari-able.

The implemented receiver, which is not discussed in this report, sup-ports two RF bands, the GSM900 uplink and downlink, which are manually selected.

T/H ADC RF Band 1

RF Band N

Section 4.2: Advantages24


4.2.3 Flexibility

Since many tasks are moved from the analogue domain to the digital domain, the RF undersampling architecture offers much more flexi-bility than the mixer-based architectures. To simultaneously support different frequency bands, modulation schemes and so on, only the running software has to be changed. Several existing systems and services can be implemented in the same receiver and future stan-dards may also be supported without changing the hardware plat-form.

The possibility to reconfigure and extend the receiver functionality in a flexible manner is a very attractive property of the RF undersamp-ling architecture. Thus, this architecture is a great step closer to the SDR receiver.

4.3 Noise FoldingOne disadvantage of the RF undersampling architecture compared with the architectures presented in chapter 3 is the decreased noise performance due to the phenomena called noise folding. Noise folding is extra serious in the RF undersampling architecture due the under-sampling strategy and the wideband T/H.

To understand the noise folding problem and why it exists, study the example in figure 4-8.

FIGURE 4-8. SIGNAL SPECTRUM BEFORE NOISE FOLDING.

FIGURE 4-9. SIGNAL SPECTRUM AFTER NOISE FOLDING.

fS

fS



Assume the sampling frequency fS is 6 MHz and the desired signal is centered at 26 MHz with a 1 MHz bandwidth. This results in a downconversion of the desired signal to 2 MHz. However, all noise energy on the equivalent distance from all harmonics of the sample signal will also end up on 2 MHz and degrade the SNR ratio. The overall result is that noise folding increase the noise floor level of the entire output signal spectrum, as shown in figure 4-9.

4.3.1 SNR Degradation

The SNR degradation due to noise folding by undersampling can be approximated by the following expression, see [3]:

EQUATION 12

where S is the power density of the desired signal, Ni is the in-band noise power density, NO is the out-band power density and m is the largest k that fulfils equation 13, see [2].

EQUATION 13

where B is the sample device’s analogue input bandwidth. The above expression assumes that all sample signal harmonics give rise to an equal amount of folded noise.

The constant k determines how much noise will be folded into the desired signal’s Nyquist zone. The larger k is, the more noise will fold onto the signal and decrease the SNR.

Assume that the in-band noise power equals the out-band noise power. The SNR, and therefore also the noise figure, degradation in dB due to noise folding can then be expressed as:

EQUATION 14

( ) oi NmN

SSNR

1−+=

12

≥≤⋅ kBf

k S

( )mSNR dB log10deg, =

Section 4.3: Noise Folding26


4.3.2 Sample Frequency Considerations

According to equations 12 to 14, the SNR degradation is decreased by avoiding a low sampling frequency relative to the signal pass-band. A low sample frequency leads to more aliases and therefore noise will fold back into the desired band.

Due to this, it is wise to choose the highest possible sample frequency that still undersamples the RF signal and down-converts it to the desired intermediate frequency.

Figure 4-10 shows the theoretical SNR degradation versus sample frequency for three different T/H bandwidths. Notice that the noise power density is assumed to be constant over the entire T/H band-width. The in-band noise power density is assumed to be equal to the out-band noise power density.

FIGURE 4-10. MODELLED SNR DEGRADATION VERSUS SAMPLE FREQUENCY.

The graph shows that doubling the sample frequency increases the SNR by 3 dB.

0

5

10

15

20

25

100 200 300 400 500 600 700 800 900 1000

Sample Frequency (MHz)

SN

R D

egra

dat

ion

(d

B)

1

5

9

Bandwidth(GHz)



4.3.3 Front-End Gain

The SNR degradation leads to a noise figure degradation by the same amount, which implies that the noise figure of an undersamp-ling T/H is large.

However, the cascaded noise figure and total receiver sensitivity can be kept relatively unaffected by providing enough front-end gain. Since the T/H is located after the front-end, the T/H noise figure is suppressed by the front-end gain, see section 2.1.1.

Assume the front-end noise figure is 7 dB. This implies a front-end noise factor of approximately 5. The total noise figure is calculated using equation 15.

EQUATION 15

−+⋅=

−+⋅=−−

−endfront

HT

endfront

HTendfronttot G

F

G

FFNF

15log10

1log10 /

10/

10



The graph in figure 4-11 shows the total receiver noise figure as a function of the T/H noise figure and the front-end gain. The front-end noise figure is assumed to be 7 dB.

FIGURE 4-11. TOTAL NOISE FIGURE VERSUS T/H NOISE FIGURE AND FRONT-END GAIN.

For front-end gains above 40 dB, the total noise figure is approxima-tely constant (7 dB) for a T/H noise figure between 10 dB and 40 dB. The T/H noise figure doesn’t really affect the total noise figure at all for a normal frant-end gain.

If the front-end gain is decreased, the T/H noise figure becomes much more important, as the graph illustrates.

4.3.4 Further Reduction Of Performance Loss

The performance loss due to noise folding does not only depend on the sample frequency. It also depends directly on the following fac-tors:

• Stop-band attenuation

0

2

4

6

8

10

12

14

10 12 14 16 18 20 22 24 26 28 30

T/H Noise Figure (dB)

To

tal N

ois

e F

igu

re (

dB

)

20

30

40

Front-End Gain (dB)



• T/H bandwidth and noise performance• Clock quality

The amount of folded noise can be reduced by using high-quality band-select filters before sampling. The RF bandpass filter is an important component since its purpose is to attenuate out-band noise before downconversion. Due to the nature of noise folding, it is especially important that the filter provide enough attenuation over the entire T/H bandwidth, rather than it has sharp passband edges.

From figure 4-12 we see that if the out-band noise can be attenuated to a certain level below the in-band noise power, the SNR degrada-tion due to noise folding is reduced to approximately zero. For smal-ler attenuation factors, a 1 dB attenuation of out-band noise compared to in-band noise implies a 1 dB SNR improvement.

The in-band noise power density is -100 dBm, the analogue input bandwidth is 9 GHz and the input signal power is -50 dBm.

FIGURE 4-12. MODELLED SNR DEGRADATION DUE TO NOISE FOLDING VERSUS DIFFERENCE BETWEEN IN-BAND AND OUT-BAND NOISE POWER DENSITY.

0

5

10

15

20

25

30

35

0 10 20 30 40 50

Nin-band - Nout--band (dB)

SN

R D

egra

dat

ion

(d

B)

100

500

1000




However, certain noise sources cannot be filtered out by the band-select filters, such as:

• Switching noise• Thermal noise• Quantization noise (for ADC)

Quantization noise and thermal noise are both of wide-band nature and will always alias to the desired band. Therefore, also the T/H cir-cuit’s own noise performance is important to reduce loss due to noise folding. Also, the T/H bandwidth should not be unnecessary wide.

4.3.5 Clock Noise

Sampling clock aperture jitter shows up as input noise. If the jitter is white, also the signal will show a white noise floor which is included in the noise folding. The SNR due to jitter depends on the sample fre-quency according to equation 16.

EQUATION 16

where fin is the input signal frequency in Hz and SNRclk is the signal-to-noise ratio of the sample clock. Again we see that a high clock fre-quency is preferable. If the clock noise is dominating the total T/H noise, the clock frequency choice becomes very important.

The SNR due to aperture jitter for a full-scale input signal is always limited by:

EQUATION 17

where ∆t is the standard deviation aperture jitter in seconds. The maximum allowed aperture jitter depends on the resolution of the ADC following the T/H. To ensure that the T/H jitter does not

clkin

clkj SNR

f

fSNR

2

=

( )tfSNR inj ∆−≤ π2log20



degrade the ADC SNR performance, the jitter must fulfil the follo-wing inequality:

EQUATION 18

4.4 Harmonics AliasingFigure 4-13 shows the T/H output spectrum of the GSM900 down-link band (925 MHz - 960 MHz) after undersampling with clock fre-quency 819.2 MHz. According to undersampling theory, the first Nyquist band (0 MHz to 409.6 MHz) will contain the following alias:

• Downlink alias (105.8 MHz - 140.8 MHz, a1 in figure)

whereas the second Nyquist band (409.6 MHz to 819.2 MHz) will contain the following alias:

• Frequency-mirrored downlink alias (678.4 MHz to 713.4 MHz, a2 in figure)

FIGURE 4-13. EXPECTED T/H OUTPUT SPECTRUM FOR GSM DOWNLINK.

The ADC samples this signal with a sample frequency of 204.8 MHz. This leads to that a1 is mirrored in fs/2 so that another alias is created at 64 MHz to 99 MHz (a3 in the figure 4-14). The two aliases a1 and a3 are periodically repeated by the sample frequency, so that each ADC

Ninf

t26

1

π≤∆

fs=819.2

MHz 200 400 600 800 0

GSM900 Downlink

fs/2=409.6

105.8- 140.8

678.4- 713.4

a1 a2

Section 4.4: Harmonics Aliasing32


Nyquist region contains exactly one alias of the original downlink signal. The a1 alias is digitally selected and processed.

FIGURE 4-14. EXPECTED ADC OUTPUT SPECTRUM FOR GSM DOWNLINK.

However, the spectrum response above does not take non-linearity effects into account. In reality, the T/H circuit will give rise to harmo-nics and spurious signals causing distortion when sampled by the ADC. Figure 4-15 illustrates how the second-order harmonics of the desired signal at the T/H output will alias during ADC sampling and interfere with the desired band. I call this problem harmonics alia-sing.

FIGURE 4-15. ALIASING OF SECOND-ORDER HARMONICS.

In this example, the desired band is located between 105.8 MHz and 140.8 MHz. The second-order harmonics of this band are shown in the figure and located between 211.6 MHz and 281.6 MHz. When this spectrum is sampled by the ADC, the second-order harmonics are mirrored in 204.8 MHz so that the desired signal is distorted by alia-sed harmonics.

There are two possible solutions to the problem of harmonic aliasing:

• Low-pass filtering• Changing sample frequencies

MHz 200 400 600 800 0

GSM900 Downlink

105.8- 140.8

678.4- 713.4

fs=204.8 fs/2=102.4

64- 99

a1 a2 a3

MHz 200 400 0

105.8- 140.8

fs=204.8 fs/2=102.4 64- 99

2nd Harmonics

Distortion



4.4.1 Low-Pass Filtering

The most effective solution to aliasing of harmonics and spurious signals is to low-pass filter the T/H output. In this way, the harmo-nics and spuriouses can easily be attenuated. In the example above, the filter should have a cut-off frequency at about fc = 150 MHz, see figure 4-16.

FIGURE 4-16. ELIMINATION OF HARMONICS ALIASING BY LOW-PASS FILTERING.

However, filtering is not a desirable solution. By placing a filter bet-ween the T/H and the ADC, the possibility to support multiple bands is drastically decreased. The filter makes it more difficult to find an appropriate T/H sampling frequency and the filter band-width limits the set of supported RF bands.

4.4.2 Changing Sample Frequencies

Harmonics aliasing may also be solved by changing the sample clocks frequencies. In the GSM900 downlink example above, increa-sing the ADC clock from 204.8 MHz to 307.2 MHz would eliminate aliasing of the second-order harmonics into the desired band, see the figure below.

FIGURE 4-17. CHANGING CLOCK FREQUENCY MAY SOLVE HARMONICS ALIASING.

MHz 200 400 0

105.8- 140.8

fs=204.8 fs/2=102.4 64- 99

fc=150

MHz 200 400 0

fs=307.2 fs/2=153.6

2nd Harmonics

Section 4.4: Harmonics Aliasing34


However, changing the sample frequency is probably not generally valid. Also, harmonics other than the second-order ones may cause interference instead.

4.5 T/H and ADC Integration Considerations

4.5.1 Sample Clocks Frequencies

The result of the T/H and ADC integration is that the signal is samp-led twice before being digitized. It is first undersampled by the T/H and then Nyquist sampled by the ADC.

It is therefore important to have a clear frequency plan to minimize performance loss due to spurious signals and alias distortion. Thus, the T/H clock frequency choice depends on the ADC clock frequency and vice versa, as well as on the RF bands of interest. Therefore, the first design question concerning the RF undersampling architecture to answer is the choice of the T/H and ADC clock frequencies.

The T/H and ADC used in this thesis to evaluate the RF undersamp-ling architecture have clock frequencies of 819.2 MHz and 204.8 MHz, respectively.

4.5.2 Clocks Phase Difference

Another important question is how the phase of the ADC clock rela-tive to the T/H clock affects the performance. The reason for this is in the basic function of a T/H circuit.

When the T/H samples a signal, it starts charging or discharging a capacitive load until the voltage over that load equals the sample voltage, see figure 4-18.

FIGURE 4-18. T/H OUTPUT AND ADC SAMPLING.

There is a risk that the ADC samples the T/H output signal before the signal has reached the correct voltage level. It is also possible that

Ideal ADC Sampling Point

Acquisition Interval

Invalid ADC Sampling Point

CLK2

T/H2 Output



that the signal frequency at the sampling point is not within the ADC’s bandwidth, leading to an invalid output. Therefore, it is important that the ADC clock samples the T/H output during the acquisition interval shown in figure 4-18.

Section 4.5: T/H and ADC Integration Considerations36


5 Measurement Results

All measurements performed to evaluate the RF undersampling architecture are presented in this chapter. The measurement results are analyzed and then compared with the modelled results.

5.1 Measurements Setup

5.1.1 The T/H Circuit

The circuit chosen to perform the undersampling and downconver-sion of the RF signals is the RTH010 track-and-hold from Rockwell Scientific.

The RTH010 is suitable for undersampling applications due to the following reasons:

• 9 GHz full-scale range bandwidth (small signals)• Wide range of clock frequencies• Provides a held output for more than a half clock period, relax-

ing bandwidth requirements of the subsequent ADC• Independent clocking of the two T/H circuits (as low as 100

MHz)

FIGURE 5-1. RTH010 FUNCTIONAL DIAGRAM.

The RTH010 has differential input-, output and clock signals and cas-cades the two internal T/H circuits. The first T/H is optimized for dynamic range, bandwidth and jitter, whereas the second T/H is

T/H1 T/H2 OUT- BUF

BUF2

BUF1

CLK1A CLK1B CLK2A CLK2B TMS

OUTP

OUTN

INP

INN

Chapter 5: Measurement Results 37


optimized for noise and low gain loss. The most important parame-ter specifications of the RTH010 T/H are listed in table 1.

TABLE 1: CENTRAL SPECIFICATIONS OF THE RTH010 TRACK-AND-HOLD

Figure 5-2 shows a close-up of the T/H board, with the RTH010 cir-cuit in focus. The T/H board was not designed in this thesis. Instead

Parameter Note Typical Value

Input Bandwidth -3 dB Gain, < 0.1 Vpp

-3 dB Gain, 0.5 Vpp

-3 dB Gain, 1 Vpp

9 GHz

8 GHz

6 GHz

Clock Frequency CLK1 (T/H1)

CLK2 (T/H2)

200 - 1000 MHz

100 - 1000 MHz

Harmonic Rejec-tion Ratio (Worst Harmonic)

1020 MHz, 1 Vpp Input

1020 MHz, 0.5 Vpp Input

60 dB

65 dB

Integrated Noise Input Referred, Hold Mode, 500 MHz clock

550 µV

Integrated Noise Input Referred, Track Mode, 500 MHz clock

400 µV

Full Scale Range 1000 mVpp

Input Resistance Each Lead to Ground 50 Ohm

Output Swing 50 Ohm Input Resistance,1 Vpp Input

0.8 Vpp

Section 5.1: Measurements Setup38


a complete evaluation board from the T/H vendor, with the T/H already mounted, was used.

FIGURE 5-2. CLOSE-UP OF THE T/H PCB.

5.1.2 T/H Measurements Setup

To measure the RTH010 performance and evaluate the RF under-sampling, the setup shown in figure 5-3 was used.

FIGURE 5-3. T/H MEASUREMENTS SETUP.

Signal Generator

Clock Generator

T/H PCB

Two-way 180° Splitter

Power Splitter

Power Splitter T

wo

-way

18

0° S

plit

ter

Hybrid Junction PCB

Spectrum Analyzer



The Hewlett Packard 8648C signal generator generates a GSM900 signal, which is made differential by a 180° splitter before being app-lied at the T/H input.

The clock is generated by the Rhode & Schwarz SMY 01 signal gene-rator. First, the clock signal is split into a 180° differential signal to support the T/H differential clocking. These two signals are then power splitted into two signals each, making a total sum of four clock signals - CLK1A, CLK1B, CLK2A and CLK2B. This allows for out-of-phase clocking of the TH1 and TH2 internal T/H circuits, which is the clocking scheme used in all tests, see figure 5-4.

FIGURE 5-4. TH1 AND TH2 OUT-OF-PHASE CLOCKING.

The differential T/H output is terminated, AC coupled and made single-ended by the hybrid junction board. The hybrid junction out-put is then analyzed by a spectrometer.

5.1.3 T/H And ADC Integration Measurement Setup

The ADC is placed on a PCI-based daughterboard called MP4. Except from digitizing the analog signal, the MP4 board also per-forms digital signal processing and transfers the digital data to soft-ware running on the local PC machine.

Section 5.1: Measurements Setup40


The ADC performance was measured by logging the digital signal via the PCI bus using a software program running on the local PC.

FIGURE 5-5. THE MP4 PCI CARD MOUNTED IN A PC.

When the clock frequencies were decided and phase difference mea-surements were completed, the clock distribution shown in figure 5-6 was decided to be used. A clock with frequency fS,TH = 819.2 MHz is generated by a local oscillator. This clock is then split into two paths, where the ADC clock frequency is divided by 4, so that fS,ADC = fS,TH/4 = 204.8 MHz.

FIGURE 5-6. T/H AND ADC CLOCKING.

ADC T/H

Frequency Divider (4x)

LO

819.2 MHz 204.8 MHz



5.2 T/H Measurement Results

5.2.1 Downconversion

The downconversion effect of undersampling was confirmed using a continous 940 MHz (GSM900 downlink) input signal and a 819.2 MHz clock. Figure 5-7 shows the T/H output spectrum from DC to 3 GHz.

Observe that the increasing attenuation by frequency is caused by the hybrid junction, which has a bandwidth of only 500 MHz.

FIGURE 5-7. T/H OUTPUT SPECTRUM CONFIRMS DOWNCONVERSION BY UNDERSAMPLING.

As the spectrum shows, each nyquist region contains exactly one alias of the original input signal, where the aliases are mirrored in half the sample frequency and in each multiple of it.

The signal marked “Down-Converted Signal“ is located in the first nyquist region at (940 - 819.2) MHz = 120.8 MHz and is the desired signal. The weaker signals (-55 dBm and below) located in the first nyquist region are harmonics of the desired signal and aliased har-monics of the input signal, see section 5.3.2 for more details.

Input Signal

Clock Frequency

Down-Converted Signal

1st Nyquist 2nd Nyquist 3rd Nyquist

Section 5.2: T/H Measurement Results42


5.2.2 Noise Folding

In the previous chapter, it was found that the SNR degradation due to noise folding is directly proportional to the sample frequency and the T/H analogue input bandwidth.

To evaluate this, two tests were performed. In the first test, the conti-nous 940 MHz signal was undersampled by a clock with frequency identical to the ADC clock frequency, that is, 204.8 MHz. The output spectrum of the GSM downlink band in the first nyquist region is shown in figure 5-8.

FIGURE 5-8. T/H OUTPUT SPECTRUM FOR GSM DOWNLINK SIGNAL IN FIRST NYQUIST ZONE WHEN SAMPLE FREQUENCY IS 204.8 MHZ.

The first Nyquist region alias of the 940 MHz signal is located at 84 MHz, as expected.

As seen by the spectrum above, the noise floor within the specific region is located at about -101 dBm. Notice that the resolution band-

MHz 849408.2045 =−⋅=IFf



width of the spectrum analyzer is 1 kHz, which would imply a noise power density of approximately -131 dBm/Hz:

In the second test, the clock frequency was increased four times to 819.2 MHz.. According to the calculations in section 4.3.1, this would imply a 6 dB improvement of the noise floor level:

The new output spectrum is shown in figure 5-9. The noise power density is now decreased from -131 dBm/Hz to approximately -137 dBm/Hz:

That corresponds to a 6 dB improvement.

FIGURE 5-9. T/H OUTPUT SPECTRUM FOR GSM DOWNLINK SIGNAL IN FIRST NYQUIST ZONE WHEN SAMPLE FREQUENCY IS 819.2 MHZ.

( ) HzdBmN /1311000log101018.204 −=−−=

( ) dBSNR 64log10deg ==

( ) HzdBmN /1371000log101072.819 −=−−=



Next, SNR measurements were performed for nine different sample frequencies from 200 MHz to 1000 MHz. Figure 5-10 shows the modelled SNR degradation (dashed line) and the measured SNR degradation (solid line) using the spectrum analyzer.

FIGURE 5-10. MEASURED SNR DEGRADATION VERSUS. SAMPLE FREQUENCY.

The measured results follows the logarithmic behaviour relatively well. Thus, the relationship between sample frequency and noise figure degradation seems to be true.

However, the measured values are about 4 dB less than the modelled values over the entire range of sample frequencies. One possible rea-son for this is that the model assumes that all aliases will contribute with the same amount of noise, which may not be the case.

7

9

11

13

15

17

19

21

200 300 400 500 600 700 800 900 1000


SN

R D

egra

dat

ion

(d

B)

Modelled

Measured



5.2.3 Noise Figure

The T/H noise figure was measured by calculating the difference between the input noise power density and the output noise power density and then adding the gain to this value, see equation 19.

EQUATION 19

By figure 5-9 we saw that the output noise power for a 819.2 MHz sample clock is approximately -137 dBm/Hz. The input power den-sity (at 940 MHz) was measured to approximately -150 dBm/Hz. The signal gain through the entire measurement setup is -9 dB. The-refore, the noise figure for the given sample frequency and input fre-quency is 22 dB:

EQUATION 20

However, a certain amount of the input noise measured by the spec-trum analyzer is generated by the spectrum analyzer itself. The true input signal noise power density may be as low as -160 dBm/Hz. The noise figure could therefore be approximately 10 dB greater than 22 dB.

However, as shown in section 4.3.3, the T/H noise figure really doesn’t affect the total noise performance of the typical RF receiver, since the front-end gain is often large enough to suppress the T/H noise figure.

Also, the exact value of 22 dB is not that important. Instead, the important conclusion from the measurement is that the noise figure is significantly higher than the typical noise figure of a mixer circuit, which is approximately 10 dB.

5.2.4 Harmonic Distortion

A high clock frequency also reduce the in-band harmonic distortion. By selecting a clock frequency in an intelligent manner, it is possible to ensure that all signal harmonics fall outside the frequency band of interest.

GainNNGainSSSNRSNRNF inputoutputinputoutputoutputinput −−=+==−=

( ) ( ) dBNF 229120107 =−−−−−=



Figure 5-11 shows the spectrum of the first Nyquist region of a 955 MHz signal sampled by a 204.8 MHz clock. The worst (second) har-monic is located in-band (about 2 MHz from desired signal) and the-refore it cannot be filtered out.

The second-order and third-order harmonic distortion rejection ratio is approximately 48 dB and 50 dB, respectively, for the present input signal strength. This is not as good as the data-sheet specification, but still acceptable.

FIGURE 5-11. T/H OUTPUT HARMONICS WHEN SAMPLE FREQUENCY IS 204.8 MHZ.

The noise floor is set by the source and the spectrum analyzer.



However, if the clock frequency is increased to 819.2 MHz, all har-monics are located outside the desired band, see figure 5-12. Notice that the frequency range is DC to 409.6 MHz.

FIGURE 5-12. T/H OUTPUT HARMONICS WHEN SAMPLE FREQUENCY IS 819.2 MHZ.

5.2.5 Two-Tone Intermodulation Distortion

The RTH010 data-sheet does not specify two-tone intermodulation distortion. Therefore, to measure this, two input signals were combi-ned and applied at the T/H input.

The signal frequencies were 940 MHz and 941 MHz, both with a sig-nal strength of -5 dBm. The output spectrum shown in figure 5-13 is for a 819.2 MHz sample frequency. The noise floor is set by the source and the spectrum analyzer.

As seen by the figure, the third-order IMD products appear at the expected frequencies, that is, 119.8 MHz and 122.8 MHz. They both have a power of -60 dBm, whereas the two main signals are -15 dBm. The 10 dB loss is mainly due to the cables and the hybrid junction



board. The third-order intermodulation distortion rejection ratio is -15 dBm - (-60 dBm) = 45 dB.

FIGURE 5-13. TWO-TONE INTERMODULATION DISTORTION.

The output third-order intercept point is 7.5 dBm.:

The exact value of OIP3 is not that important. The main purpose of this measurement was to roughly compare the intercept point bet-ween this T/H circuit and the typical mixer IP3, which is approxima-tely equal to the measured value.

5.3 T/H And ADC Integration Measurement Results

5.3.1 Clocks Phase Difference

Since the T/H and the ADC are located on separate boards, it is very difficult to control the clock phase difference. However, all tests have

dBmRR

POIP outout 5.7

2

4515

2

33 =+−=+=



shown that the problem described in section 4.5.2 is unlikely to appear. The main reason for this is probably that the T/H circuit’s rise time is very small relative to the ADC clock period.

In future implementations of the RF undersampling architecture it is recommended to have the T/H and the ADC on the same board so that the clock phase can be controlled.

5.3.2 Spectrum Response

The T/H input signal frequency is 955 MHz and the T/H sample fre-quency is 819.2 MHz. The T/H output spectrum from DC to 1 GHz measured by the spectrum analyzer is shown in figure 5-14.

FIGURE 5-14. T/H OUTPUT SPECTRUM DC - 1 GHZ.

Two aliases of the input signal are generated at 135.8 MHz and 683.4 MHz. The second- and third-order harmonics of the low-frequency alias are labeled “Alias Harmonics“. Also, the harmonics of the 955 MHz input signal are aliased down to the second Nyquist zone. As shown, the spectrum of the first and second Nyquist zones are filled with non-desired signals, such as harmonics, aliased harmonics and one signal alias. When the signal above is sampled by the ADC with a sample frequency of 204.8 MHz, some of the non-desired signals will alias into the desired band.

Input Signal Signal Aliases

Alias Harmonics Input Signal Harmonics (Aliased)

Section 5.3: T/H And ADC Integration Measurement Results50


The ADC output signal was logged and its FFT was computed and plotted using Matlab. The resulting spectrum is shown in figure 5-15. By studying this spectrum, it is clear that some of the non-desired signals have aliased into the desired band, for example the second- and third-order harmonics of the 135.8 MHz ADC input signal. These are marked with the two arrows in figure 5-15.

FIGURE 5-15. ADC OUTPUT SPECTRUM.

Please notice that the distortion is more worse than it appears to be by the spectrum above due to the unintentional attenuation of non-desired signals caused by the hybrid junction.

5.3.3 Spectrum Response With Intermediate Filtering

From the last chapter it was found that low-pass filtering the T/H output should reduce the total harmonic distortion. To evaluate this, the previous measurements were performed again, but now with a 150 MHz low-pass filter placed at the hybrid junction output.

0 51.2 102.4 153.6 204.8-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

dBc

MHz



The filtered T/H output spectrum is shown is figure 5-16. As seen, the filter removes the majority of the non-desired signals shown in figure 5-14.

FIGURE 5-16. LOW-PASS FILTER OUTPUT SPECTRUM DC - 1 GHZ.

The reduction of non-desired harmonics and aliases, compared to the non-filtered case, implies that the ADC output distortion is decreased. Figure 5-17 shows the FFT spectrum of the ADC output. By comparing this spectrum with the spectrum in figure 5-15, it is clear that the distortion rejection is reduced. For example, the third-



order harmonic is no longer present and the second-order harmonic power is reduced by approximately 5 dB.

FIGURE 5-17. ADC OUTPUT SPECTRUM WITH FILTER.

0 51.2 102.4 153.6 204.-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

dBc

MHz



6 Conclusions

In this chapter, conclusions about the RF undersampling architec-ture are drawn and answers to the main thesis questions are given. Also, techniques to improve the performance of the RF undersamp-ling architecture are proposed.

This thesis has shown that the RF undersampling architecture has several advantages over the most common architectures used today. First of all, the component density, especially for the analogue domain, is reduced. This is a very attractive property since several problems are eliminated. Also, analogue design is often expensive and limits the receiver flexibility.

Another major advantage is that the wideband T/H enables direct digitization of the entire RF spectrum within the T/H bandwidth. Thus, the RF undersampling architecture promotes multi-band and wide bandwidth implementations.

Due to folding of wide-band noise into the desired IF band, the RF undersampling architecture suffers from worse noise performance than other architectures. Both the theoretical studies and the perfor-med measurements shows that the performance degradation due to noise folding is directly dependent on the sample frequency in choice. The higher the sample frequency the less noise folds into the desired band.

However, the theoretical studies have also shown that the noise fol-ding is not a problem in the typical RF undersampling receiver. If enough gain is provided by the front-end, the total performance degradation due to noise folding is very limited.

A high T/H sample frequency does not only decrease noise folding, it also improves SNR degradation caused by clock noise and aper-ture jitter. A third factor pleading for use of a high sample frequency is that the signal harmonics generated by the T/H circuit may easily end up inside the desired IF band if a low sample frequency is used.

Since the performance loss caused by noise folding can be effectively suppressed, the greatest performance problem with the RF under-sampling architecture is harmonics aliasing. Harmonics aliasing

Chapter 6: Conclusions 55


increase the total harmonic distortion of the ADC output due to alia-sing of the T/H output harmonics, spurious signals and other sig-nals. In this sense, the T/H undersampling suffers from similar problems as the mixer circuit does.

The harmonics aliasing problem can be eliminated or reduced by low-pass filtering the T/H output. This is performed in the same manner as in all mixer-based architectures, where the mixer output is low-pass filtered. However, this comes at the cost of lost flexibility, multi-band support and increased component density.

6.1 Future Work

6.1.1 Differential Signalling

By using differential signalling between the T/H and the ADC, all even-order harmonics are cancelled. This may drastically reduce the performance loss due to ADC aliasing of T/H harmonics.

To understand why the even-order harmonics are eliminated, see figure 6-1. When the difference between the two signals is derived, the second-order harmonic is zero. This is true for all even-order har-monics.

FIGURE 6-1. MATHEMATICAL DESCRIPTION FOR ELIMINATION OF EVEN-ORDER HARMONICS.

Differential signalling also eliminates loss caused by differential-to-single-ended converters, such as the hybrid junction used in the measurements, and improves the common-mode noise rejection.

6.1.2 Double Scanning

Since harmonics and spurious signals responds different to power changes than the fundamental signal does, see section 2.1.3, it is pos-sible to further reduce harmonic distortion by utilizing double scan-ning.

221 xx αα +

( ) ( )221 xx −+− αα

( ) ( )( ) xxxxx 12

112

21 2ααααα =−+−−+-

+

Section 6.1: Future Work56


Double scanning is performed by doing two different data acquisi-tions. One of these two measurements is performed by attenuating the input signal a certain amount before entering the non-linear device.

In the RF undersampling receiver, this means that the ADC output is analyzed both for an unattenuated T/H input signal and for an attenuated T/H input signal. It is now possible to digitally differenti-ate and remove the harmonics and spuriouses from the desired sig-nal since the power changes of the harmonics and the spuriouses are different from the desired signal.

Assume the spectrum shown in figure 6-2 is the ADC output spec-trum for the desired band for an unattenuated input T/H signal.

FIGURE 6-2. FIRST SCAN (UNATTENUATED INPUT SIGNAL).

Next, assume that the T/H input is attenuated by 6 dB. Then the fun-damental signal would be attenuated by 6 dB, whereas the harmo-nics, in this example the second-order harmonics, would become 12

Fundamental

Signal

Second-Order Harmonics

4 dBm

-40 dBm

Desired Band

Chapter 6: Conclusions 57


dB weaker, see figure 6-3. In this case, all spectral bins that decrease more than 6 dB are undesired and can be removed.

FIGURE 6-3. SECOND SCAN (ATTENUATED INPUT SIGNAL).

To enable double scanning, special signal processing algorithms must be used. One of the future tasks to improve the RF undersamp-ling receiver is to develop these algorithms.

6.1.3 Variable Sample Frequencies

One of the possible solutions to harmonics aliasing was to change the T/H or ADC clock frequency. However, changing the clock fre-quency to prevent harmonics aliasing for a specific band may imply that another band can no longer be supported. Therefore, to support of all desired bands and at the same time eliminate harmonics alia-sing, it would be advantageous to be able to select the current sample frequency depending on which band is active.

Second-Order Harmonics

-2 dBm

Desired Band

-52 dBm

Section 6.1: Future Work58


7 References

[1] M. Patel, P. Lane, “Comparison of Downconversion Techniques for Software Radio”, Department of Electronics and Electrical Enginee-ring, University College London.

[2] D. Jakonis, J. Dabrowski, C. Svensson, “Noise Reduction by Sampling Frequency Choice in Subsampling Mixer”, Department of Electrical Engineering, Linköping University.

[3] R. G. Vaughan, N. L. Scott, D. R. White, “The theory of bandpass sampling”, IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 1973-1984, Sep 1991.

[4] M. Loy, “Understanding and Enhancing Sensitivity in Receivers for Wireless Applications”, Texas Instruments, Technical Brief SWRA030.

[5] M. C. Lawton, “Sensitivity Analysis Of Radio Architectures Employing Sampl And Hold Techniques”, Hewlett Packard Laborato-ries.

[6] B. Brannon, C. Cloninger, “Redefining the Role of ADCs in Wire-less”, Analog Devices, Inc.

[7] D. F. Dubbert, T. L. Hardin, G. G. Delaplain, “Characterization of a Track-and-hold Amplifier for Application to a High Performance SAR“, Sandia National Laboratories, July 2002.

7.1 Recommended LiteratureThe following sources of information are recommended as a comple-ment to this report:

• D. M. Akos, M. Stockmaster, J. B. Y. Tsui, J. Cashera, “Direct Bandpass Sampling of Multiple Distinct RF Signals”,IEEE Transactions on Communications, vol. 47, no. 7, pp. 983-988, July 1999.

• K. McClaning, T. Vito, “Radio Receiver Design”, Noble Publis-hing; Feb 2001.

• Ching-Hsiang Tseng, Sun-Chung Chou, “Direct downconver-sion of multiple RF signals using bandpass sampling”, IEEE

59


International Conference on Communications, vol. 3, pp. 2003-2007, May 2003

• B. Brannon, Basics of Designing a Digital Radio Receiver (Radio 101), Analog Devices, Inc.

• P. Pérez, A. Santos. J. J. Vaquerob, “Potential use of the under-sampling technique in the acquisition of nuclear magnetic reso-nance signals”, E.T.S.I. Telecomunicacio´n, Ciudad Uni_ersitaria, Uni_ersidad Polite´cnica de Madrid, May 2001.

• T. Vasseaux, B. Huyart, P. Loumecu, “A track&hold-AGC suita-ble for downconversion by subsampling”, The 6th IEEE Interna-tional Conference on Electronics, Circuits and Systems, vol. 3, pp. 1527-1530, Sep 1999.

60


Index

Numerics

1/f noise, 17

A

Aliasing distortion, 21

C

Clock Noise, 31

Clocks Phase Difference, 35, 49

Conclusions, 55

D

DC offset, 14, 17

Differential Signalling, 56

digitizing block, 20

Double Scanning, 56

Down-Conversion, 42

Down-Conversion By Undersampling, 22

H

Half-IF Response, 15

Harmonic Distortion, 8, 46

Harmonics Aliasing, 32

Changing Sample Frequencies, 34Low-Pass Filtering, 34

I

Image Response, 14

IMD rejection ratio, 10

L

LO Leakage, 14

LO Spurious Responses, 15

M

Measurement Results, 37

Measurements Setup, 37

T/H Measurements Setup, 39The T/H Circuit, 37

minimum-detectable signal, 7

N

Noise Figure, 6, 46

Noise Folding, 25, 43

Front-End Gain, 28Sample Frequency Considerations, 27SNR Degradation, 26

Nyquist sample rate, 21

S

Selectivity, 16Sensitivity, 7

SNR degradation, 45

Spectrum Response, 50

With Intermediate Filtering, 51

Spurious Free Dynamic Range, 12

T

T/H and ADC clocking, 41

T/H Measurement Results, 42

The Direct-Conversion Architecture, 17

The Mixer, 11

The RF Undersampling Architecture, 19

Advantages, 23

The Superheterodyne Architecture, 16

61


Third-Order Intercept Point, 11

Two-Tone Intermodulation Distortion, 9, 48

U

Undersampling, 19

V

Variable Sample Frequencies, 58

62

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