by George Marsh

An evolution that started with thermionic valve-

based mainframe computers and can now put

multiples of their processing power into a modern

lap-top is today proceeding towards ambient

intelligence, in which ever more compact processing

will be all around us and, quite literally, part of the

furniture. Convergence of information and

communications technology (ICT), today exemplified

by the conjunction of GSM (global system for

mobile) telephony with ‘palm’ PC power, will go

much further as microscopic electronics become

nanoscopic. Ultimately we will have the power to

merge biological and inanimate intelligence to create

extended neuro-electronic systems.

Visionary stuff, but although the day of the cyborg

may still be some way off, IMEC (Inter-University

MicroElectronics Centre) – Europe’s leading

independent microelectronics research organization –

sees its role as expediting some aspects of this future.

This means, inter alia, a dedication to maintaining the

currency of Moore’s Law, in the belief that this can

continue for several years yet before fundamental

limits impose insurmountable barriers. Success will

require further extension of the boundaries of

complementary metal oxide silicon (CMOS), that

backbone of mainstream electronic technology.

Materials, both the manipulation of existing and

development of new, are germane to this, as

Materials Today discovered on a recent visit.

Belgian, European, and globalUnlike some other research entities that are regionally

spread, IMEC is concentrated in one location, the Belgian

university town of Leuven. There are also small satellites in

San José, California, and Shanghai, China. Over 1200 people

working at IMEC – some 350 of these are ‘industrial

residents’, PhD researchers, and others not actually on the

payroll – are supported by an annual budget of around 120

million, some 70% of which is self-generated through

contract research. Half of this research emanates from

Europe, IMEC’s aims and programs coinciding well with those,

for example, of the European Community’s Sixth Framework.

The rest involves contract partners in North America, Asia-

Pacific, and increasingly other regions.

June 200240

IMEC pushesthe limits of CMOS

ISSN:1369 7021 © Elsevier Science Ltd 2002

INSIGHT FEATURE

June 2002 41

This international focus, in line with the global nature of

the semiconductor industry, runs alongside an institutional

aim to bring more ICT activity to Belgium itself through spin-

offs, training, and inward investment. According to Jan

Wauters from IMEC’s business development department, the

organization is working with about 70 Flemish companies and

creates, on average, one spin-off per year. A major IMEC

strength over contract research houses that are affiliated to

particular manufacturers is, according to Wauters, its

independence. This, and the great care it takes with

intellectual property, enables IMEC to work with

organizations that compete directly with each other. IMEC is

also careful to ring-fence the intellectual property it develops

through its own, strictly internal R&D activities.

Although facilities started in 1984 with a handful of

portable cabins, they now comprise three major resource

blocks (IMEC 1, 2, and 3) on the campus of Leuven’s

Katholieke Universiteit, along with a separate large clean area

(over a third of which is Class 1) and pilot line for 200 mm

wafers (Fig. 1). This fourth building was recently extended to

4800 m2. Inside may be seen a full set of front end of line

(FEOL) and back end of line (BEOL) process equipment from a

range of suppliers; the usual cassettes of wafers in various

stages of process and analysis; rare 193 and 157 nm litho

gear including a recently commissioned Ultratech ministepper

with a 0.75 numerical aperture, 4 x 4 mm field size, 35 nm

overlay capability, and 6:1 reduction ratio; an atomic layer

deposition platform; and an exotic array of spectroscopic,

microscopic (including atomic force microscopy), and

metrology tools for material characterization (Fig. 2). Most of

the fabrication area is devoted to silicon (Si) and compound

process applications, though some space is set aside for basic

research.

Roadblocks for CMOSPotential show stoppers for CMOS include material-related

issues like ultrathin gate oxides and high dielectric constant

(k) replacements for silicon oxide (SiO2) at the front end of

line, and interconnect technology at the back end of line.

Fig. 1 This 193 nm step-and-scan system is part of IMEC’s advanced processing capability.

Fig. 2 A scanning spreading resistance microscope is among characterization tools.

INSIGHT FEATURE

June 200242

Overall scale is a function of the lithography used to

‘draw’ ever finer lines on Si integrated circuits (ICs). A

continued major focus is to extend lithography based on the

193 nm wavelength of excimer argon fluoride lasers right to

its limits of 90-75 nm patterning (Fig. 3). (This compares with

the 248 nm wavelength provided by current industry-

standard krypton fluoride lasers, which lenses and other

optical means can push to line widths of 130 nm.) Work with

over 25 international partners within the 193 nm optical

lithography consortium makes this IMEC’s largest

collaborative program. Aggressive optical extension to

fluorine excimer laser-based 157 nm lithography is, however,

well advanced as the next step and involves a research team

of some 45-50 people, including 10-15 from affiliate

companies. (Such collaboration takes place within IMEC

industrial affiliation programs, IIAPs.)

AlS i,SiO2

Po ly-S iS i3N4

TiS i 2

CoS i2TaSi2NiS iWSi2

WTiN

Cu

Low-k d ie lec trics

PZT, SBT

Metal ga tes

High-k d ie lec trics

?

1970 1980 1990 2000 2010

Ma

teri

als

Source : INFINEON

Number of materia ls booming

Fig. 4 Implementation of sub-micron scale devices – anticipated timing.

Fig. 3 A major current focus is pushing 193 nm lithography to its limits. Lithography basedon the 193 nm laser wavelength can, with lenses and other optical elements, deliver 100 nm linewidths, as used in producing this silicon wafer.

(a)

(b) (c)

INSIGHT FEATURE

June 2002 43

Utilizing the fruits of lithography goes hand in hand with

improving its state-of-the-art. As progress into deep sub-

micron CMOS continues at IMEC, work to integrate initial

0.13 µm devices, developed over the last two years, should

be complete this year, while 100 nm devices are already

being optimized ready for process integration in 2003.

Development of 65 nm devices has just begun and will

continue through 2004, while 45 nm will follow (Fig. 4).

Precision material modification is vital to maintaining or

improving CMOS performance at these scales. As Gonçal

Badenes responsible for CMOS process and device integration

activities points out, manipulation of doping – always key to

semiconductor performance – becomes even more critical if

the myriads of transistor switches that make up logic devices

are to operate with low power consumption in the presence

of high drive currents. “As dimensions become really short,

there can be a leakage of current when the transistor is

switched off,” Badenes explains. “This is clearly bad for power

consumption overall. By tailoring the proportions of

implanted dopants such as phosphorus and arsenic carefully,

we can minimize these short-channel effects.” Likewise,

appropriate doping can minimize power dissipation for a

given time delay. “It’s the final optimizing touches that are so

crucial for successful industrialization,” says Badenes, who

adds that recent results with an IMEC-developed 100 nm

transistor with a 75 nm gate length were among the best in

the industry, comparing well with those achieved by Intel.

A 100 nm device requires a gate oxide as thin as 2 nm, at

which thickness leakage takes place through direct tunneling

of charge carriers between the gate and channel regions.

Judicious material treatment and optimization can inhibit this

tendency. For example, nitrogen enrichment of the SiO2 has

proved beneficial, with remote plasma nitridation (RPN)

providing two orders of magnitude reduction in leakage and

suppressing penetration of the B dopant. Oxynitrides,

achieved via a thermal oxidizing step before nitriding, are a

less promising – albeit simple – avenue. Badenes believes that

scaling can be taken down to 1.04-1.2 nm for high-

performance CMOS, and 1.5-2 nm for low power and

memory applications. He cautions, however, that ultimate

practical constraints could be more a question of the

reliability of the ultra-thin oxide layer than of gate leakage.

It is this reliability issue that has prompted a race among

the world’s semiconductor manufacturers to find an eventual

successor to SiO2 that will remain viable at very low

dimensions. As IMEC president and chief executive officer

Gilbert Declerck says, “The semiconductor industry has been

built on silicon oxide. We now face a point where the heart

of the MOS transistor may have to be replaced.”

Alternative candidate materials for the gate region include

metal oxides such as Al, Zr, Hf, Ti, and Cr. Some of these

metal oxides pose challenges of incompatibility with Si,

which will remain the substrate material of choice for some

time. An IMEC-led consortium is currently half-way through a

three-year research program to develop solutions suitable for

devices down to 70 nm or less. Participation of industry

heavyweights Hitachi, Motorola, Texas Instruments, and

Philips, who have elected to work collaboratively rather than

keep these issues to themselves in their own laboratories,

amounts to an impressive endorsement of IMEC’s reputation.

The consortium also includes other leading names such as

Spinning out

A mission to carry out strategic research three to ten

years ahead of industrial exploitation is matched by a

commitment to transferring the products of research

effectively into industry, an aim promoted by the

collaboration of over 450 outside partners and by the

ever growing list of spin-off companies – 19 at a recent

count.

A dozen of these have been set up over the last five

years including Sirius Communications, a satellite

communication specialist; Target Compiler Technologies,

which produces code for designing and programming

digital signal processors; CoWare, which offers

combined hardware and software solutions; Acunia,

involved in the development of telematics platforms;

AnSem, a specialist in analog design services;

Oligosense, which utilizes electrically conductive

oligomers in electronic noses; 3E, specializing in

sustainable energies; FillFactory, aiming to commercialize

CMOS image sensors; Q-Star Test, with a current

monitor product line; Septentrio, developing satellite

navigation systems; and XeniCs, specializing in innovative

infrared image sensors. The latest addition, recently

announced, is Photovoltech, formed with energy

companies Electrabel, TotalFinaElf, and Soltech to

produce components for photovoltaic systems.

INSIGHT FEATURE

June 200244

Advanced Micro Devices, Conexant, Hewlett-Packard,

Hyundai, Infineon Technologies, International Sematech, and

STMicroelectronics.

Major semiconductor houses plan to launch, in line with

the International Technology Roadmap for Semiconductors,

high-end large-scale integration (LSI) products featuring new

high- and low-k materials. Hitachi, for instance, intends to

take the wraps off its 0.1 µm process technology embodying

1 nm effective oxide thickness (EOT) by next year and move

to the 0.07 µm rule using 0.5 nm EOT two years later.

Emerging RFSub-micron devices of 100 nm or less are candidates for radio

frequency (RF) applications and a new RF-CMOS program

aims to push the technology well into the microwave regime

(5-25 GHz) and then up to 50 GHz. Indeed, early IMEC test

results cited by Badenes suggest that eventually transistors

will be produced that achieve maximum operating

frequencies of up to180 GHz. Under a three-year program

that commenced last September, collaborative teams are

already re-modeling architectures and processes first

developed for digital technology, to meet 5-6 GHz

requirements. Meanwhile circuit designers seek to incorporate

these, integrated with appropriate passive devices and back-

end interconnects, into chips. Outside collaborators on this

project include Ericsson, who is contributing microwave

design expertise, together with Philips and Chalmers

University on the design and modeling side. Badenes expects

100 nm RF-CMOS to hit the market just a year or two after

advanced CMOS is applied to mainstream digital technology.

Success at this level will bode well for the future of RF-

CMOS, but IMEC is not ignoring the potential alternatives,

such as bipolar CMOS and compound III-V semiconductors

like GaAs. It is, for example, supporting Alcatel in its

development of 0.35 µm SiGe BiCMOS technology suitable

for prototyping and volume production of RF devices running

at up to 10 GHz.

Nano-scaleThe question of a SiO2 replacement looms larger as

downscaling takes electronics further into the nanometric

region. Marc Van Rossum, a professor at the Katholieke

Universiteit and advisor to the IMEC strategic development

unit would personally put his money on nanotubes to replace

the Si channel. Although, as Van Rossum admits, a reliable

Non-CMOS materials

IMEC activities extend well outside CMOS and embrace a

range of non-Si and hybrid electronics from III-Vs to

polymers, taking in ferromagnetics and heterojunctions

on the way. As random examples:

• In optoelectronics IMEC has developed gallium

arsenide-based LEDs with efficiencies of 40%,

corresponding to 1 mW of light emitted per 1.75 mA of

current passing through the diode. It has also

collaborated in the development of tunable laser diodes

for wavelength division multiplexed (WDM) systems.

• In the burgeoning field of magnetoelectronics it has

developed working devices based on combinations of

magnetic and semiconductor structures. As an

alternative to thin film techniques, researchers have

fabricated magnetic semiconductors using molecular

beam epitaxy to deposit semiconductor and magnetic

materials. Introducing magnetism into the semiconductor

layer yields magneto-transport and -optic effects that

hold promise for future devices. Ultra high vacuum

technology has been used to grow III-V semiconductors

that incorporate magnetic impurities such as MnGaAs.

On a shorter timescale, tunnel junction magnetic random

access memory (TJMRAM) could be used in plastic

smart cards, which require a combination of processor

capability with non-volatile high-density magnetic memory.

Bringing their own ‘spin’ to semiconductor R&D, IMEC

researchers have used electrodeposition to produce thin-

film spin valve structures comprising a noble metal, such

as Au, sandwiched between weak and strong magnetic

layers. Vertical spin transistors have been fabricated by

wafer bonding a spin valve base between a GaAs emitter

and a Si collector (Fig. 6).

• Biological and molecular materials offer exciting

possibilities for creating novel electronic components.

Si-rooted concepts have already been mentioned, but

non-Si possibilities are also being investigated.

• Most obviously divorced from CMOS is the emerging

field of plastic electronics. Here IMEC is working towards

producing electronics on flexible sheet substrates that

can be manufactured roll to roll for packaging, medical,

INSIGHT FEATURE

process for synthesizing pure nanotubes does not yet exist,

nanotube transistors were first demonstrated several years

ago by groups from Delft University of Technology and IBM

Research, the latter going on to construct an inverter. (IBM’s

continuing investigation of nanotube potential should not,

however, be taken as an infallible sign that this technology

will triumph, since the company has also in the past ramped

up its efforts on III-V and other technologies, only to move

away from them later.)

Before any nanotube future, CMOS has a long way to go,

believes Van Rossum, with its capabilities reaching down to

at least the 35 nm scale. Describing this well-established and

backed technology core as the ‘steel’ of electronics, he says

that it will support new MOS-based structures including

ballistic MOS, vertical MOS, and SiGe heterojunctions. Van

Rossum points out that early work in nanoelectronics, before

that term had even become established, was mainly III-V

based (quantum wells were, for instance, easier to realize in

GaAs), but that many early III-V concepts have since been

replicated successfully in Si. CMOS will, he claims, continue

to serve as a unifying trunk when different technologies and

architectures are combined together on a single chip, though

he admits that once integration with C-based structures,

including biochemical, is attempted, the semiconductor

community may have to think again. Then, he suggests,

biological, physical, and engineering disciplines will come

together with nanotechnology as their common force

multiplier.

At that stage, materials will benefit from manipulation and

self-organization at molecular and atomic scales. A foretaste

of things to come is offered by recent IMEC research on self-

assembled monolayers (SAMs) to increase the performance of

biosensors. It has proved possible to modify the surfaces of

metals like Pt, Pd, Cu, and Au using thiols R-(CH2)n-SH.

Surfaces can be made hydrophilic or hydrophobic, or

expanded with desired functional groups, using a thiol layer a

few nanometers thick. By employing mixed SAMs, surfaces

can be tuned for the desired application – biological

recognition or selective immobilization of biomolecules, for

example. Of more direct relevance to CMOS, the nanoscale

‘bottom-up’ approach could conceivably deliver the ultimate

Si successor.

Convergence of ‘top down’ and ‘bottom up’ approaches

will yield highly integrated chips, where computing is only

part of the total functionality. These systems-in-a-package

June 2002 45

Fig. 5 UTCS (ultra-thin chip stacking) silicon wafer.

fabric, and other applications. Realizing inexpensive

organic thin-film transistors and LEDs is a step in this

direction. Organic solar cells created using bulk donor-

acceptor heterojunction concepts may show conversion

efficiencies of only ~3%, but their wrap-round applicability,

low cost, and disposability could have compensating

appeal. IMEC has also demonstrated an ability to lift

thin-film monocrystalline Si solar cells from Si growth

substrate and transfer them to a cheap substrate such

as Al203. This is achieved using a spinable oxide that

both binds the substrate and semiconductor layers and

accommodates the difference in coefficient of thermal

expansion between the two. An energy conversion

efficiency of 12% for an active layer thickness of only

10 µm indicates the potential of this approach.

will not only handle voltages, but will also deal with photons,

motions, magnetic fields, and, as in the biosensor example

above, molecular recognition. Nanoelectronics to support

these developments can for some time continue to be based

on advanced MOS, fabricated using a combination of evolved

top-down patterning with, increasingly, nanostructured

epitaxial growth of Si, Ge, and C materials. Ultimate CMOS

will combine such devices as nano field-effect transistors

(IMEC was engaged, with the University of Cambridge, in a

project to produce nanoFETs over a decade ago), gate all-

round transistors utilizing new gate oxides and polycrystalline

Si, and epitaxially-produced SiGe transistors. Devices like the

SiGe barrier vertical transistor, the SiGeC heterojunction

bipolar transistor, and the quantum MOSFET may also come

into their own, as well as various new forms of memory such

as single-electron nanocrystal-based nanoFlash.

Even patterning down to 10 nm resolution can, believes

Van Rossum, be supported using optical lithography

principles once a move is made to shorter wavelengths of

around 13 nm. Extreme ultra violet integration (EUVI) should,

he told Materials Today, become possible by 2005 and be up

and running by the end of the decade. Dielectrics for deep

nanoscale devices may progress through mesoporous

materials that contain air, to air itself (k = 1 rather than the

dielectric constant of 3 or 4 typical of present materials) if

the challenges of air-bridge technology can be met. At the

back end of line, interconnects will rely on thin-film Cu lines

(now well established in working processors such as Intel’s

Pentium 4) to replace Al technology, and the three-

dimensional stacking of ultra-thin multi-chip modules to

achieve short, high-density interconnect routes (Fig. 5).

Much of the work mentioned – ultimate oxynitrides,

high-k metal gate stack materials, ultra-shallow junctions and

contact schemes, advanced substrate/channel engineering,

and implementation of 40-25 nm devices – is encompassed

by IMEC’s internal Advanced Device Implementation Program

(ADIP). IIAP collaborations will contribute advanced

lithography and high-k dielectrics, plus salicides and shallow

junctions. Looking further ahead, an Emerging Alternative

Devices (EMERALD) program should ensure that when

classical CMOS does eventually run out of steam, probably at

around 30-35 nm gate lengths, alternatives will be ready.

Candidates include fully depleted silicon-on-insulator (SOI),

strained Si/SiGe as a basis for high mobility CMOS, and

SiGe/Si heterojunctions for the source side of vertical devices.

These Si-based materials will be complemented by new

ferroelectric materials for scaled capacitors, BiCMOS

combinations, and evolved magnetic materials for scaled

Flash memory.

INSIGHT FEATURE

June 200246

Fig. 6 Optical test of the injection of spin-polarized current through the magnetic tunnelcontact of an LED, cooled with liquid nitrogen.

Fig. 7 Progress towards polymer electronics has yielded this organic solar cell on a flexiblesubstrate.

INSIGHT FEATURE

Another future possibility is the polymer semiconductor,

one variant of which is a polymer-based ChemFET sensor

(Fig. 7). Here a Si layer supports a SiNx-based dielectric

sensing area on a P3HT (poly{3-hexylthiophene}) organic

semiconductor. The polymer, replacing the conventional MOS

gate, acts as a charge scavenger which, by capturing ions,

influences the flow of current.

Looking even further ahead, IMEC is involved in research

aimed at bringing biology and nanoelectronics together in

advanced bio-electronic systems (Fig. 4c). A biosensor, for

example, would have a semiconductor transducer connected,

via a linking layer, to biological probes that would target

particular biochemicals. A complete neuro-electric synapse

would be based on a ‘floating gate FET’ and incorporate a

molecular transducer to enhance capacitive coupling, a layer

to anchor neurons and guide their growth, and a capping

layer to mitigate ion leakage and shunting. Challenges include

persuading molecules to self-assemble organically onto

substrates such as gold-on-silicon and then become

immobilized, and achieving biocompatibility, especially with

proteins (DNA being less of a challenge).

In a world in which micro- and nano-scale integration will

bring gigascale complexity (in the 30 nm range chips will

contain two billion logic transistors, equivalent to 1000

programmable processors and 50 Mb of storage) IMEC sees a

continuing role for Si in general and CMOS in particular, but

will be ready with alternatives when future ambient

consciousness-augmenting bioelectronic technologies

demand them. MT

FOR FURTHER INFORMATION

Contact: IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

Phone:: +32 16 28 12 11

Fax: +32 16 22 94 00

http://www.imec.be

June 2002 47