WP1 Management, Dissemination and Exploitation leader: L. Selmi, IUNET WP2 Physics based models and verification leader: A. Schenk, ETHZ WP3 Characterization leader: L. Czornomaz, IBM WP4 TCAD models and verification leader: F. Bufler, Synopsys WP5 Device level performance investigation leader: D. Esseni, IUNET WP6 Application by end users leader: T. Herrmann, GLOBALFOUNDRIES

Importance and success of the III-V-MOS integrated

modeling approach

Importance and success of the III-V-MOS integrated

modeling approach

Interview of Luca Selmi, III-V-MOS Coordinator, Univ. of Udine, IUNET

As III-V-MOS coordinator, could you explain us why models and

methodologies are so important in this domain?

The integration of III-V compound semiconductors on silicon platforms is foreseen

as the next major evolution of advanced CMOS technology nodes. The introduction

of such a disruptive innovation is a long term process where accurate Technology

Computer Aided Design (TCAD) is indispensable to reduce cost and to explore in a

timely manner the available engineering options.

The problem is that TCAD cannot provide yet quantitatively accurate predictions for III-V n-MOSFETs,

essentially because what used to be bulk material properties become device and bias dependent

quantities in nanoscale transistors. In addition, available modeling approaches beyond commercial TCAD

do not meet the industry demand for comprehensive and efficient models.

This is why III-V-MOS deploys a coordinated effort among the top european experts of nanoscale device

modeling methodologies, backed-up by advanced device fabrication data, to take advantage of the best

that each method can offer, and in order to develop calibrated TCAD descriptions for a large variety of

device options and configurations.

How can you be sure that the integrated modeling approach is the right way to go ?

III-V-MOS hierarchical, integrated modeling approach (see Figure) is of

paramount importance for the project, since it is instrumental to transfer the

details of thin-film and interface physics into TCAD models that describe the

complex interplay between material parameters, composition, strain and device

dimensions in modern technologies. In III-V-MOS we guarantee the consistency

among all modeling levels by comparing systematically simulations of the same

“template” devices obtained with different modeling approaches (see, e.g., [1]).

This is a well-defined methodology, successfully developed on a smaller scale in

past collaborative initiatives. In III-V-MOS we embraced and extended this

approach by including more models (from atomistic to TCAD) and by feeding the

simulation activity with real experimental data from advanced devices and test

structures. [1] E.Caruso et al., “Modeling approaches for band-structure calculation in III-V FET

quantum wells”, Proc. 1st Joint EUROSOI-ULIS Conference, p. 101 2015.

III-V-MOS www.iii-v-mos-project.eu

contact@iii-v-mos-project.eu

News from the European Technology

CAD for III-V Semiconductor-based

MOSFETs Research team at month 15

October 2014

Objective 1 > ”High-level” simulators for III-V

compound semiconductor n-MOSFETs at and beyond the

14 nm node

ETHZ & IUNET & QuantumWise: band-structure calculations for

ultra-thin relaxed and strained InGaAs layersAn accurate description of the band structure in III-V compound semiconductor films is perhaps the

most important ingredient for accurate modeling of nanoscale devices. The Density Functional Theory,

Tight Binding (TB), K●P and non–parabolic Effective Mass Approximation (NP-EMA) represent

complementary methods for band structure calculations. No single method can be preferred a-priori,

each having its own advantages and limitations. In III-V-MOS, band structure calculations for ultra-thin

InGaAs layers (5nm film shown in Figure1) have been

developed and mutually compared. The discrepancies and

relative errors provide direct indications on each model’s

validity limits. III-V-MOS is actively pursuing this methodology,

with the goal of developing a database of theoretically and

experimentally calibrated parameter values for the III-V

compound semiconductors of current interest for industry.

In the future, the models will be extended to the carrier

transport and the extrinsic contact resistance, thus eventually

gaining a complete description of full devices with complex

geometry suited to assist performance evaluation.

Synopsys: First version of Monte Carlo model for InGaAs

Since a few years, Monte Carlo (MC) transport models have officially become an integral part of TCAD

for semiconductor devices. Previously, widespread acceptance of MC simulation in industry was

hampered by the large simulation times and the unclear advantages compared to the faster drift-

diffusion model. The far-from-equilibrium transport regime of modern nanoscale MOSFETs, and MC

simulation wall clock times falling below 10 min for ID,SAT on 16 core machines [2] per bias point have

changed this situation. That is why III-V-MOS considers Monte Carlo simulation methods as an integral

part of TCAD. In III-V-MOS, Synopsys has developed a first version of the MC module for In(1-x)GaxAs

alloy devices.

The main ingredients of MC simulation are the band structure and the collision rates for all relevant

scattering mechanisms. For the band structure, either analytical approximations, or numerical tables

computed with the nonlocal empirical pseudopotential method can be used. The tables for InGaAs and

the side-materials GaAs and InAs are calibrated on experimental splittings between symmetry points in

the Brillouin zone.

Scattering mechanisms always include intravalley and intervalley phonons. As of today, the processes

and coupling constants published in [3] for GaAs have been implemented, but more work is expected

on this topic once new time-of-flight measurements will become available in III-V-MOS. Since the same

coupling constants are usually taken for InAs and GaAs, we also use the values of GaAs for InAs and

only change material parameters such as the velocity of sound and the mass density. Similarly, the

impurity scattering rate is only affected by the different value for the static permittivity. In the alloy

InGaAs, the phonon scattering rates of both side-materials are weighted by the corresponding mole

fraction. Finally, alloy scattering is taken into account and the alloy potential is treated as adjustable

parameter.

A major addition has been the consideration of polar-optical phonon scattering which is absent in non-

polar semiconductors like Si, Ge and SiGe alloys. The exact (anisotropic) scattering rate is used and the

after-scattering state is selected according to the transition probability per unit time with the stochastic

acceptance-rejection scheme. For the computation of this scattering rate a simple analytic non-

parabolic band structure is used. All other Monte Carlo steps are performed with the pseudopotential

band structure. Surface roughness scattering is treated as a combination of specular and diffusive

scattering (together with a quantum correction based on effective oxide permittivity and work functions

from a previous quantum simulation [4]. The ratio of diffusive surface scattering is an empirical

parameter which is to be adjusted to experimental long-channel effective mobility curves

[2] F.M. Bufler et al., “Efficient 3D Monte Carlo simulation of Orientation and Stress Effects in FinFETs”, Proc.

SISPAD, Glasgow (UK), Sept.2013; pp. 172.

[3] M. Lundstrom, “Fundamentals of carrier transport,” Cambridge University, Press, 2000.

[4] F.M. Bufler and L.Smith, “3D Monte Carlo simulation of FinFET and FDSOI devices with accurate quantum”, J.

Comput.Electron.12, 651 (2013).

Figure 1

PLANAR

InP/

InGaAs FinFET

: VERTICAL: Nanowire

PLANAR: Wafer bonding

Objective 2 > Major evolution of advanced CMOS

technology nodes

IBM & IMEC: State-of-the-art III-V processing facilities supporting

dedicated test structures and experiments for advanced modeling

High mobility channel materials such as InGaAs and SiGe

are expected to provide a higher performance at a lower

power thanks to the higher injection velocity of electrons

and holes in inversion layers. While SiGe channel p-MOS is

close to be a mature technology, InGaAs-based n-MOS

transistors still present

numerous challenges and

demand large investments.

It is therefore of utmost

importance for the industry to have access to accurate models to predict

the future performance and economical viability of production-type

InGaAs n-type transistors before they even exist. For that reason, the

two leading III-V industrial research centers (IMEC and IBM) engaged

into the III-V-MOS project in order to provide state-of-the-art III-V

fabrication processes and devices with planar, fin or wire architecture as

a flexible source of diverse and complementary data that can feed the

development of accurate InGaAs transport models.

This collaboration goes well beyond a simple comparison of

models with data acquired on standard InGaAs n-type transistors.

The concept is to leverage the processing capabilities of the

technology partners and the modeling expertise of simulation

partners, in order to design, fabricate, characterize and model

dedicated test structures that will separately address the most

important issues in InGaAs modeling. In the first year, dedicated

experiments were performed in order to

extract the bandgap dependence on the

channel thickness of InGaAs-on-insulator

substrates for very thin layers (down to

4nm) where carrier confinement plays a

major role. MOS capacitors with different

surface preparation were fabricated, characterized and modeled. Those results

will be compared with atomistic simulations to provide insights on the nature of

interface traps. In addition, dedicated N+/n/N+ test structures were designed

and characterized with the aim to extract ideal transport properties of InGaAs

n-type transistors in absence of process-induced defects.

Next year, specific characterization techniques like time-of-flight

measurements will be applied onto dedicated test structures to measure the

fundamental electron drift/diffusion properties as a function of electric field for

a range of electric fields that were never explored in the past and that

corresponds to the operating region of an InGaAs n-type transistor.

Objective 3 > Transfer of models into commercial

simulators.

A keynote of the III-V-MOS project is the commitment to transfer models into commercial TCAD and

simulation software, and to deliver simulation setups for InGaAs MOSFETs to the industrial partners.

Early achievements in this direction are the release of the Monte Carlo model for InGaAs (Synopsys),

and the QuantumWise ATK-2014 Density Functional Theory simulation software described below.

Quantumwise: new release of atomistic simulation software

QuantumWise, project partner responsible of atomistic density functional theory band structure

calculations, has in October 2014 released a new version of its simulation software, ATK-2014, with

special focus on the atomic-scale modelling of semiconductor devices and materials. ATK calculates the

band structure of bulk (three dimensional) and confined (one- or two-dimensional) systems. For the

latter, it is possible to use fractionally charged hydrogen atoms for passivating surface dangling bonds

avoiding the introduction of spurious surface states [5].

The new release ATK-2014 includes modules for

accurate ab-initio DFT simulations of the electronic

structure of III-V materials developed through

QuantumWise’s participation in the III-V- MOS

project. To obtain accurate band structures the

release includes new MetaGGA Density functionals

[6] which can be used together with relativistic

pseudo potentials that include spin-orbit couplings.

The ab-initio calculations have been validated with

experimental data and semi-empirical models

available from the other project partners. A notable

example is given in the Figure which shows the

atomistic local density of states at an InP/InGaAs

heterojunction. In the spirit of the integrated

modeling approach pursued by III-V-MOS, the

electronic structure can be exported and used with

the Sentaurus Device simulator from Synopsys.

The new band-structure calculations methods can also be used for device simulation using the Non

Equilibrium Green’s Function (NEGF) transport model functionality implemented in ATK, or to describe

the band offset at an interface, as illustrated below. The new release includes tutorials with step-by-

step guides on how to apply the new functionality for III-V material systems.

[5] J. Li et al., Physical Review B, vol. 72, 125325 (2005)

[6] F. Tran et al., “Accurate Band Gaps of Semiconductors and Insulators with a Semilocal Exchange-Correlation

Potential,” PhysIcal Review Letters, 102, p. 226401, 2009.

Synopsys: first version of simulation setups released to

GLOBALFOUNDRIES, IBM and IMEC

The Synopsys Monte Carlo device simulator has been extended for the simulation of n-type III-V

materials. Experimental velocity-field characteristics of bulk GaAs and InGaAs could be reproduced with

good accuracy and more calibrations and tests are foreseen for thin layer InGaAs in the next months by

the III-V-MOS work-programme. These new simulation capabilities are now

included in the Synopsys release J-2014.09. In addition, complete

simulation setups for simulation of realistic 3D planar SOI and FinFET

technologies have been generated and transferred to GLOBALFOUNDRIES,

IBM and IMEC for evaluation.

Future TCAD model improvements may address the inclusion of source-to-

drain tunneling, a physical effect which can deteriorate the subthreshold

swing of MOS transistors at the ultimate technology nodes. Fine-tuning of

model parameters on new experimental data will be pursued to further

increase the dependability of the code.

Prepared by Pascale Caulier (SINANO Institute), Dissemination Manager of III-V-MOS