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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012 1579

Single-Stage, Universal-Input AC/DC LED DriverWith Current-Controlled Variable PFC

Boost InductorYuequan Hu, Laszlo Huber, Member, IEEE, and Milan M. Jovanovic, Fellow, IEEE

Abstract—This paper presents a single-stage flyback power-factor-correction (PFC) circuit with a variable boost inductancefor high-brightness LED applications for the universal input volt-age (90–270 Vrm s ). The proposed circuit overcomes the limitationsof the conventional single-stage PFC flyback with a constant boostinductance that cannot be designed to achieve a practical max-imum bulk-capacitor voltage level (i.e., less than 450 V) at highline while meeting required line-current harmonic specificationsat low line. According to the proposed method for achieving vari-able boost inductance, the boost inductance has a constant highvalue at high line, while at low line it is reduced proportionallyto the load current, so that the IEC 61000-3-2 class C and corre-sponding Japanese JIS C 61000-3-2 class C line-current harmoniclimits are satisfied. The proposed single-stage PFC flyback LEDdriver with the variable boost inductor is experimentally verifiedon a 24-V/91-W prototype circuit.

Index Terms—LED driver, power factor correction (PFC), singlestage, variable boost inductance.

I. INTRODUCTION

THE technology and performance of high-brightness LEDs(HB LEDs) has undergone significant improvements

driven by new applications in liquid-crystal-display (LCD)backlighting, automobiles, traffic lights, and general-purposelighting [1]–[3]. As a solid-state light source that does not con-tain mercury, HB LEDs have been widely accepted becauseof their superior longevity, low-maintenance requirements, andcontinuously improving luminance with a great potential to re-place existing lighting sources such as incandescent and fluo-rescent lamps in the future.

For input-power levels above 25 W, ac/dc LED drivers mustcomply with the line-current harmonic limits set by the IEC61000-3-2 class C [4] and the corresponding Japanese JIS C61000-3-2 class C [5] regulations. Generally, it is difficult tomeet these requirements by employing passive power-factor-correction (PFC) techniques, especially for the universal input-

Manuscript received March 8, 2010; revised August 28, 2010; acceptedSeptember 20, 2010. Date of current version February 7, 2012. This paperwas presented at the 25th Annual IEEE Applied Power Electronics Conference(APEC), Palm Springs, CA, Feb. 21–25, 2010. Recommended for publicationby Associate Editor M. Alonso.

Y. Hu is with Cree Inc., Morrisville, NC 27560, USA (e-mail:[email protected]).

L. Huber and M. M. Jovanovic are with Power Electronics Laboratory,Delta Products Corporation, Research Triangle Park, NC 27709 USA (e-mail:[email protected], [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2010.2082564

Fig. 1. Conventional two-stage LED driver.

Fig. 2. Single-stage flyback LED driver without energy-storage capacitor atprimary side [8].

voltage-range (90–270 Vrms) applications. As a result, themajority of today’s universal-input-voltage-range ac/dc LEDdrivers are implemented with active PFC.

A conventional two-stage LED driver with active PFC isshown in Fig. 1. The first stage provides a near unity powerfactor and a low total harmonic distortion (THD) in the entireuniversal input-voltage range (90–270 Vrms), while the seconddc/dc stage is used to provide a tight regulation of the output.Since the circuit in Fig. 1 requires two independently controlledpower switches and two control circuits, it suffers from an in-creased component count and cost. In low-power lighting ap-plications, where the cost is the dominant consideration, thetwo-stage approach is less competitive than single-stage activePFC implementations [6], [7], where the PFC stage is integratedwith the dc/dc stage. Moreover, due to its minimal componentcount and low cost, the single-stage, single-switch, PFC fly-back converter [8], [9] has emerged as the most widely usedsingle-stage topology.

Generally, a single-stage PFC ac/dc converter can be imple-mented without or with a bulk capacitor at the primary side, as il-lustrated in Figs. 2 and 3, respectively. Although the single-stage

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1580 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012

Fig. 3. Single-stage flyback LED driver with energy-storage capacitor at pri-mary side [9].

PFC circuit in Fig. 2 [8] has the advantage of a lower componentcount, its output voltage has a high ripple at twice the line fre-quency unless very large output capacitors are used. Since foran LED load, a small variation in the driving voltage can lead toa large variation in the LED current, a large ripple of the LEDcurrent would seriously affect the reliability and longevity [10],as well as the luminous efficacy [11] of the LEDs. Therefore,the approach in Fig. 2 often requires a postregulator, which addscost and lowers the efficiency.

The single-stage PFC flyback topology shown in Fig. 3 [9]presents one of the most cost-effective single-stage solutions.In this converter, a PFC boost stage is integrated with the dc/dcflyback stage. The PFC boost stage operates in discontinuousconduction mode (DCM), while the dc/dc flyback stage operatesat the DCM/continuous-conduction-mode (CCM) boundary. Alow input-current harmonic distortion can be achieved due tothe inherent property of the DCM PFC boost converter to drawa near sinusoidal current if its duty cycle is held relatively con-stant during a half line cycle. However, voltage V B across bulkcapacitor CB is not regulated, and at high line, it can increaseto impractical levels. To reduce the bulk-capacitor voltage, oneterminal of the boost-inductor winding is connected to a tap-ping point of the primary winding of the flyback transformer,which provides a negative magnetic feedback [12]. However,the tapping of the flyback primary winding also results in azero-crossing distortion of the line current. In fact, as long asthe instantaneous line voltage is lower than the voltage at thetapping point, no current is drawn from the input, which re-duces the power factor and increases the line-current harmonics.Therefore, the selection of the tapping point is determined bythe tradeoff between the reduction of the bulk-capacitor voltageand the quality of the line current.

The single-stage PFC flyback in Fig. 3 has been successfullyapplied in adapter/charger applications for the universal linevoltage, where the line-current harmonics need to meet the IEC61000-3-2 and JIS C 61000-3-2 class D limits, which are lessstringent than the corresponding class C limits.

It was shown in [13] that the single-stage PFC flyback inFig. 3 with a constant boost inductance cannot be designed toachieve a practical maximum bulk-capacitor voltage level (i.e.,less than 450 V) at high line while meeting the JIS C 61000-3-2class C line-current harmonic limits at low line. To overcomethese limitations, a variable boost inductance is required, i.e.,a high boost inductance at high line to limit the bulk-capacitor

Fig. 4. Basic variable inductor by adding a dc-bias flux to main magnetic flux:(a) structure; (b) principle of operation [14].

voltage and a lower boost inductance at low line to ensure DCMoperation and, consequently, a low THD. In fact, at low line,when a constant boost inductance is used, the inductor willenter CCM operation around the peak of the line-voltage, andthe line-current waveform will have a surge around its peakvalue [13], resulting in an increased THD. Furthermore, if thebulk-capacitor voltage is slightly lower than the peak value ofthe rectified line voltage, the peak charging of the bulk capacitorthrough the bridge rectifier will also result in a surge in the line-current waveform [12] with an increased THD.

In this paper, it is shown that by optimizing the tapping pointof the primary winding of the flyback transformer in Fig. 3, andby employing a novel technique to reduce the boost inductance atlow line, a high power factor and a low THD with relatively highefficiency can be achieved such that the line-current harmonicssatisfy the IEC 61000-3-2 and corresponding Japanese JIS C61000-3-2 class C limits, while the bulk-capacitor voltage islimited below 400 V.

II. VARIABLE INDUCTOR FOR LED APPLICATIONS

A variable inductor for LED applications can be achievedby controlling the inductance with a dc-bias current, i.e., byadding a dc-bias flux to the main magnetic flux [14]–[20]. Thebasic concept is shown in Fig. 4, where a control winding NCis added to the inductor winding NL on the same magneticcore [14]. A dc-bias current IC flowing through the controlwinding produces a bias magnetic flux ΦC . The main magneticflux ΦL produced by the inductor current is superimposed on

HU et al.: SINGLE-STAGE, UNIVERSAL-INPUT AC/DC LED DRIVER WITH CURRENT-CONTROLLED VARIABLE PFC BOOST INDUCTOR 1581

Fig. 5. Improved variable inductor: (a) structure; principle of operation (b)without and (c) with bias current [15], [16].

the bias magnetic flux ΦC . As the dc-bias magnetizing forceincreases, the permeability of the core material, i.e., the slopeof the B–H curve (= limΔH→0 ΔB/ΔH) decreases, as shownin Fig. 4(b), leading to a decreased inductance.

To reduce the circuit complexity and maximize efficiency, inthe LED driver described in this paper, the load current is used asthe dc-bias current by connecting the control winding in serieswith the LED load. Because in this implementation the ripplevoltage induced in the control winding affects the LED current,it is of the utmost importance to minimize this voltage ripple sothat the LED ripple current is minimized to the point that it doesnot affect the light quality. Since the induced voltage across thecontrol winding depends on the coupling between the controland inductor windings, the coupling plays a major role in thedesign of a variable inductor for this LED driver application.The basic structure of the current-controlled variable inductorshown in Fig. 4(a) is not suitable for LED applications becausethe control winding is strongly coupled to the inductor winding,resulting in a large induced ac voltage in the control winding.

An improved variable inductor is proposed in [15] and [16],where the inductor winding is divided into two identical por-tions, which are wound on two identical toroidal cores andconnected in series so as to produce opposing fluxes throughthe control winding, which is wound over both cores, as shownin Fig. 5(a). Ideally, due to the opposing fluxes, there is nocoupling between the inductor and control windings. Without abias current in the control winding, both cores exhibit the sameflux-density variation, i.e., ΔB1 = ΔB2 , as shown in Fig. 5(b).

Fig. 6. Variable inductor using EE cores with control winding wound on centerleg [17].

Therefore, the total inductance is twice the inductance of the in-dividual inductor windings. Due to the equal but opposing mag-netic fluxes through the control winding, the induced voltage inthe control winding is zero. However, with a bias current in thecontrol winding, a biasing field H0 is produced that displacesthe operating point of the cores along their B–H curves, asshown in Fig. 5(c). One core (core 1) operates in the nonlinearto saturation region, whereas the other core (core 2) operatesin the nonlinear to linear region along their respective B–Hcurves. As a result, the flux-density variation and, consequently,the permeability in both cores are reduced compared to the casewithout a dc bias. Therefore, the total inductance is reduced. Inaddition, the flux-density variation in core 1 is smaller than thatin core 2, i.e., ΔB1 < ΔB2 . Consequently, the total flux-densityvariation through the control winding is not zero, resulting in aninduced ac voltage in the control winding. It should be noted thatwith an increased field H in Fig. 5(c), i.e., at large signals, thedifference between the two opposing fluxes increases, resultingin an increased ac voltage in the control winding.

Another implementation of the variable inductor in Fig. 5 ispresented in [17], where instead of two toroidal cores a pair of Ecores are used, as shown in Fig. 6. A variable inductor, similarto that in Fig. 6, with the difference that the positions of theinductor winding and control winding are interchanged, i.e., thecontrol winding is divided into two identical portions, whichare wound on the outer legs of the EE core and connected inseries, while the inductor winding is wound on the center legof the EE core, is shown in Fig. 7 [18]–[20]. It should be notedin Fig. 7 that the air gaps from the outer legs of the EE core inFig. 6 are moved to the central leg. The basic operation of thevariable inductor in Fig. 7 is the same as that of the variableinductor in Fig. 6. However, the variable inductor in Fig. 7 hasa significant advantage compared to the variable inductor inFig. 6. As can be seen in Fig. 7, the path of the bias magneticflux ΦC does not include an air gap and, consequently, a lowerbias magnetomotive force is required to achieve the desiredinductance value.

In this paper, a new structure of the current-controlled vari-able inductor is proposed as shown in Fig. 8. The inductor is


Fig. 7. Variable inductor using EE cores with control winding wound on outerlegs [18]–[20].

Fig. 8. Proposed current-controlled variable inductor.

implemented with an EE core and winding NL , whereas controlwinding NC is placed on a half core (E) that is closely attachedto the bottom part of the EE core. It should be noted that in thisstructure there is practically no air gap at the interface betweenthe two cores, except for a very small gap due to the roughnessof the contact surfaces. Other types of cores such as EI and Ucores can be also used. When dc-bias current IC flows in controlwinding NC , a magnetic flux ΦC is induced, that is added to themain magnetic flux ΦL at the bottom part of the boost-inductorEE core. As a result, at the bottom part of the EE core, the effec-tive permeability is reduced, and consequently, the inductanceis decreased.

III. SINGLE-STAGE PFC FLYBACK LED DRIVER WITH

VARIABLE BOOST INDUCTOR

A. Variable Boost Inductor

The block diagram of the proposed single-stage PFC flybackLED driver with variable boost inductor is shown in Fig. 9.The boost inductance LB is controlled by the load current, i.e.,IC = ILOAD . The control circuit includes switch QC , a dc-bias

Fig. 9. Block diagram of proposed single-stage PFC flyback with variableboost inductance for HB LED applications.

control circuit, an input voltage sensing circuit, and a low-passLC filter. At high line, switch QC is closed, shorting bias wind-ing NC . As a result, there is no bias current through winding NC ,and the boost inductance does not change. At low line, switchQC is open and the bias current flows through bias winding NC ,inducing a magnetic flux ΦC that is added to the main mag-netic flux ΦLB at the bottom part of the boost-inductor EE core.Consequently, the boost inductance is decreased. The reductionof the boost inductance is proportional to the applied bias cur-rent. The low-pass LC filter in parallel with control windingNC essentially prevents the ac ripple component of the control-winding current from flowing through the LED load, namely,the control-winding current, in addition to the dc component,has a relatively large ac component, which is due to the inducedac voltage in the control winding. Without filter inductance LC ,the amplitude of the ac ripple current of the control winding willbe very large if the leakage inductance of the control windingunder the dc-bias current is small. The value of inductance LCand capacitance CC should be large enough so that the ac ripplecurrent through the LED load is smaller than a specified per-centage (5% in the most stringent case) of the dc load current.

B. Control Circuit

Fig. 10 shows the detailed schematic of the proposed single-stage PFC flyback HB LED driver. The input voltage is sensedby a circuit comprising winding N3 wound on the boost-inductorEE core, diode D8 , and capacitor C1 . MOSFET Q2 connected


Fig. 10. Schematic of proposed single-stage PFC flyback with variable boost inductance for HB LED applications.

in series with the LED load is the bias switch QC in Fig. 9.When main switch Q1 is turned on, diode D8 is forward biased,peak charging capacitor C1 with a voltage

VC1 =(√

2VIN − N1

NPVB

)N3

NLB

− VD8 (1)

where N 1 , NP , and NLB are the number of turns of the feedbackwinding, primary winding of the flyback transformer, and theboost-inductor winding, respectively. A proper number of turnsN 3 (N3 = 2) is chosen so that the voltage across capacitor C1turns on Zener diode ZD1 (VZD1 = 10V) only at high line (180–270 Vrms). When ZD1 is turned on, switch Q4 is turned on andswitch Q3 is turned off. As a result, the gate-to-source voltage ofMOSFET Q2 is high and Q2 is turned on. The load current flowsthrough switch Q2 and the bias current of control winding NCis approximately zero. Therefore, the boost inductance remainsunchanged. It should be noted that the turn-on resistance ofswitch Q2 needs to be negligible compared to the resistanceof control winding NC to prevent a substantial current flowingthrough the control winding at high line. Otherwise, the effectiveboost inductance would become lower and voltage VB wouldincrease to an undesirable level. At low line, the voltage acrosscapacitor C1 is lower than the turn-on voltage of ZD1 , Q4 isturned off and Q3 is turned on. As a result, the gate-to-sourcevoltage of MOSFET Q2 is low and Q2 is turned off. The entireload current flows through the control winding. Therefore, theboost inductance is reduced.

C. Design Considerations

The design of the flyback circuit in Fig. 10 without the PFCpart is basically the same as the design of the conventionalflyback circuit. Key design parameters of the PFC part of theflyback circuit in Fig. 10 are number of turns N 1 and boostinductance LB . The design goal is to achieve a proper PFCoperation, i.e., the line current to meet the IEC 61000-3-2 andJIS C 61000-3-2 class C current harmonic limits, and to limitbulk-capacitor voltage VB below 400 V.

It was shown in [13] that bulk-capacitor voltage V B is afunction of input voltage vIN , ratio of inductances LB/LM ,

Fig. 11. Calculated voltage VB versus ratio N1 /NP .

ratio of number of turns N1/NP , and output voltage VO , i.e.,

VB = f(vIN , LB/LM , N1/NP , VO). (2)

The bulk-capacitor voltage increases with increasing rmsvalue of the line voltage, and it decreases with increasing turnsratio N1/NP and increasing ratio LB/LM of inductances, as il-lustrated in Figs. 11 and 12, respectively. It should be notedthat VB does not depend on the load current as explainedin [6].

For proper PFC operation, in order to meet the IEC 61000-3-2and JIS C 61000-3-2 class C limits, the zero-crossing distortionof the line current due to the tapping of the primary windingshould be optimized, and the boost inductor should be preventedfrom operating in CCM.

Following the same procedure for the analysis of the bulk-capacitor voltage as in [13], the line-current waveform and thecorresponding THD can be obtained. For example, calculatedline-current waveforms at three different turns ratios N1/NP ,at nominal low line (VIN = 120Vrms) are shown in Fig. 13. Itfollows from Fig. 13 that with increasing turns ratio N1/NP thedead-angle of the line current around zero crossing increases,resulting in an increased THD. As another example, Fig. 14


Fig. 12. Calculated voltage VB versus ratio LB /LM .

Fig. 13. Calculated line-current waveforms for different ratios N1 /NP .

Fig. 14. Calculated THD versus ratio N1 /NP at VIN = 230 Vrm s .

shows calculated THD versus N1/NP for three different valuesof LB , at nominal high line (VIN = 230Vrms). It follows fromFig. 14 that THD significantly increases with increasing ratioN1/NP , whereas the presented variation of LB does not havesignificant effect on THD. It can be seen in Fig. 14 that for a

Fig. 15. Desired range for ratio LB /LM versus ratio N1 /NP : (a) in lowline-voltage range; (b) in high line-voltage range.

THD lower than 20%, which is a typical requirement for lightingapplications, turns ratio N1/NP should be smaller than 0.15.

In order to ensure DCM operation of boost inductor LB ,the time to completely reset the boost-inductor core should beshorter than the turn-off time of switch Q1 around the peak ofthe line voltage (worst case), i.e.,

TRES LB ≤ TOFF Q1 . (3)

In this way, the current flowing through the boost inductordecreases to zero before switch Q1 is turned on, ensuring a highpower factor and a low THD.

The time to completely reset the boost-inductor core and theturn-off time of switch Q1 operating at DCM/CCM boundarycan be, respectively, expressed as

TRES LB

=(vrec

IN − N1VB/NP)NPVO/NS

[VB + (1 − N1/NP)NPVO/NS − vrecIN ](VB + NPVO/NS)

TS

(4)

and

TOFF Q1 =(

1 − VONP/NS

VB + VONP/NS

)TS (5)

where TS is the switching period of switch Q1 and vrecIN is the

instantaneous rectified line voltage.


Fig. 16. Proposed variable boost inductor.

Using (2)–(5), the maximum ratio LB/LM versus N1/NPthat will ensure DCM operation of LB can be obtained. InFig. 15(a), the calculated maximum ratio LB/LM versus N1/NPthat ensures DCM operation of LB is presented at nominal lowline (120 Vrms). Fig. 15(a) also includes the calculated minimumLB/LM versus N1/NP that ensures limiting the bulk-capacitorvoltage below 400 V at the upper end of the low line-voltagerange (i.e., 140 Vrms).

The calculated maximum and minimum ratios LB/LM versusN1/NP in the high line-voltage range are presented in Fig. 15(b).As follows from Fig. 15(b), in the high line-voltage range, thepossible range of ratio LB/LM is much narrower than in thelow line-voltage range. It also follows from Fig. 15(b) that theminimum possible turns ratio N1/NP is 0.1.

It can be clearly seen from Fig. 15 that different ratios LB/LMare required in the low line-voltage range and in the high line-voltage range, i.e., that a variable boost inductance is requiredin the universal line-voltage range.

Based on the calculated results presented in Figs. 11–14, turnsratio N1/NP = 0.13 (N 1 = 4, NP = 30) is selected for the finaldesign. It follows from Fig. 15(b) that for N1/NP = 0.13 in thehigh line-voltage range, ratio LB/LM should be around 0.6,i.e., the desired boost inductance is 390 μH for the selectedLM = 645 μH.

Finally, it follows from Fig. 15(a) that for N1/NP = 0.13 inthe low line-voltage range, ratio LB/LM should be smaller than0.32, i.e., the desired boost inductance should be smaller than206μH for the selected LM = 645 μH.

IV. EXPERIMENTAL RESULTS

To verify the proposed variable boost-inductance technique,a 24-V/91-W single-stage PFC flyback prototype for HB LEDapplications was built. The control circuit is based on the quasi-resonant controller NCP1207 from On Semiconductor. Fig. 16

Fig. 17. Measured boost inductance versus dc-bias current.

Fig. 18. Measured voltage vCc [50 mV/div] across capacitor CC and mea-sured current iC [2 A/div] through control winding at nominal low line (120Vrm s ) and full load (IO = 3.8 A). Two bottom traces obtained by zooming inaround peak value of current iC .

shows a photograph of the proposed current-controlled variableboost inductor, while Fig. 17 shows the measured inductanceversus dc-bias current. As shown in Fig. 17, the effective induc-tance drops faster with increasing dc-bias current when the turnsnumber NC of the control winding is higher, and therefore, itrequires a lower dc-bias current. However, a higher turns num-ber NC leads to a higher resistance, hence, higher winding lossat the same load current. Moreover, a lower boost inductancegenerally results in a lower overall efficiency of the LED driver.Therefore, turns number NC should be minimized to ensurelow-enough boost inductance and DCM operation at low linewhile maintaining relatively high efficiency. A turns numberNC = 12 was selected for the final design. The dc resistanceof winding NC is 20 mΩ, while the turn-ON resistance of biasswitch Q2 is 1.8 mΩ (<<20 mΩ). At low line, switch Q2 isturned off, and the entire load current IO = 3.8 A flows throughthe control winding resulting in a power loss of 0.29 W, i.e.,a 0.3% decrease of efficiency. At high line, bias switch Q2 isturned on and control winding NC is essentially shorted since


Fig. 19. Measured line-current (500 mA/div) and line-voltage (100 V/div)waveforms: (a) VIN = 120 Vrm s ; (b) VIN = 230 Vrm s .

its dc resistance is much higher than the turn-ON resistance ofswitch Q2 , resulting in a power loss of 22 mW at IO = 3.8 A.

The measured voltage across capacitor CC and the mea-sured current through the control winding at nominal low line(120 Vrms) and full load (IO = 3.8 A) are shown in Fig. 18.In the worst case (maximum ripple current), the peak-to-peakvalue of capacitor CC voltage is around 100 mV (neglecting thehigh-frequency noise), whereas the peak-to-peak value of theac ripple current is 3.4 A. Without the external inductor LC , thepeak-to-peak value of the ac ripple current increases to 7 A.

The measured line-voltage and line-current waveforms at fullload are shown in Fig. 19. At nominal low line (120 Vrms),THD = 15%, PF = 0.985, VB = 171V, and efficiency = 88%;while at nominal high line (230 Vrms), THD = 10.39%, PF= 0.947, VB = 327V, and efficiency = 91% were obtained.It should be noted that THD = 15% measured at 120 Vrms is

Fig. 20. Measured line-current harmonics at (a) VIN = 120 Vrm s ; (b) VIN =230 Vrm s .

in good agreement with the calculated value (13.1%) shown inFig. 13. It should be also noted that THD = 10.39% measuredat 230 Vrms is in good agreement with the calculated value(∼10%) shown in Fig. 14 at N1/NP = 0.1 and LB = 400 μH.

Measured line-current harmonics at full load are shown inFig. 20. It can be seen that the line-current harmonics are belowthe IEC 61000-3-2 and JIS C 61000-3-2 class C limits withenough margin. The measured efficiency versus output poweris shown in Fig. 21. It should be noted that the measured ef-ficiency at full load is well above 85%, which is the typicalrequirement at full load. The maximum bulk-capacitor voltage,obtained at VIN = 270Vrms , is VB max = 398V, which is ingood agreement with the calculated value shown in Fig. 12 atLB/LM = 0.6.

Measurements with an actual LED load were also performed.Four LED strings each with 7 series-connected white LEDs(Philips Lumileds, LXHL-LW3 C) were paralleled and directlydriven by the proposed PFC flyback prototype with an outputvoltage of 24 V. The measured waveform of the LED current atnominal low line (120Vrms) and full load is shown in Fig. 22.The peak-to-peak value of the ac ripple current is 4.6% of thefull load current (3.8 A). At nominal high line (230Vrms), themeasured peak-to-peak ac ripple current is 2.8% of the full loadcurrent.


Fig. 21. Measured efficiency versus output power.

Fig. 22. Measured waveform of LED current at nominal low line (120 Vrm s )and full load. Top trace: IO [1 A/div, 2 ms/div]; bottom trace: IO RIPPLE[50 mA/div, 10 μs/div].

V. SUMMARY

A single-stage PFC flyback with a variable boost inductancefor HB LED applications for the universal input voltage is pre-sented in this paper. The boost inductance has a constant highvalue at high line, while at low line it is reduced proportionallyto the load current. Experimental results obtained on a 24-V/91-W prototype show that the proposed PFC converter achieves anefficiency of 88%, a power factor of 0.985 and a THD of 15%at nominal low line (120 Vrms), and an efficiency of 91%, apower factor of 0.947 and a THD of 10.39% at nominal highline (230 Vrms). Line-current harmonics satisfy the IEC 61000-3-2 and corresponding Japanese JIS C 61000-3-2 class C limitswith enough margin. The maximum bulk-capacitor voltage isslightly less than 400 V.

Therefore, the proposed PFC flyback circuit is suitable fordirectly driving LED strings, and no post-regulators are nec-essary, which is a significant advantage over the conventionalPFC flyback circuit without an energy-storage capacitor at theprimary side.

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Yuequan Hu received the Bachelor’s and Master’sdegrees in mechanical engineering, and the Ph.D. de-gree in electrical engineering from the University ofScience and Technology of China, Hefei, China, in1989, 1992, and 1999, respectively.

From May 2003 to Oct. 2010, he was an R&Dmember of the Power Electronics Laboratory, DeltaProducts Corporation. Since November 2010, he hasbeen a Senior Design Engineer at Cree Inc., a market-leading innovator and manufacturer of lighting-classLEDs, indoor and outdoor lighting, and semiconduc-

tor solutions for wireless and power applications. His main research interestsfocus on high-intensity discharge (HID) lamp ballasts and advanced LED light-ing solutions.


Laszlo Huber (M’86) was born in Novi Sad, Yu-goslavia, in 1953. He received the Dipl. Eng. de-gree from the University of Novi Sad, Novi Sad, in1977, the M.S. degree from the University of Nis,Nis, Yugoslavia, in 1977, and the Ph.D. degree fromthe University of Novi Sad in 1992, all in electricalengineering.

From 1977 to 1992, he was an Instructor at the In-stitute for Power and Electronics, University of NoviSad. In 1992, he joined the Virginia Power Electron-ics Center, Virginia Tech, Blacksburg, as a Visiting

Professor. From 1993 to 1994, he was a Research Scientist at the Virginia PowerElectronics Center. Since 1994, he has been a Senior Member of the R&D Staff,Power Electronics Laboratory, Delta Products Corporation, Research TrianglePark, NC, the Advanced R&D unit of Delta Electronics, Inc., Taiwan, one ofthe world’s largest manufacturers of power supplies. His 33-year experienceincludes the analysis, simulation, and design of high-frequency, high-power-density, single-phase and three-phase power processors; modeling, simulation,evaluation, and application of high-power semiconductor devices; and model-ing, simulation, analysis, and design of analog and digital electronics circuits.He has authored or coauthored 80 technical papers. He holds five U.S. patents.

Dr. Huber is the recipient of the IEEE Power Electronics Society (PELS)Transactions Prize Paper Award for the best paper published in 2009 and theYugoslav Conference on Electronics, Telecommunication, Automation, and Nu-clear Technique (ETAN) Best Paper Award in 1990.

Milan M. Jovanovic (S’85–M’88–SM’89–F’01)was born in Belgrade, Serbia. He received the Dipl.Ing. degree in electrical engineering from the Univer-sity of Belgrade, Belgrade.

He is currently the Chief Technology Officer of thePower Systems Business Group, Delta Electronics,Inc., Taiwan, one of the world’s largest manufactur-ers of power supplies, and Vice President for R&D ofDelta Products Corporation, Research Triangle Park,NC.

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