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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 7, JULY 2013 2685

Calibration-Kit Design for Millimeter-WaveSilicon Integrated Circuits

Dylan F. Williams, Fellow, IEEE, Phillip Corson, Member, IEEE, Jahnavi Sharma, Student Member, IEEE,Harish Krishnaswamy, Member, IEEE, Wei Tai, Member, IEEE, Zacharias George, David Ricketts, Paul Watson,

Eric Dacquay, Member, IEEE, and Sorin P. Voinigescu, Senior Member, IEEE

Abstract—We study and present design guidelines for thru-re-flect-line vector-network-analyzer calibration kits used for char-acterizing circuits and transistors fabricated on silicon integratedcircuits at millimeter-wave frequencies. We compare contact-paddesigns and develop fixed-fill contacts that achieve both repeat-able and low contact-pad capacitances. We develop a fill-free andmesh-free transmission line structure for the calibration kit andcompare it to similar transmission lines withmeshed ground plane.We also develop a gold plating process that greatly improves con-tact repeatability, permitting the use of redundant multiline cali-brations. This in turn simplifies the development of an error anal-ysis. Finally, we apply the technique to state-of-the-art transistorcharacterization, and present measured results with uncertainties.

Index Terms—Calibration, measurement, millimeter wave, scat-tering parameters, silicon, transistor, uncertainty, vector networkanalyzer.

I. INTRODUCTION

W E STUDY the contact pads, ground-plane meshes,and number of transmission lines used in mil-

limeter-wave thru-reflect-line (TRL) vector-network-analyzercalibration kits fabricated in the IBM 45-nm complementarymetal–oxide–semiconductor (CMOS) silicon-on-insulatorSOI12S0 integrated-circuit process.1 This leads to straightfor-ward guidelines for calibration-kit design. We then apply thecalibration kits to transistor characterization and explore theirfrequency limitations.

Manuscript received March 09, 2013; accepted May 07, 2013. Date of pub-lication June 14, 2013; date of current version June 28, 2013. This work wassupported by the Defense Advanced Research Projects Agency (DARPA) underthe ELASTx Program.D. F. Williams is with the National Institute of Standards and Technology,

Boulder, CO 80305 USA (e-mail: [email protected]).P. Corson is with IBM Semiconductor Research and Development Center,

Essex Junction, VT 05452 USA.J. Sharma and H. Krishnaswamy are with the Department of Electrical Engi-

neering, Columbia University, New York, NY 10027 USA.W. Tai, Z. George, and D. Ricketts are with the Electrical and Computer En-

gineering Department, Carnegie Mellon University, Pittsburgh, PA 15213-3890USA.P. Watson is with the Air Force Research Laboratory, Wright Patterson Air

Force Base, Dayton, OH 45433-7132 USA.E. Dacquay and S. P. Voinigescu are with the Electrical and Computer Engi-

neering Department, University of Toronto, Toronto, ON M5S 3G4, Canada.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TMTT.2013.2265685

1We use brand names only to better specify the experimental conditions. TheNational Institute of Standards and Technology does not endorse commercialproducts. Other products may work as well or better.

Vector-network-analyzer calibrations used to characterizesilicon transistors are usually performed on commercialimpedance-standard substrates fabricated on an alumina sub-strate with a short-open-load-thru (SOLT), line-reflect-match(LRM) [1], line-reflect-reflect-match (LRRM) [2], or similarcalibration algorithm. This first tier calibration moves thecalibration reference plane “to the probe tips.” The first-tierprobe-tip calibration is then often followed by a second-tiercalibration intended to move the calibration reference planefrom the probe tips to the transistor terminals [3]–[5]. Thesesecond tier calibrations are used to subtract out the electricalparasitics associated with contact pads, short transmission linesin the interconnect stack separating the contact pads from thetransistors, and access vias connecting those transmission linesto transistors fabricated in the silicon substrate.The TRL calibration method avoids calibrating at the probe

tip, where the lack of a transmission line makes it difficult torigorously define voltages, currents, and wave parameters. TheTRL calibration is unique in that it puts the calibration refer-ence plane directly in a transmission line where wave parame-ters, voltages, and currents can be rigorously defined. The TRLcalibration does this by measuring traveling-wave amplitudes ina single-mode transmission line at the center of a thru with norecourse to any assumptions with respect to symmetry, loss, orthe lumped-element nature of the standards [6]. For this reason,the TRL calibration has been adopted as the calibration of ref-erence for coaxial measurements at microwave frequencies.References [7] and [8] introduced an accurate approach for

determining the characteristic impedance of small printed trans-mission lines from the propagation constant measured by theTRL calibration. This advance allows the reference impedanceof on-wafer TRL calibrations to be accurately set to 50 whenthe lines are quasi-TEM and employ low-loss dielectrics, andhas led to the TRL calibration also being adopted as the calibra-tion of reference for on-wafer measurements at microwave fre-quencies [2]; [9]–[11]. Furthermore, approaches that make useof redundant calibration standards [12]–[15] have overcome thebandwidth limitations of the early TRL algorithms.Since the TRL calibration makes few assumptions about the

calibration standards, it is particularly well suited to performingmeasurements at millimeter-wave frequencies and beyond. Seoet al. estimated increases in the capacitance due to fill and re-sistance due to ground-plane meshing in TRL calibrations per-formed in transmission lines fabricated in silicon interconnectstacks with a 65-nm IBM process [16]. Seo et al. not only per-formed TRL calibrations in these lines, but used them in am-plifier matching networks. Recent work on calibrations in thin

U.S. Government work not protected by U.S. copyright.

2686 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 7, JULY 2013

polymer microstrip transmission lines has demonstrated accu-rate transistor characterization to 750 GHz with the TRL ap-proach [17]. The fundamental nature of the TRL calibrationalso simplifies the development of error analyses, and reason-able error estimates can be obtained simply with the use of thesame redundant calibration standards used to extend the band-width of the calibrations [13]–[15].TRL calibrations are not typically used to characterize sil-

icon transistors in part because of the expense of fabricating theTRL standards on the silicon die, the difficulty of repeatedlyforming good contacts with the aluminum or copper contactpads on the silicon die, the difficulty of performing accuratemeasurements at very low frequencies with TRL calibra-tions, and the availability of commercial impedance-standardsubstrates supporting short-open-load, LRM, and similarlumped-element-based calibrations with good accuracy atfrequencies suitable for characterizing slower silicon devices.Layout and automated testing is also complicated by the needfor transmission lines of different lengths. As a result, mostsilicon transistors are characterized by building microstriplines, or closely related conductor-backed coplanar lines, in themetal interconnect stack, typically using multilayered groundsstitched together with vias, and off-wafer lumped-elementcalibrations with easy-to-contact gold-plated contact pads.However, as the speed of silicon transistors has improved so

has the need for accurate high-frequency vector-network-an-alyzer calibrations for characterizing transistors fabricated onsilicon. In this paper, we examine the fundamental limitationsof TRL calibrations performed in the interconnect stack of theSOI12S0 integrated-circuit process. We show that gold platingcan be used to improve the repeatability of contacts to transmis-sion lines fabricated on silicon die. This greatly improves the ac-curacy and reliability of TRL calibrations performed directly onsilicon wafers. We also show that field penetration into the sil-icon is low, allowing the methods described in [7] and [8] to beused to set the reference impedance of the TRL calibration accu-rately, and that the loss of the small microstrip lines fabricatedin the interconnect stack is not too large to prevent the algo-rithm from converging. We demonstrate the TRL calibration inthe SOI12S0 integrated-circuit process with transistor measure-ments at millimeter wavelengths, and show that the calibrationcontinues to behave well far into the sub-millimeter wavelengthregion.

II. TRL CALIBRATION KIT

Fig. 1 shows a photograph of a typical test structure we fabri-cated with its contact pads and 150- m-long microstrip accesslines, as well as a sketch of the cross section of the microstriptransmission lines we used. We used contact pads and accesslines of the same design for the test structures, devices-under-test, and in the calibration kit to minimize calibration and mea-surement errors.We supplemented the 300- m-long thru line in the TRL cal-

ibration kit with a pair of symmetric shorts offset by 150 mfrom the contact pads, and four transmission lines of additionallength 200, 300, 800, and 2000 m. This design sets the initialreference plane of the TRL calibration 150 m from the contactpads in the center of the thru line. This position corresponds to

Fig. 1. Transmission-line calibration artifacts and test structures we employed.The interconnect stack supports 11 levels of metal: LB, UB, UA, B3, B2, B1,C2, C1, M3, M2, and M1. (a) Photograph of a test structure showing the contactpads, access lines, and device-under-test. The signal contact pads are 40- mlong and 30- mwide, and are separated from the ground contact pads by 15 m.Some of the automated fill on the top metal layers can be seen in the photograph.The photograph also shows some inadvertent top-metal-level fill directly aroundthe contact pads that we could have eliminated with an additional exclusionlayer. (b) Cross section of the transmission line.

the input at the left of the transistor, as shown in the figure. Themultiple lines allow us to perform broadband TRL calibration.We fabricated the access lines and transmission lines used in

the TRL calibration kit in the interconnect stack of the IBM45-nm CMOS silicon-on-insulator SOI12S0 integrated-circuitprocess (see Fig. 1). That technology supports three thick metaland dielectric layers at the top of the interconnect stack. Wefabricated our transmission-line center conductor in the top-most LB layer, and were able to completely suppress metal fillin the two UA and UB layers below this topmost LB layerover a 24- m width while adhering to the design rules. Thecenter conductor was 6- m wide and supported by approxi-mately 6.275 m of dielectric with a relative dielectric constantof about 4.0. This put the nominal characteristic impedance ofthe transmission lines at about 75 , a reasonable match to ournominally 50- probes.To set the reference impedance of the TRL calibration to

50 , we first determined the capacitance per unit length of theline at low frequencies with the load method of [8]. However, as

WILLIAMS et al.: CALIBRATION-KIT DESIGN FOR MILLIMETER-WAVE SILICON INTEGRATED CIRCUITS 2687

we did not have an on-wafer load, we used an off-wafer load in-stead, potentially adding some error into the overall referenceimpedance of the calibration. We then determined the actualcharacteristic impedance of the lines from the measured propa-gation constant with themethod of [7], which works well in low-loss dielectrics. This provided us with the information neededto account for the complex characteristic impedance of thesetransmission lines and to transform the reference impedance ofthe TRL calibration to 50 . This correction is important evenwhen nominally 50- transmission lines are used in the cali-bration because the actual characteristic impedance of printedlines becomes large at low frequencies as the resistance per unitlength of the lines becomes comparable to the inductive reac-tance per unit length of the lines.We formed the ground plane from the fourth level of

metal (B3) from the top of the interconnect stack. This solidlevel of metal was 12- m wide and approximately 255-nmthick. To meet the design rules for the IBM process, weadded 3- m-wide strips of B3 metal spaced 3 m from these12- m-wide ground lines and tied the ground plane togetherwith 7.6- and 7.0- m-wide strips in the next two higher levelsof metal UB and UA, as shown in Fig. 1. We also meshedtogether all of the lower levels of metal below the B3 groundplane.

III. CONTACT-PAD DESIGN

We optimized our calibration-kit design to reduce contact-padcapacitance and improve contact resistance.

A. Contact-Pad Capacitance

The TRL calibration corrects for the electrical behavior ofthe vector network analyzer, probes, contact pads, and accesseslines. After the calibration is performed, the measurement refer-ence plane is set in the center of the thru, and the initial referenceimpedance of the calibration is transformed to 50 .Although the calibration corrects for the capacitance of the

contact pads, the capacitance of the pads is large enough at mil-limeter-wave frequencies to adversely impact measurements.For example, a contact-pad capacitance of 17 fF correspondsto a shunt impedance of less than 100 at 100 GHz, a para-sitic that is of the same order of magnitude as the impedanceof the measurement system. Equally important, the calibrationdoes not correct for differences in contact-pad capacitance fromcalibration artifact to calibration artifact and from calibrationartifact to device-under-test.Reference [18] suggests opening windows under contact pads

to reduce pad capacitance. However, this approach was devel-oped for interconnect stacks with only a few metal layers andthinner dielectrics than in the IBM technology, and our electro-magnetic simulations indicated that this approach does little toreduce contact-pad capacitance in this technology.To minimize the impact of contact-pad capacitance in our

technology, following [18], we first selected a 40- m-long by30- m-wide contact pad. This was the smallest size we felt thatwe could make these contact pads without adversely impactingcontact reliability.We then investigated the impact of fill strategy on the capaci-

tance of the contact pad. Fig. 2 shows the measured capacitance

Fig. 2. Measured capacitances of contact pads of the same area, but with dif-ferent fill. Only one version of the fixed-fill design was fabricated, and that de-sign had fill suppression around the periphery.

of several contact pads with this geometry as a function ofthe type of fill used under the contact pads. The dashed curvemarked with hollow circles and labeled “DV” correspondsto opening a hole in the passivation over a 40- m-long by30- m-wide contact pad and allowing the automated IBMroutines to place fill under and around the pad. The solid curvemarked with hollow circles corresponds to the same pad, exceptthat fill was suppressed around its periphery. The figure showsthat suppressing the fill around the pad significantly reducescontact-pad capacitance.The curve labeled “BONDPAD” corresponds to the same

contact pad, but uses fill automatically generated by IBM toreduce the capacitance of wire-bond pads. Using this special fillpattern further reduces the capacitance of the contact pad. Thefigure also shows that eliminating the fill around the peripheryreduces the capacitance of these contact pads even further.While the capacitance of contact pads using fill automatically

generated by IBM to reduce the capacitance of wire-bond padsis low, the actual placement of the fill depends on nearby struc-tures, potentially changing the capacitance of the pad. Since thecalibration does not correct for changing pad capacitances, wetook extra steps to ensure the uniformity of the contact-pad ca-pacitance over the die by replacing the automatically generatedIBM fill with a fixed fill pattern. This fixed fill pattern is similarto the actual automated fill patterns generated by the IBM fillsoftware. The capacitance of this contact pad is labeled “Fixedfill” in Fig. 2, and is nearly equal to that of the low-capacitanceIBM “BONDPAD” fill with fill suppression around the pad pe-riphery. However, it has the additional advantage that the fillpattern is independent of position on the die. For this reason,we used this fixed fill pattern under the contact pads that weused in our TRL calibration kit and test structures.

B. Contact-Pad Metallization

The IBM process we used employs aluminum for the top-metal level. However, obtaining reliable probe connections toaluminum contact pads, which oxidize quickly, is very chal-lenging, and can depend both on the type of probe employed,the number of previous contacts on the pad, and the skill of the


Fig. 3. Measured contact resistances.

operator. For example, [4] showed that errors due to contact-padrepeatability dominate over errors due to test-set drift over an8-h period. To remedy this, we developed a process based on[19] and [20] for gold plating the aluminum contact pads fabri-cated at IBM.Fig. 3 compares measurements of the total resistance of the

bias tee, probe, contact, line, and via of six offset shorts usinga standard microwave probe with beryllium-copper tips. Twoof the offset shorts had pads that were plated with gold, andfour of the offset shorts had bare aluminum pads. Fig. 3 showsclearly that the gold-plated pads improve the dc contact resis-tance significantly.Fig. 4(a) and (b) compares repeated measurements of the re-

flection coefficient of a short with and without gold-plated con-tact pads using the same probes and operator. Again, the im-provement in contact repeatability is evident. These observa-tions are consistent with those of [4], which also demonstratedthat contact-pad resistance is more difficult to control on alu-minum pads than on gold pads.Of course, we might have obtained better results on the bare

aluminum pads had we used probes designed specifically forthat purpose. Nevertheless, the improvement we obtained incontact repeatability by gold-plating our contact pads with ourprobes designed with beryllium-copper tips was fairly dramatic,and might expect benefits even with probes developed specifi-cally for aluminum pads as well. Finally, we noted a strong cor-relation between the RF repeatability of our probes and the dcrepeatability. This suggests that monitoring dc resistance duringmicrowave measurements as a tool for detecting poor contactrepeatability at microwave frequencies.

IV. REFERENCE IMPEDANCE

We mentioned above that we set the reference impedanceof the TRL calibration to 50 with the capacitance per unitlength of the line at low frequencies determined from the loadmethod of [8] and the measured propagation constant [7]. Thisprocedure requires a constant capacitance per unit length oftransmission line and a small , where is the conduc-tance per unit length of the transmission line. These conditionsare usually satisfied when low-loss dielectrics are used in the

Fig. 4. Comparison of measurements of offset shorts made with bare and gold-plated aluminum contact pads. (a) Repeatability of the reflection coefficient ofa short measured with gold-plated aluminum contacts. (b) Repeatability of thereflection coefficient of a short measured with standard aluminum contacts.

construction of the transmission lines, and previous compar-isons to calibrations on an impedance-standard substrate indi-cate that most transmission lines in a silicon interconnect stackmeet these criteria [5].We used an approximate SOLT probe-tip calibration per-

formed on a commercial calibration substrate and the calibrationcomparison method of [21] to verify, to the extent possible, theaccuracy of the reference impedance of our TRL calibration,and thus our assumption of constant capacitance per unitlength of transmission line and a small in our transmis-sion lines. This approach is similar to that employed in [22].As we cannot expect the SOLT calibration to be accurate athigh frequencies, and the TRL calibration fails at very lowfrequencies, we only expect this comparison between thetwo calibrations to work well only at moderate microwavefrequencies.Fig. 5 shows the reference impedance of the TRL calibra-

tion that we estimated from this approach. Most importantly, theimaginary part of the reference impedance appears linear. Thisis more likely due to an error in the inductance of the resistorsuggested by the manufacturer for use in the SOLT calibration,


Fig. 5. Reference impedance of our TRL calibration determined by comparisonto a probe-tip SOLT calibration.

than to loss in the dielectric material in the interconnect stack,which would typically manifest itself as a constant loss tangent,and thus, a constant offset in the imaginary component of theTRL reference impedance.The 0.5- offset in the low-frequency limit of the real part

of the reference impedance of the TRL calibration indicates anerror in setting the dc value of the capacitance in the TRLalgorithm [7], [8]. This offset is not surprising, given that wedid not have an on-wafer resistor with which to estimate thecapacitance per unit length of our transmission lines.Finally, the figure shows a weak resonance in the reference

impedance at about 35 GHz. It may be due to a problem withthe SOLT calibration, with the approximations involved in thecalibration comparison method itself [21], or a manifestation ofunexpected behavior in the dielectrics in the interconnect stackin which we built our transmission lines. Without further infor-mation, we are unable to identify the source of this behavior.

V. GROUND-PLANE DESIGN

The transmission lines we employed were fabricated on topof a lossy doped silicon substrate. Furthermore, ground planesin this technology are often meshed, raising the possibility thatfields might penetrate through them and into the silicon sub-strate, and potentially violate the key assumptions of constantcapacitance and zero conductance used to set the referenceimpedance to 50 . While we did not see evidence of this in thereference impedance we estimated in Section IV from the cali-bration-comparison method, we further searched for evidenceof field penetration through our ground planes by constructingtransmission lines with thinner ground planes and constructingtransmission lines with floating fill, and comparing them to ournominal transmission lines. Our intent was to try to detect anyissues with field penetration or fill by exaggerating them inthese additional transmission lines, and then comparing themto our nominal transmission lines.As indicated in Fig. 1, the IBM technology we used affords a

great deal of flexibility in the construction of the ground plane.We chose B3, the fourth level of metal from the top, for the nom-inal ground planes we used in our TRL calibrations. We choseB3 in part because the IBM design rules do not require this metal

level to be meshed over a 12- m width, and in part because thelower levels of metal and dielectrics are so thin that using B3for the ground does not significantly decrease the overall dielec-tric thickness. Furthermore, we meshed all of the lower levelsof metal available to us together, and attached them to B3 withperiodic vias, limiting field penetration through the metals tothe greatest extent possible. Thus, our nominal approach shouldminimize field penetration into the substrate, and best satisfythe conditions of constant capacitance and small conductancerequired by the calibration, while keeping the impedance of thelines high.To verify the conditions constant and are also

small when the ground planes are thinner, contain floating fill,or are meshed, we fabricated two additional TRL calibrationkits comprised of a thru-line and an additional 650- m-longline. The first calibration kit used the ground-plane designshown in Fig. 1, except that the grounded UA and UB stripswere replaced with floating islands. The second calibration kitused a meshed ground plane in the bottom three levels of metalM1, M2, and M3 in the interconnect stack. These three lowestmetal levels are approximately 140-nm thick, meshed, and tiedtogether with arrays of vias.We used the calibration-comparison method of [2] with

the recommended algorithm of [21] to compare these twotransmission lines to our nominal transmission line shown inFig. 1. This allowed us to estimate the characteristic impedanceof these transmission lines from the characteristic impedanceof our nominal lines calculated from the constant-capacitanceassumption of [7]. We then used the propagation constants ofthese lines estimated from the TRL calibrations to estimate thecapacitance and conductance per unit length of the lines shownin Fig. 6. The curve labeled “Floating UA and UB islands”correspond to the configuration of Fig. 1 with floating UA andUB islands instead of strips tied to ground with arrays of vias,and the curve labeled “M1–M3 meshed ground” correspondsto our meshed ground plane in the lowest three metal levelsM1, M2, and M3.

A. Capacitance and Conductance Per Unit Length

First, we note from that the measured capacitances per unitlength of the transmission lines in Fig. 6(a) compare well withthe fixed capacitance of 1.55 pF/cm we estimated for our nom-inal transmission lines shown in Fig. 1 with the load methodof [8] below 50 GHz. While we must treat the measurementsabove 50 GHz with some caution, as the approximations thatwe employed to estimate the parameters plotted in Fig. 6 beginto fail at higher frequencies [21] and the larger deviations above90 GHz may be due to instrumentation errors, these measure-ments are a good indication that the capacitances of all of thelines are roughly constant below 50 GHz.We also conclude from Fig. 6(a) that themeshed ground plane

fabricated on the lowest metal levels does not allow significantenergy to leak through the ground plane and into the lossy sil-icon beneath at frequencies below 50 GHz, which would be evi-denced by significant values of . This is extremely signif-icant from the point of view of calibration-kit design because theskin depth prevents field penetration through the ground planeat higher frequencies. Thus, we expect field penetration into the


Fig. 6. Comparison of measured and simulated transmission-line parameters.(a) Measured capacitance and conductance. (b) Simulated conductance.(c) Resistance and inductance.

lossy silicon substrate to be a low-frequency phenomenon, and alack of measured low-frequency field penetration indicates thatwe should not have field penetration at higher frequencies either.Fig. 6(b) shows results of HFSS simulations we performed

to further verify our conclusions regarding the behavior of. To increase accuracy, we substituted the fields from

our HFSS simulations into the perturbation expressions in [6,

eqs. (33)–(36)] for the capacitance , inductance , conduc-tance , and resistance per unit length of the rectangularwaveguide. These expressions are

(1)

where the integrals are performed over the cross section of theguide, is defined by , , and

.The solid curves in Fig. 6(b) show the total value of

we calculated for a microstrip line fabricated in this technologywith solid metal or meshed M1–M3 ground planes, while thedashed curves in Fig. 6(b) exclude the fields in the metals fromthe expressions in (1) and show only the component ofdue to the field that penetrates into the silicon dielectric. Thedashed lines show that the component of due to field pen-etration into the silicon is very small, confirming our measuredresults and giving us confidence in the reference-impedancetransformation we must apply in our TRL calibration.The solid lines also indicate that the total value of in-

cluding transverse currents in the metals is small as well. How-ever, the total values of in Fig. 6(b) should be treatedwithcaution, as we found it difficult to obtain good convergence forthe transverse currents in the metal, particularly when the metalwas meshed. Thus, while these results further support our mea-surements by indicating that the total values of are smallin these lines, it would not be appropriate to draw further conclu-sions regarding the actual magnitudes of in these lines.

B. Inductance and Resistance per Unit Length

Finally, Fig. 6(c) shows a modest increases in the inductanceand resistance per unit length of our two transmission lines

when compared to the nominal design of Fig. 1 below 50 GHz,where the frequencies are low enough that we can have con-fidence in the measured estimates in Fig. 6. However, thesemodest increases in and are not particularly significantfrom a calibration point of view, as they are estimated in ourcalibration procedure from our measured propagation constant[7]. In fact, the modest increase in the resistance per unitlength when the metal is meshed gives us greater confidencethat should not increase greatly when the metal groundplane is meshed.Thus, we see that, while we choose a very conservative

approach to ground-plane design that backs a solid metal B3ground with a stack of meshed grounds underneath to minimizefield penetration into the silicon substrate, our results indicatethat even designs with only a few meshed metal levels in theground should prevent significant field penetration into thesilicon substrate.


Finally, due to the inherent errors in our estimates of thetransmission-line parameters of the transmission lines em-ploying floating islands and M1–M3 meshed ground planesoutlined in [21], it is difficult to draw conclusions about thebehavior of these transmission lines above 80 GHz from thedata plotted in Fig. 6. Nevertheless, the data below 50 GHz arequite comforting, and a good indication that TRL calibrationkits based on any of these lines should perform well over theentire band.

VI. TRANSISTOR MEASUREMENTS

We applied our calibration to the characterization of a siliconnFET power transistor with 40 fingers of width 770 nm and aminimum length of 40 nm designed for use at millimeter-wavefrequencies. The gate was contacted on a single side, while thesource and drain both exit on the opposite side of the gate inorder to reduce parasitic capacitance. The sources connect di-rectly to the ground plane. The drains are tapered while movingup through the metal stack to make contact with the signal lineof the microstrip feeds.

A. Coupling Corrections

We first investigated the impact of the coupling correctionsinvestigated in [17] because that reference showed significantimprovements in millimeter-wave transistor scattering-pa-rameter measurements of heterojunction bipolar transistorsdesigned for use at terahertz frequencies. Fig. 7 compares themagnitude and phase of scattering-parameter measurementsof a power transistor we designed for use at millimeter-wavefrequencies with and without coupling corrections. Thesemeasurements were corrected to the initial reference planeof the TRL calibration, and we did not attempt to move thatreference plane to the transistor contacts. The figure shows thatthe differences are very much smaller than those observed in[17]. This could be due to the larger size of the transistors wedesigned for this IBM technology, or to differences in contactpads, access lines, or probes.

B. Uncertainties

We also performed an uncertainty analysis to assess theoverall accuracy of our measurement and calibration proce-dures. We used the orthogonal-distance regression algorithmsof ODRPACK [23], as implemented in [13] and [14], to esti-mate the uncertainty in our TRL calibration from the lack offit of the overdetermined measurements of the TRL calibrationstandards to the VNA calibration model. To capture drift in theVNA and the cables, we included calibration measurementsperformed both before and after the transistor measurements.We added estimates of the uncertainty in the crosstalk correc-

tions to these errors. As we have found that corrections due tocrosstalk are unreliable, we estimated the standard uncertaintyin our crosstalk corrections as equal to half of the values of thecorrections themselves. We also assumed a coverage factor oftwo for the uncertainty in the crosstalk terms. We then propa-gated these errors through the de-embedding procedure to as-sess its impact on the transistor parameters.Fig. 8 shows measurements of the gain of our transistor and

95% confidence intervals. As we did not attenuate the signals

Fig. 7. Comparison of transistor scattering parameters with and without cou-pling corrections. (a) Magnitude comparison. (b) Phase comparison.

from the vector network analyzer for these measurements, theresponse of our transistors was not quite linear, which may ex-plain in part why some of the variation in ourmeasurementsmayseem somewhat large compared to our 95% confidence inter-vals. For example, the uncertainty analysis does not account fora jump in power level at 67 GHz from approximately 17 dBmto about 5 dBm where the test-set configuration changes auto-matically inside our vector network analyzer. Nevertheless, our95% confidence intervals do seem representative of our actualuncertainties.

VII. FREQUENCY LIMITATIONS

The lateral dimensions of the transmission lines we used inour calibration kits are small enough, and the dielectrics areof high-enough quality, that it seemed possible that our trans-mission lines might be useful not just for calibrations at mil-limeter-wave frequencies, but also in the sub-millimeter-waveregion. Fig. 9 shows the measured effective dielectric constant,which is a normalized form of the propagation constant [6],and the attenuation of transmission lines fabricated in the IBMtechnology with a 4- m-wide center conductor and the samemeshed M1–M3 ground-plane design we discussed earlier.


Fig. 8. Measurements of transistor gain with 95% confidence limits.

Fig. 9. Comparison of measured propagation constants and attenuation.(a) Effective dielectric constant. (b) Attenuation.

This curve is dashed in the figure and labeled “IBM 45 nmSOI.” The contact pads on this wafer were also gold plated. Wecompared these measurements to measurements performed on

Fig. 10. Magnitude and phase of the scattering parameters of two Beattystandards.

22- m-wide gold microstrip lines fabricated on a 8- m-thickbisbenzocyclobutene-based (BCB) monomers film designedfor measurements at terahertz frequencies [17], which arelabeled “THz BCB.”The propagation constants determined by TRL calibrations

in the two technologies are remarkably similar. While the loss(as reflected by the imaginary part of the effective dielectricconstant) and real part of the effective dielectric constant of thetransmission lines in the IBM technology are greater than thoseof the BCB-based microstrip lines, they were not lossy enoughto prevent TRL calibration from failing at these sub-millimeterwavelengths.More importantly, at high frequencies the effective dielectric

constant is smooth and well behaved, and does not display res-onances of other characteristics that might indicate radiation,multimode propagation, or other problems in the transmissionlines at these frequencies. While the attenuation of our silicontransmission lines in Fig. 9(b) is much higher than that of theterahertz lines, they are both still well behaved below 325 GHz,and reasonably well behaved in the 325–500-GHz band. Fur-thermore, we note that the most significant noise in the measure-ments between 325–400 GHz are present in both the terahertzBCB and the IBM 45-nm SOI measurements, an indication thatthe root cause of this noise is more likely due to instrumentationproblems than the calibration artifacts.Fig. 10 shows measurements of two Beatty standards that are

a half wavelength long at about 420 GHz. Here again, the mea-surements, while not as accurate at submillimeter wavelengthsas in the millimeter-wave region, are quite well behaved below325 GHz, and reasonably well behaved in the 325–500-GHzband.

A. Multiline Calibrations

Single-line TRL calibrations typically fail whenever thelength of the transmission line reaches a multiple of ahalf-wavelength long. This happens because the scatteringparameters of the line in the calibration kit cannot be distin-guished from the scattering parameters of the thru when the line


Fig. 11. Comparison of reflection coefficients of a Beatty line calibrated witha thru, reflect, and 1-mm line, and with a thru, reflect, and all lines.

is a multiple of a half-wavelength longer. However, this is nottrue if the transmission lines are so lossy that the attenuation ofthe line is significantly greater than the attenuation of the thrudue to the line’s additional length.We performed a short investigation to see if the high loss of

our silicon transmission lines could be actually used to reducethe number of transmission lines in our calibration kit, and thusreduce its size. Fig. 11 shows a typical comparison of reflectioncoefficients of one of our Beatty lines measured with a TRL cal-ibration kit using a thru, reflect, and all of the lines, and a thru,reflect, and 1-mm line. The arrows at the bottom of the graphindicate the locations where the 1-mm line is an integer mul-tiple of a half-wavelength long. It is clear from the figure thatthe calibration using only the 1-mm line fails these locations,indicating that the loss in our transmission lines fabricated inthe IBM technology was not large enough to allow us to accu-rately calibrate our vector network analyzer when the line was amultiple of a half-wavelength longer that the thru line. Thus, weconclude that obtaining accurate TRL calibrations in the trans-mission lines we used at sub-millimeter wavelengths will re-quire multiline calibrations.

VIII. CONCLUSION

We have shown that the TRL calibration algorithm providesan accurate alternative to lumped-element calibrations that iswell suited to measurements at millimeter and sub-millimeterwavelengths. We investigated possible sources of error, in-cluding field penetration through meshed ground planes, metalcontact repeatability, and contact-pad capacitance. We showedthat contact repeatability can be improved by plating the alu-minum pads with gold and developed a pad design that reducesthe magnitude and variation of contact-pad capacitances. Fi-nally, we applied the approach to transistor characterizationand presented uncertainties for those measurements.

ACKNOWLEDGMENT

This work is a publication of the National Institute of Stan-dards and Technology, an agency of the U.S. government, and is

not subject to U.S. copyright. The views, opinions, and/or find-ings contained in this article are those of the author and shouldnot be interpreted as representing the official views or policies,either expressed or implied, of either the Defense Advanced Re-search Projects Agency or the Department of Defense.

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[3] A. Rumiantsev, P. Sakalas, N. Derrier, D. Celi, and M. Schroter, “Influ-ence of probe tip calibration on measurement accuracy of small-signalparameters of advanced BiCMOS HBTs,” in IEEE Bipolar/BiCMOSCircuits Technol. Meeting, Sep. 2011, pp. 203–206.

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[5] A. Rumiantsev, P. L. Corson, S. L. Sweeney, and U. Arz, “Applying thecalibration comparison technique for verification of transmission linestandards on silicon up to 110 GHz,” in Automat. RF Techn. GroupConf. Dig., Dec. 2009, vol. 73, pp. 1–6.

[6] R. B. Marks and D. F. Williams, “A general waveguide circuit theory,”J. Res. Nat. Inst. Standards Technol., vol. 97, no. 5, pp. 533–562, Sep.1992.

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[10] R. B. Marks and D. F. Williams, “Verification of commercial probe-tipcalibrations,” in ARFTG Conf. Dig., Dec. 1993, vol. 42, pp. 37–44.

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[14] D. F. Williams, C. M. Wang, and U. Arz, “An optimal multiline TRLcalibration algorithm,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun.2003, vol. 3, pp. 1819–1822.

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[23] P. T. Boggs, R. H. Byrd, J. E. Rogers, and R. B. Schnabel, User’s Ref-erence Guide for ODRPACK Version 2.01 Software for Weighted Or-thogonal Distance Regression. Boulder, CO, USA: NIST, 1992.

Dylan F. Williams (S’82–M’86–SM’90–F’02)received the Ph.D. degree in electrical engineeringfrom the University of California at Berkeley,Berkeley, CA, USA, in 1986.In 1989, he joined the Electromagnetic Fields

Division, National Institute of Standards and Tech-nology, Boulder, CO, USA, where he developselectrical waveform and microwave metrology. Hehas authored or coauthored over 80 technical papers.Dr. Williams was co-editor-in-chief of the IEEE

TRANSACTIONS ON MICROWAVE THEORY AND

TECHNIQUES (2006–2010). He is currently the executive editor of the IEEETRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY. He was therecipient of the Department of Commerce Bronze and Silver Medals, theAstin Measurement Science Award, two Electrical Engineering Laboratory’sOutstanding Paper Awards, three Automatic RF Techniques Group (ARFTG)Best Paper Awards, the ARFTG Automated Measurements Technology Award,the IEEE Morris E. Leeds Award, the 2011 European Microwave Prize, and the2013 IEEE Joseph F. Keithley Award.

Phillip Corson (M’06) received the B.S. degreein mathematics from the University of Vermont,Burlington, VT, USA, in 1994.In 1980, he joined IBM Microelectronics, Essex

Junction, VT, USA, where he was involved withadvanced bipolar memory development. His projectsinclude design and characterization of bipolar andCMOS high-performance SRAM and DRAM prod-ucts, SRAM product engineering, modeling ionizingradiation and SER, development of an enhanced ITinfrastructure, AIX system administration and soft-

ware development, and team lead for compact model device characterization.He is currently an Advisory Engineer involved in passive device modeling.

Jahnavi Sharma (S’10) received the Bachelors andMasters degrees in electrical engineering from the In-dian Institute of Technology, Madras, India, in 2009,and is currently working toward the Ph.D. degree atColumbia University, New York, NY, USA.In the summer of 2007, she performed a

three-month internship with the MicroelectronicsCenter, Indian Institute of Technology, Kharagpur,India. Her research interests include sub-mil-limeter-wave circuits in CMOS and exploration ofassociated applications.

Harish Krishnaswamy (S’04–M’09) received theB.Tech. degree in electrical engineering from theIndian Institute of Technology, Madras, India, in2001, and the M.S. and Ph.D. degrees in electricalengineering from the University of Southern Cali-fornia (USC), Los Angeles, CA, USA, in 2003 and2009, respectively.In 2009, he joined the Electrical Engineering

Department, Columbia University, New York,NY, USA, as an Assistant Professor. His researchinterests broadly span integrated devices, circuits,

and systems for a variety of RF and millimeter-wave applications. His currentresearch efforts are focused on silicon-based millimeter-wave power amplifiers,

sub-millimeter-wave circuits and systems, and reconfigurable broadband RFtransceivers for cognitive and software-defined radio.Dr. Krishnaswamy serves as a member of the Technical Program Committee

(TPC) of several conferences, including the IEEE RFIC Symposium and IEEEVLSI-D. He was the recipient of the IEEE International Solid State CircuitsConference (ISSCC) Lewis Winner Award for Outstanding Paper in 2007, theBest Thesis in Experimental Research Award from the USC Viterbi School ofEngineering in 2009, and the Defense Advanced Projects Agency Young Fac-ulty Award in 2011.

Wei Tai (S’08–M’13) received the B.S. degree inelectrical engineering from National Taiwan Univer-sity, Taipei, Taiwan, in 2004, and the Ph.D. degree inelectrical and computer engineering from CarnegieMellon University, Pittsburgh, PA, USA, in 2012.In 2009, he was an Intern with the Intel Corpo-

ration, Hillsboro, OR, USA, where he was involvedin the design of 4G/WLAN CMOS power amplifierswith dynamic power control. He is currently a SeniorEngineer with Qualcomm Technologies Inc., SanDiego, CA, USA, where he develops multi-mode

3G/4G power amplifiers. His research is focused on RF and millimeter-waveintegrated circuits and power amplifiers.Dr. Tai was the recipient of the 2011 Analog Devices Outstanding Student

Designer Award.

Zacharias George, photograph and biography not available at time ofpublication.

David Ricketts, photograph and biography not available at time of publication.

Paul Watson, photograph and biography not available at time of publication.

Eric Dacquay (S’07–M’08), photograph and biography not available at time ofpublication.

Sorin P. Voinigescu (S’91–M’95–SM’02) receivedthe M.Sc. degree in electronics from the PolytechnicInstitute of Bucharest, Romania, in 1984, and thePh.D. degree in electrical and computer engineeringfrom the University of Toronto, Toronto, ON,Canada, in 1994.From 1994 to 2002, he was initially with Nortel

Networks and then with Quake Technologies,Ottawa, ON, Canada, where he was responsiblefor projects in high-frequency characterization andstatistical scalable compact model development for

Si, SiGe, and III–V devices. He later conducted research on wireless andoptical fiber building blocks and transceivers in these technologies. In 2002,he joined the University of Toronto, where he is currently a Full Professor.From 2008 to 2009, he spent a sabbatical year with Fujitsu Laboratories ofAmerica, Sunnyvale, CA, USA. His research and teaching interests focus onnanoscale semiconductor devices and their application in integrated circuits atfrequencies beyond 300 GHz.Dr. Voinigescu is a member of the ITRSRF/AMSCommittee and of the Tech-

nical Program Committees (TPCs) of the IEEE CSICS and BCTM. He was therecipient of Nortel Network’s President Award for Innovation in 1996. He was acorecipient of the Best Paper Award of the 2001 IEEE CICC and the 2005 IEEECSICS. He was the recipient of the Beatrice Winner Award of the 2008 IEEEISSCC. His students have been the recipient of Student Paper Awards of the2004 VLSI Circuits Symposium, 2006 SiRF Meeting, RFIC Symposium andBCTM, and 2008 and 2012 IEEE Microwave Theory and Techniques Society(IEEE MTT-S) International Microwave Symposium.

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