ieee transactions on industrial electronics, vol. 67, …

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 10, OCTOBER 2020 8363

Soft-Switching Bidirectional Buck/BoostConverter With a Lossless Passive Snubber

Mohammad Reza Mohammadi , Hosein Farzanehfard , Member, IEEE,and Ehsan Adib , Member, IEEE

Abstract—This article introduces a new lossless passivesnubber for the bidirectional buck/boost converter. The pro-posed snubber comprises a low number of passive com-ponents which jointly contribute to achieve soft switchingcondition at both the buck and boost operations of theconverter. Without using the auxiliary switch, soft switchingcondition is ensured over a wide load range with a relativelylow circulating current. Also, there is no need for any com-plex control method to diminish circulating current at lightloads. Consequently, by using a simple auxiliary circuit andthe conventional control methods, excellent efficiency isacquired over a wide load range. The proposed topologyis analyzed in detail and to confirm the theoretical analysis,the experimental results of a 500 W–100 kHz prototype forboth the boost and buck modes in full-load and 20% offull-load are presented.

Index Terms—Bidirectional buck/boost converter(BBBC), soft-switching technique, snubbers.

I. INTRODUCTION

IN RECENT decades, the importance of bidirectional dc–dc

converters has greatly increased, largely due to the advent

and rapid growth of renewable energies and hybrid/electrical

vehicles. In these applications, bidirectional dc–dc converters

are generally used to manage the charge and discharge of the

energy storage devices, and also, to match the different voltage

levels of the energy storage devices and dc bus [1], [2]. The bidi-

rectional buck/boost converter (BBBC) is considered as the basic

bidirectional converter, and it is used in many applications [1],

[2]. This converter composes of the two well-known buck and

boost converters, and in each operation mode, it has the intrinsic

characteristics of the basis converter. The primary issue of BBBC

is the slow body diodes of the main switches which have the

role of the converter rectifying diodes. This issue results in

severe switching losses due to the excessive reverse recovery

time of the slow body diode of the conventional power switches.

Manuscript received December 23, 2018; revised May 4, 2019 andJuly 8, 2019; accepted October 4, 2019. Date of publication October25, 2019; date of current version June 3, 2020. (Corresponding author:Hosein Farzanehfard.)

M. R. Mohammadi is with the Department of Electrical Engineering,Najafabad Branch, Islamic Azad University, Najafabad 85141-43131,Iran (e-mail: [email protected]).

H. Farzanehfard and E. Adib are with the Department of Electricaland Computer Engineering, Isfahan University of Technology, Isfahan84156-83111, Iran (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this article are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2019.2947850

Hence, high-frequency switching of BBBC to increase the power

density is not provided. To achieve excellent efficiency in the

high-frequency operation of BBBC, employing soft switching

methods is inevitable [2]–[31].

In [2]–[23], soft switching condition is obtained for BBBC

using auxiliary circuits with active switch. Based on the soft

switching method used, these converters can be categorized into

zero voltage transition (ZVT) BBBCs [2]–[16], zero current

transition (ZCT) BBBCs [17], [18], zero-voltage zero-current

switching (ZVZCS) BBBCs [19], [20], and active clamping

BBBCs [21]–[23]. In ZVT and active clamping BBBCs, zero

voltage switching (ZVS) of the main switches, and in ZCT

BBBCs, zero current switching (ZCS) of the main switches is

provided. In ZVZCS BBBCs, both the ZVS and ZCS condition

are provided for the main switches. Nevertheless, in the ZVT

and ZVZCS BBBCs, generally, two auxiliary switches are uti-

lized. Besides, in ZCT and active clamping BBBCs at least one

auxiliary switch is required. Extra switches require additional

heatsinks, related gate-drive circuits, and timing circuits which

increase the overall converter cost and complexity and reduce

the power density. The design of the auxiliary gate drive circuits

is more challenging when the source terminal of the auxiliary

switch is not grounded, and the floating gate drive circuit is

required. The floating gate drive circuit is required in [9]–[14]

for two auxiliary switches, and in [2]–[8], [17]–[23] for one

auxiliary switch. Also, usually capacitive turn-ON loss exists in

all solutions at least for the auxiliary switch.

In soft switching BBBCs of [24]–[30], no auxiliary switch

is utilized, and passive elements merely achieve soft switching.

In [24]–[28], the desirable features such as ZVS condition and

elimination of the diode reverse recovery losses are achieved.

However, in these converters, the root-mean-square value of the

main switches current is almost constant over the entire load

variations. Besides, a substantial and constant circulating current

always exists in the converter. The mentioned problems signifi-

cantly reduce efficiency, particularly at light-loads. To diminish

the circulating current at light loads, it is required to increase

the switching frequency when the output power is reduced [28].

However, variable frequency control methods increase the filter

size and complexity. In [29], [30], soft switching condition is

obtained using the passive snubber circuits. In these converters,

the problems of [24]–[28] do not exist. However, in [29], soft

switching is provided only at turn-ON instants, and the main

switches turn-OFF under hard switching. Besides, in [30], large

additional voltage stress is applied on the main switches.

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8364 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 10, OCTOBER 2020

Fig. 1. (a) Proposed BBBC with lossless passive snubber. (b) Pro-posed converter with the coupled inductors equivalent circuit.

In this article, a lossless passive snubber is proposed which

provides soft switching condition in BBBC without the auxiliary

switch. Various lossless passive snubbers are proposed for the

basic unidirectional converters [31]–[34]. However, these snub-

bers can provide soft switching condition only in one power flow

direction (boost mode or buck mode) of BBBC. To obtain soft

switching condition in BBBC using these snubbers, two inde-

pendent cells should be applied for the buck and boost modes

of BBBC. This approach not only increases the complexity of

the converter but also, each cell may interfere with the correct

operation of the other cell. The proposed snubber circuit uses

minimum passive elements to provide soft switching in both the

buck and boost operations. When no auxiliary switch is used, the

related heatsinks, gate drive, and timing circuits of the auxiliary

switches are also eliminated. Hence, the reliability and power

density increase and the converter cost and complexity would

decrease. In the proposed converter, soft switching condition

is secured for all the semiconductor elements. Also, the pro-

posed converter benefits from relatively low circulating current

which proportionately diminishes as the output power decreases.

Consequently, excellent efficiency is achieved over a wide load

range, without using the complex variable frequency control

methods.

First, in Section II, the structure and operation of the proposed

converter are discussed. Next, Section III describes the design

considerations. In Section IV, the experimental results of a

500 W–100 kHz prototype for both the boost and buck modes in

full load and 20% of full load are presented. Finally, Section V

concludes this article.

II. CIRCUIT STRUCTURE AND OPERATION

The structure of the proposed converter is depicted in Fig. 1(a).

The proposed snubber is made up of a snubber capacitor CS , a

snubber inductor LS , a clamp capacitor CC , a coupled inductor

L2, which is coupled with the main inductor L1, and three

auxiliary diodes D1, D2, and D3. As illustrated in Fig. 1(b),

the coupled inductors L1 and L2 can be modeled as an ideal

transformer with turn ratio n [=k−1(L2/L1)^0.5], magnetizing in-

ductance Lm (= L1) and leakage inductor Llk [= (1− k2)L2].This way, the inductor Lm acts as the converter filter inductor.

The converter operation involves eight operating stages in each

buck and boost modes of operation. For the converter operation

analysis, the following assumptions are made

1) The converter operates at steady state condition, and the

elements are ideal.

Lm and CC are large, and iLm and VCc are assumed constant

in a switching cycle (iLm = ILm)

A. Boost Mode of Operation

In this mode, S1 is controlled, S2 is OFF, and the S2 body diode

is the converter rectifying diode. Hence, the power flow is from

VL to VH . The equivalent circuits of eight operating stages in the

boost mode and the related theoretical waveforms are illustrated

in Figs. 2 and 3, respectively. Before the first stage, it is assumed

that the boost converter is at its conventional stage when the main

switch is OFF, and ILm transfers toVH through the S2 body diode

(as can be seen in the equivalent circuit of Fig. 2(h)).

Stage 1 [t0–t1]: At t0, S1 is turned ON. By turning S1 ON, the

voltage −VH is placed across the LS , and so, LS current begins

to decrease as follows:

iLS = ILm −VH

LS

(t− t0). (1)

In this stage, the voltage VL is placed across the primary side

of the ideal transformer (vP = VL) and therefore, the secondary

side voltage is nVL (vS = nVL). Hence, the voltage VCc + nVL

is applied across the Llk, and its current (iD3) increases linearly

as follows:

iD3 =VCc + nVL

Llk

(t− t0). (2)

The current iD3 exits from the dotted terminal of the trans-

former secondary side, and thus, the current niD3 enters the

dotted terminal of the transformer primary side. Consequently,

from (1) and (2) and using the Kirchhoff current law, the current

equations of the main switch S1 and the S2 body diode are derived

as

iS1 =

(

VH

LS

+n(VCc + nVL)

Llk

)

(t− t0) (3)

−iS2 = ILm −

(

VH

LS

+VCc + nVL

Llk

)

(t− t0). (4)

According to (3), iS1 increases linearly from zero; as a result,

S1 turn-ON is under ZCS. Based on (4), the current of the S2 body

diode reduces linearly to zero with a defined slop, and then, the

reverse recovery time of the S2 body diode begins. Due to the

defined rate of the diode current reduction, the reverse recovery

time of the S2 body diode is under control. At t1, the current of

iD3 is defined as I0.

Stage 2 [t1–t2]: At t1, a resonance starts between CS , LS ,

and Llk. During this resonance, the CS voltage discharges to

zero. Hence, the voltage of the S2 body diode increases slowly

which offers a remarkable reduction of the S2 body diode volt-

age/current overlap. This point and the defined rate of diode

current reduction would reduce the reverse recovery losses of


MOHAMMADI et al.: SOFT-SWITCHING BBBC WITH A LOSSLESS PASSIVE SNUBBER 8365

Fig. 2. Operating stages of the proposed converter in boost operation. (a) Stage 1. (b) Stage 2. (c) Stage 3. (d) Stage 4. (e) Stage 5. (f) Stage 6.(g) Stage 7. (h) Stage 8.

Fig. 3. Theoretical waveforms of the converter in boost operation.

S2 body diode. At t2, the currents iD2 and iD3 are defined as I1and I2, respectively.

Stage 3 [t2–t3]: At t2, CS is completely discharged, and so,

diode D1 turns ON under ZVS. In this condition, the voltage

–(VH − nVL) applies across the Llk, and its current (iD3)linearly decreases to zero. Thus, at the end of this stage, diode D3

would turn-OFF under ZCS condition. In this stage, the current

equation of iD3 is

iD3 = I2 −VH − nVL

Llk

(t− t0). (5)

At t3, iD2 is defined as I3.

Stage 4 [t3–t4]: In this stage, the voltage VCc applies across

the LS , and so the current of LS linearly reduces to zero. Hence,

at the end of this stage, diodes D1 and D2 would turn-OFF under

ZCS.

Stage 5 [t4–t5]: The boost converter is at its conventional

stage when the main switch is ON.

Stage 6 [t5–t6]: At t5, S1 is turned OFF. Then, the capacitor

CS begins to charge by ILm. As a result, the voltage of the main

switch S1 increases slowly, and S1 is turned OFF under ZVS.

Stage 7 [t6–t7]: At t6, the CS voltage reaches VH + VCc and

so, the S2 body diode and D2 turn-ON under ZVS. Consequently,

ILm flows to VH through the path of D1, D2, CC , and S2 body

diode. In this condition, the voltage VCc applies across the LS

and its current increases linearly to ILm. At the same time, D1

and D2 currents linearly decline to zero and hence, D1 and D2

turn-OFF under ZCS. The equation for iD1 or iD2 is

iD1 = iD2 = ILm −VCc

LS

(t− t6). (6)

Stage 8 [t7–t0 + T]: The boost converter is at its conventional

stage when the main switch is OFF.

B. Buck Mode of Operation

In this mode, S2 is controlled, S1 remains OFF, and the S1body diode is the converter rectifying diode. In this condition,

power transfers from VH to VL. The equivalent circuits of eight

operating stages in the buck mode and the related theoretical

waveforms are illustrated in Figs. 4 and 5, respectively. Before

the first stage, it is assumed that the buck converter is at its

conventional stage when the main switch is OFF, and ILm is

flowing to VL through the S1 body diode [as can be seen in the

equivalent circuit of Fig. 4(h)].

Stage 1 [t0–t1]: This stage begins by turning S2 ON. When

S1 is turned ON, the voltage −VH is placed across LS , and its

current increases linearly as follows:

iLS = −VH

LS

(t− t0). (7)

In this stage, the voltages of the primary and secondary sides

of the ideal transformer are VL and nVL, respectively (vP = VL,

vS = nVL). Thus, VCc + nVL places across the Llk, and its



Fig. 4. Operating stages of the proposed converter in buck operation. (a) Stage 1. (b) Stage 2. (c) Stage 3. (d) Stage 4. (e) Stage 5. (f) Stage 6.(g) Stage 7. (h) Stage 8.

Fig. 5. Theoretical waveforms of the converter in buck operation.

current (iD3) increases linearly as follows:

iD3 =VCc + nVL

Llk

(t− t0). (8)

From (7) and (8), the current equation of S2 would be

iS2 =

(

VH

LS

+VCc + nVL

Llk

)

(t− t0). (9)

Based on (9), the S1 current increases linearly from zero, and

so, S1 is turned ON under ZCS. In this stage, the current iD3

exits from the dotted terminal of the transformer secondary side,

as a result, the current niD3 enters the dotted terminal of the

transformer primary side. From (7) and (8), the current equation

of the S1 body diode is as follows:

−iS1 = ILm −

(

VH

LS

+n(VCc + nVL)

Llk

)

(t− t0). (10)

According to (10), the current of the S1 body diode reduces

to zero with a defined rate, hence, the reverse recovery time of

S1 is under control. At t1, iD3 is defined as I0.

Stage 2 [t1–t2]: At t1, a resonance starts between CS , LS ,

and Llk. Among this resonance, the capacitor CS is charged to

VCc + VH . Hence, the voltage of S1 body diode slowly increases

which helps to reduce the reverse recovery losses. The values of

iD1 and iD3 at t2 are defined as I1 and I2, respectively.

Stage 3 [t2–t3]: This stage begins when CS is charged to

VCc + VH , and diode D2 turns ON under ZVS. Thus, −VCc is

placed across LS and its current linearly declines. At the same

time, the voltage –[n(VH + VCc − VL)− VCc] is applied across

the Llk, and its current (iD3) linearly reduces as follows:

iD3 = I2 −n(VH + VCc − VL)− VCc

Llk

(t− t2). (11)

Hence, the current equation for D1 and D2 are derived as

iD1 = iD2 = I1 −

(

n2(VH + VCc − VL)− nVCc

Llk

+VCc

LS

)

(t− t2). (12)

According to (12), iD1 and iD2 decline to zero, and the diodes

D1 and D2 turns OFF under ZCS condition. At t3, iD3 is defined

as I3.

Stage 4 [t3–t4]: In this stage, the D3 current reduces to zero,

and the diode D3 would be turned OFF under ZCS.

Stage 5 [t4–t5]: The buck converter is at its conventional stage

when the main switch is ON.

Stage 6 [t5–t6]: At t5, S2 is turned OFF, and the capacitor CS

discharges by the magnetizing inductor current (ILM ). Since the

voltages of VH and VCc are assumed constant, the voltage of S2increases slowly, and so, S2 is turned OFF is under ZVS. At the

end of this stage, CS discharges completely.



TABLE IVOLTAGE STRESS OF THE SEMICONDUCTOR ELEMENTS

Note: VCc = n(VH − VL)

Stage 7 [t6–t7]: At t6, the voltage of CS reaches zero, and

so, the diodes D1 and S1 body diode would turn-ON under ZVS.

In this condition, the voltage VCc places across the LS . Hence

iLS decreases to zero, and the diodes D1 and D2 would turn OFF

under ZCS. The equation of iD1 or iD2 would be

iD1 = iD2 = ILm −VCc

LS

(t− t6). (13)

Stage 8 [t7–t0 + T]: The buck converter is at its conventional

stage when the main switch is OFF.

III. DESIGN CONSIDERATIONS

In this section, the elements of the proposed snubber are de-

signed to ascertain the proper operation of the proposed snubber.

The snubber capacitor CS provides the ZVS condition of the

main switches at the turn-OFF and is designed as follows [35]:

CS > CS_min =iSW tf

2vSW

(14)

where iSW is the value of switch current before turn-OFF instant,

vSW is the final value of switch voltage after turn-OFF, and tf is

the switch current fall time.

In the equivalent model of the coupled inductors, Lm is the

main inductor of the converter and is designed as the main

inductor of the regular boost or buck converters. Besides, since

L1 = Lm, the value of L1 is obtained. The coupled inductors

are utilized to reset the circulating current through the diode

D3, especially in the buck operation. Hence, the turn ratio of n

should be designed so that the circulating current resets to zero

in stage 3 of both buck and boost operations. Hence, from (5)

and (12), the following conditions must be satisfied:

VH > nVL (15)

n(VH + VCc − VL) > VCc. (16)

The value of VCc in both the buck and boost operations is

estimated as

VCc = n(VH − VL). (17)

Using (17), if n > 0, the condition of (16) is always met.

Hence, only the condition of (15) must be satisfied. On the other

hand, the value of the turns ratio n is effective in the additional

voltage stress on the main switches. Table I presents the voltage

stress of the proposed converter semiconductor elements. As

seen, the additional voltage stress on the main switches is equal

to VCc. To limit this additional voltage stress to below 20% of

VH , and from (17), the following condition should satisfy:

n < nmax =0.2VH

VH − VL

. (18)

Consequently, if n is selected according to (18), the voltage

stress of the main switches limit to below 1.2VH . Besides, the

condition of (15) is satisfied, and the proper operation of the

proposed snubber is ensured.

In the proposed converter, the current reduction rate of the

rectifying diodes (di/dt) at turn-OFF instant is determined by the

auxiliary circuit. From (4), (10), and (17), di/dt in boost and buck

operations are derived as (19) and (20), respectively,

|di

dt| =

VH

LS

+nVH

Llk

(19)

|di

dt| =

VH

LS

+n2VH

Llk

. (20)

Based on (19) and (20), to reduce the value of di/dt, the

inductor LS should be selected large enough. On the other hand,

in operating stage 7 of boost and buck operations, it must be

secured that the current of the auxiliary diodes D1 and D2 (iD1

and iD2) reach zero. Hence, by neglecting the duration time of

stage 6, the duration time of stage 7 must be less than the main

switch OFF time [(1 − D)T]. Hence, from (6) and (13), LS is

designed as follows:

LS < LS_max =n(VH − VL)(1−D)

ILmf(21)

where f is the converter switching frequency ( f = 1/T). Note, in

(21), ILm should be calculated for the worst-case condition when

the converter operates in full-load and maximum duty cycle.

The capacitor CC is the clamp capacitor and absorbs the extra

energy of the circuit. Hence, the value of CC should be selected

large enough to make sure that the voltage ripple of CC (∆VCc)is limited. In boost operation, CC is discharged in stage 1 and

is charged in stages 2, 3, 4, and 7. Hence, for stage 1, |∆VCc| in

boost operation is obtained as follows:

|∆VCc| =1

Cc

∫ t1

t0

iCcdt. (22)

In the first stage, iCc = −iD3. Hence, from (2), |∆VCc| in

boost operation is derived as follows:

|∆VCc| =(ILm)2Llk

CC(VCc + nVL). (23)

To limit |∆VCc| in boost operation to less than 2% of VCc,

from (17) and (23), the value of CC is designed as follows:

CC > CCmin1 =50(ILm)2Llk

n2VH(VH − VL). (24)

Similarly, in buck operation, CC is discharged in stages 1, 2,

3, and 4, and is charged in stages 6 and 7. Hence, by omitting the

duration time of stage 6, from (13) and (17), and by performing

the same procedure done in the boost operation, the value of CC

is as follows:

CC > CCmin2 =50(ILm)2LS

(VH − VL)2 . (25)



Fig. 6. Experimental results at full load (500 W) (time scale is 1 µs/div) in (a) boost operation and (b) buck operation.

Fig. 7. Experimental results at 20% of full load (100 W) (time scale is 1 µs/div) in (a) boost operation and (b) buck operation.

Consequently, if CC is selected larger than the maxi-

mum value of CCmin1 and CCmin2, the voltage ripple of

CC (|∆VCc|) is limited at less than 2% of VCc in both boost

and buck operations.

Finally, it should be noted that in many applications, the

low-voltage and high-voltage sources of the BBCs are batter-

ies and dc-bus, respectively. However, to implement the BBC

individually, two additional capacitors on the low-voltage and

high-voltage sides are necessary. The capacitors of high-voltage

and low-voltage sides are designed like the output capacitors of

the conventional boost and buck converters, respectively [35].

IV. EXPERIMENTAL RESULTS

To verify the proper operation of the proposed snubber, a

laboratory prototype of a BBBC with the proposed snubber is

implemented. Table II shows the parameters and the component

values. Based on the converter parameters, and from (18), the

value of nmax would be 0.33. The value of n is selected as 0.28.

Hence, from (21), the value of LS_max would be 77 µH. The

snubber inductor LS is selected equal to 55 µH. Besides, from

(24) and (25), the values of CCmin1 and CCmin2 would be 0.59

and 0.57 µF, respectively. The clamp capacitor CC is selected

equal to 2.2 µF. For the main switches (S1 and S2), IRFP460

is used, and MUR860 is utilized for the auxiliary diodes (D1,

D2, and D3). Based on the selected switches, and from (14), the

TABLE IIPARAMETERS AND COMPONENT VALUES OF THE

IMPLEMENTED PROTOTYPE CONVERTER

value of CSmin would be 0.2 nF. By a proper overdesign, the

snubber capacitor CS is selected equal to 2.2 nF. The measured

waveforms of the proposed converter at full load (500 W) and

20% of full load (100 W) are illustrated in Figs. 6 and 7,

respectively. Besides, the photo of the prototype is shown in

Fig. 8. From the voltage and current waveforms of the main

switches (S1 in boost operation and S2 in buck operation), ZCS

turn-ON and ZVS turn-OFF are distinctly observed. Besides, as

seen from the voltage and current waveforms of the main diodes

(S2 body diode in boost operation and S1 body diode in buck

operation), the reverse recovery current of the slow body diodes

is under control due to the defined di/dt rate. Also, the ZVS



Fig.8. Photo of the prototype.

TABLE IIIPOWER LOSS ANALYSIS OF THE PROPOSED CONVERTER

condition of the main diodes at turn-OFF is provided, and so,

the voltage/current overlap is almost omitted. Consequently, the

reverse recovery losses of the slow body diodes are reduced.The

current waveforms of the diodes D2 and D3 (iD2 and iD3) clearly

demonstrates that the ZCS condition at turn-OFF is provided

for these diodes, and, the circulating current of the proposed

converter is relatively low. Also, as seen from the measured

waveforms of iD2 and iD3 in 20% of full load, the level of the

circulating current diminishes at light loads. Hence, excellent

efficiency is achieved over a wide load range.

To analyze further the effectiveness of the proposed converter,

a loss breakdown analysis is undertaken. Table III shows the

component losses in both of the boost and buck modes at

full-load (500 W) and 20% of full-load (100 W). As observed,

due to ZCS turn-ON of the main switches, capacitive turn-ON

losses in the main switches are not eliminated. To evaluate

this issue in comparison with the previous ZVS BBBCs, an

important issue should be considered that in all of ZVT BBBCs

in [2]–[16], ZVZCS BBBC in [19] and active-clamping BBBCs

in [22]–[23], although ZVS condition is achieved for the main

switches, the auxiliary switches turn-ON under ZCS and their

capacitive turn-ON loss still exist. In [24]–[34], soft-switching

is achieved without using auxiliary switches. Table IV presents

a comparison between the proposed snubber and some of these

converters. In the BBBCs introduced in [24]–[28], ZVS con-

dition is obtained for the main switches without additional

voltage stress. However, in these converters, a substantial and

constant circulating current always exist in the converter over

load variations. The conduction losses due to these circulating

currents reduce the converter efficiency, particularly at light

TABLE IVCOMPARISON BETWEEN THE PROPOSED LOSSLESS SNUBBER AND

SOFT SWITCHING CIRCUITS WITHOUT AUXILIARY SWITCH

Fig. 9. Efficiency curves of the proposed converter and ZVS BBBCswithout auxiliary switch in [24]–[26] under the condition of VL = 150 V,VH = 380 V, and f = 100 kHz.

loads. Compared with the proposed converter, these conduction

losses are dominant with respect to the capacitive turn-ON losses

of the proposed converter. To illustrate this issue, the efficiency

curves of the proposed converter and ZVS BBBCs in [24]–[26]

are shown in Fig. 9. For all compared converters, the operating

condition and the employed semiconductor elements are the

same as the proposed converter.

V. CONCLUSION

In this article a new lossless passive snubber for the BBBC was

introduced. The operation of the BBBC with the proposed snub-

ber was analyzed in both the buck and boost modes, and the de-

sign considerations for the proper operation of the converter was

presented. The proposed snubber provided fully soft-switching

conditions for the BBBC at both the buck and boost operating

modes. Due to soft switching, the reverse recovery losses of the



low-speed body diodes of the BBBC were virtually eliminated.

These conditions were ensured over a wide load range, and with

a relatively low circulating current. The experimental results

of a 500 W prototype were presented for both the boost and

buck operations at full load and 20% of full load (100 W). The

experimental results confirmed the converter proper operation.

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