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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2674629, IEEETransactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Open-Circuit IGBT Fault Detection and Location Isolation for Cascaded Multilevel Converters

Jacob Lamb, Student Member, IEEE, and Behrooz Mirafzal, Senior Member, IEEE

Abstract—An open-circuit IGBT fault detection technique for cascaded h-bridge (CHB) multilevel converters is presented in this paper. This technique, designed to be implemented independently for each CHB leg, utilizes one current sensor and one voltage sensor to monitor a leg’s current and output voltage. Measured voltages are compared to expected voltages, and deviations are used to determine open-circuit fault locations based on the deviation’s magnitude and current flow direction. Once potential fault locations have been identified, the fault location is systematically isolated and then verified, reducing the possibility of unnecessary corrective actions due to fault misidentification, e.g. an intermittent gate misfiring fault being classified as an open-circuit fault. The proposed technique can be implemented for any number of cells, is independent of the PWM strategy used, and can be applied to symmetric and asymmetric CHB converters regardless of the cell input dc-source magnitudes utilized, i.e. cell input voltages are not required to be equal or to exist in specific ratios. For a CHB leg with cells, the proposed technique identifies and isolates open-circuit switch faults in less than measurement (sampling) cycles, and verification is completed in less than one full fundamental cycle. Experimentally obtained data demonstrate the efficacy of the proposed fault detection and isolation technique.

Index Terms—Cascaded h-bridge multilevel converters, fault-tolerant control, open-circuit fault detection.

I. INTRODUCTION

ultilevel converters, compared to traditional two-level voltage source inverters, provide reduced ⁄ ,

improved scalability, and reduced THD at lower switching frequencies, making them an attractive option for use in high-power applications [1]-[9]. Several multilevel topologies exist, but three of the most established are the neutral point clamped, the flying capacitor, the modular multilevel, and the cascaded h-bridge (CHB) multilevel converters [3]-[11]. This paper focuses on the CHB converter, which has been implemented and proposed for use in a wide range of applications, including active filters, renewable energy conversion systems, and traction motor applications [3]-[5], [12], [13].

Regardless of the topology used, solid-state based power converters are vital components of many advanced electrical systems [1]-[7], [12]-[19]. At a minimum, converter failure is an inconvenience often necessitating costly repairs [4], [18]-[20], and in critical applications converter failures can be hazardous. For instance, a converter failure occurring in a

Manuscript received September 12, 2016; revised November 12, 2016, and

December 9, 2016; accepted December 31, 2016. This work was supported in part by the National Science Foundation under Grant ECCS-1351665.

The authors are with the Electrical and Computer Engineering Department, Kansas State University, Manhattan, KS 66506 USA (e-mail: [email protected]; [email protected]).

transportation vehicle during operation can adversely affect vehicle stability, thereby endangering passengers [4], [16], [18], [20]. As such, ensuring the reliable operation of converters has become an increasingly important goal for the electrical engineering community [1]-[9], [14]-[23]. Insulated-gate bipolar transistors (IGBT) are known to be one of the most failure prone components of power converters [4], [17]-[21], [23]-[25]. Thermomechanical fatigue is the main cause of IGBT failures [8], [19], [21], [24], and due to the inherent power and thermal cycling in some applications, e.g. electric vehicle motor drives [26], this thermomechanical fatigue is difficult to avoid. The probability of an IGBT fault is further increased when using multilevel converters, as opposed to traditional two-level voltage source inverters, due to the high number of semiconductor switches [2], [4], [9]-[12]. These additional switches, however, make multilevel converters inherently reconfigurable allowing continued converter operation in the event of one or more faults [2]-[4], [11], [27].

Switch failures can be roughly classified as open- or short-circuit faults [1], [11], [17]-[20], [28]. Short-circuit failures can cause nearly immediate damage to a CHB cell [9], [17], [18], [20], [22], but the dangers of open-circuit faults cannot be neglected as extended operation with open-circuit failures can cause extensive damage to an entire system [1], [6], [13], [17], [18], [20]. Further, the probability of an open-circuit fault occurring, e.g. due to thermomechanical fatigue, is non-negligible and must be addressed [17], [18], [20]. Identification and isolation of open-circuit faults can be approached using algorithmic solutions, as proposed herein, whereas short-circuit protection is often provided by hardware solutions [15], [16], [18], [20], such as the desaturation [9] or / feedback methods [22]. Hardware is used for short-circuit protection largely due to the speed with which these faults must be detected and corrected, often cited as 10μs, in order to prevent damage to the complementary switch within a leg [11], [15], [18]. Furthermore, industrial drives typically include short-circuit protection [17], whereas protection is not included as a standard feature for open-circuit faults [23]. Accordingly, there is still an industry need for further advancements which protect against open-circuit faults [23]. This paper focuses on open-circuit IGBT faults, characterized by loss of IGBT control but continued operation of the faulty switch’s anti-parallel diode [12], [16]. Such faults are due, for instance, to wire bond liftoff or failure in gate-drive circuitry [6], [8], [20], [28]. These open-circuit faults create deleterious effects which can cause further system damage if no remedial action is taken [1], [6], [13], [17], [18]. However, prior to any corrective reconfiguration, e.g. [12], [27], the fault location must be pinpointed [9].

Various techniques for fault identification have been proposed [11], [15], [16], [20], [23], [28], but are targeted toward implementation in two-level voltage source inverters and therefore do not aim to identify the exact location of a

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L ELECTRONICS

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E TRANSACTIONS

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Once all possiitch most likelymade to have

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measured outltage then no refore is

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L ELECTRONICS

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2) For ∈ 1,4ce the current rrent will flow tmilarly, if ∈ce the current f3) The possiblyough the con∈ 1,4 or negang either of the∈ 1,0 if Regardless of nverter, when en-circuit fault the measured visfying (1) or (cell operates npected open-csfiring, wherea2 may indica

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fault in ,plemented. Onll 1 using the bFinally, it is noquires consideilization of high

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5. Three-step 2,3 the current d

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through the fau2,3 then Cell

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using this thris verified if th

voltage during(2) occurs durinnormally durincircuit fault mas unexpected ate time-variany changed stisfied. Confirmult location le of the general fault is first ide example fromnd (ii) The isola-bypassed by w changes dire

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L ELECTRONICS

gain used for Ph the converterulty switch’s anl is used for P

he converter is pch is tested ones, i.e. becom2,3 . The sw

fected by the fa,0 if 2, etrategy utilize

ree-step procedhe expected leg steps 1 and 2ng step 3. On t

ng steps 1, 2, may have beoutput voltage

nt input dc-sosuch that (1)ming or clear

takes apprrated waveformdentified.

m the previous sated faulty switsetting ection, i.e. al. When currealf-cycle later,

1 . Redeviate from and corrective

rrective action or. ation of the proe sensor circhigh-resolution

m voltage and the time req

er, the proposeh-bandwidth seble to high-frer circuitry is ced and the oise, although

mately up to thesensor circuitry

ess for a , fstep is reversed

PWM generatir is negative, nti-parallel diodPWM generatipositive. nce current flo

mes positive fitch is tested

fault location, eetc. ed by the CHdure a suspectg voltage is equ2, but a deviatithe other hand,and 3, then t

en due to gaes during stepsurce magnitud) or (2) weing , as roximately om, depending

subsections: tch is , , a0 while 0, Cell 1 is us

ent flow chang the verificatiegardless of t

by , and the actions can is to hard-bypa

oposed techniqcuitry necessan sensors increa

current can quired for faed technique doensors, which aequency noise.

decreased thsystem is le

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e.g.

HB ted ual ion , if the ate s 1 des ere an

one on

and 0.

sed ges ion the hus be

ass

que ary. ase be

ault oes are

If hen ess ent ner as

the proupon th

In thpresentthe meproposeeach pvalidatiOpen-cthe gatprovidethe propgate-miparameusing lein a rosimulatconsidethen anbe usedcould b(1) or (that thbehavioof curre

A. Ope

The obtaineselectedusing Toccurs voltageidentifi

, ,checkedmeasur

antested d∈ 2,After

step mverificaverifiedreferenpeak, referenovermo

For oposed methodhe sensor bandw

IV.

his section, Mted for a symmethods proposed technique i

phase, data colion of the deteccircuit faults wte signal sent ed for two diffposed techniquisfiring fault.

eters shown inevel-shifted sin

otating pattern tion idealitieseration. Howevn epsilon value d since the CHbe selected to m(2) to be satisfi

he converter’s or of the propoent flow throug

en-Circuit Fau

simulation dataed for an oped to demonstraTable III paramwhen the leg-

es are equal,ied as possib

, , ,d in the ordrement cycles, nd the isolatioduring isolatio,4 , 0 if r , is isol

method presenation completed, a hard-bypas

nce waveform ithereby preve

nce waveformodulation is pe

SPrefault Referenc

, ,

Carrier FrequencMeasurement PeLoad

d does not impwidth.

SIMULATION R

MATLAB/Simumetric three-cesed in the pris designed to llected for a ction, isolation

were simulated to a given sw

ferent simulatioues for: (A) an

The presenten Table III, wnusoidal PWMto achieve th

s, selecting ver, if measurebased on the 4

HB is symmetmitigate noise

fied during normload does no

osed technique,gh the converte

ult

a in this subsecen-circuit ,ate the longest

meters. For thisstate is the maximum

ble fault locat, , , ,

der they appe2.5ms, elapseon of , .

on, the test leg∈ 1,3 , and

lated, the fault nted in Sect

ed 11.47ms aftss is implementis adjusted fromenting overmom adjustmentermitted for th

TABLE III SIMULATION PARA

ce Voltage

cy riod

2.5

pose any strict

RESULTS

ulink simulatioell CHB leg torevious section

be individualsingle-phase s

n, and verificatiby appropriatewitch. Simulatons to show thopen-circuit faed simulations

with gate signaM, where cells he desired vol

is not aement noise we40V input dc vtric. For instan

concerns withmal operation.ot significantly, provided thater can be determ

ction, shown in fault, where

t possible isols simulation, fa1, 1, 1 . Si

m number of tions, i.e. . Elements

ear in the see between the g

For switch g-state used wd 1 for a

is verified usition III, with

fter isolation. Wted for Cell 3 am a 100V peaodulation. Not can be

he application.

AMETERS 100 sin 2π60t

3 40,40,40 1.32 kHz 500 μs

5Ω in series with

requirements

on results are o demonstrate n. Since the lly applied to system allow ion processes. ely modifying tion data are e behavior of

ault, and (B) a s utilize the als generated are activated

ltage. Due to an important ere a concern, voltages could nce, 20V hout allowing

Finally, note y impact the t the direction mined.

n Fig. 6, were e , was ation process

fault detection ince all input switches are

, , of are

et, thus five generation of

, was 0 if

all . ing the three-h successful

With the fault and the PWM ak to an 80V ote that this

omitted if For a three-

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E TRANSACTIONS

ase system, onfiguration

mpensation [11

Gate Misfiring

Simulation dattained for a ected to demon

a non-singulmulated gate-mpear as an opene-misfiring fau

nducting to nonFor this simulaen 1,1, 0, , , . A

ecked in the asurement cyc

d the isolation then implemenerating properrefore cleared a

V.

In this sectionhnique are preen-circuit faultgate signal sensetup shown i An Altera Ehniques outlinhniques for det

. 6. CHB leg lineuit fault occurring

ck, occur in the 2.5

. 7. CHB leg linfiring fault occurrilack, occur in the

S ON INDUSTRIAL

postfault opeactions, e.g

], [27].

g Fault

ta in this subs, gate-mis

nstrate the sholar , usin

misfiring fault n-circuit until iult is cleared ifn-conducting anation, an appare0 , and thus As before, the

order they acle, 500μs, elof , . The

nted, and ,rly 11.20ms and no correcti

EXPERIMENTA

n, experimentasented for an ats were emulatnt to a given swin Fig. 8, with pEP3C16F484Cned in [29], tection, isolatio

e-to-neutral voltagg at 17.35ms. Faul5ms between pref

e-to-neutral voltaging at 18.8ms. Fa0.5ms between pr

L ELECTRONICS

eration may g. fundamen

section, shownfiring fault, wrtest possible i

ng Table III causes the af

its gate signal f the gate signnd back. ent open-circuit

,ese possible faappear in theapses between

e three-step ver is tested and

after isolationive action is ne

AL VERIFICATIO

al data verifyinasymmetric thrted by appropr

witch. Data werparameters as

C6 FPGA, prowas used to

on, and verifica

e and load current detection and iso

fault steady-state a

ge and load curreault detection and refault steady-state

require furthntal phase-sh

n in Fig. 7, wewhere , wisolation proceparameters. T

ffected switch is cycled, i.e. tal is turned fro

t fault is detect, , , ,

ault locations ae set, thus on generatirification proceconfirmed to

n. The faultecessary.

ON

ng the proposree-cell CHB leriately modifyire collected usioutlined in Tabogrammed usi

implement tation proposed

t with a , opolation, highlightedand verification.

nt with a , gisolation, highlighe and verification.

her hift

ere was ess, The

to the om

ted ,

are one ion ess be is

sed eg. ing ing ble ing the

d in

SectionimplemASPWMsoft-byppreventpermittadjustmpostfaue.g. fun

The experimdigital output divider amplifimeasurtransduADC. StransferFPGA.

2.5also attsatisfy current

pen-d in

gatehted

Fig. 8. Otechniqu

n III. Steady-mented using th

M [3]. Reconfypass for the ft overmodulatted for an apment can be oult operation mndamental phas

current and mental setup isconverter (ADvoltage, after

r and then shifier (IA) withred using a 2ucer, a voltage dSerial peripherr the 12-bit m

The propo5V, selected batempting to m(1) or (2) in th

t flow reversal

One leg of this labue, as it is designed

EPrefault Refere

, ,

Carrier FrequenMeasurement PLC Filter Load

-state behaviorhe FPGA, was figuration for vfaulty cell andtion. As befopplication thenomitted. Also,

may require furtse-shift compen

voltage senss shown in FigDC) was used

it had been sfted using an h 1MHz band200 kHz banddivider, an ADral interface co

measurement dosed method ased on the me

minimize the nuhe event of a faduring the isol

boratory scale CHBd to be implemente

TABLE IVEXPERIMENT PARA

ence Voltage

ncy Period

r for the CHachieved using

verified faults cd a reference aore, if overmn the referenc

for a three-pther reconfigurnsation [11], [2sor circuitry g. 9. A MAX18

to measure thstepped down AD620AN insdwidth. The dwidth LAH25D620AN IA, an

ommunication data from the

was implemasurement nois

umber of cells ault. Finally, tolation procedur

B was used to veried independently f

V AMETERS 170 sin 2π60t

3 60,70,75 V2.52kHz ~110 μs

3mH,15 μF 50Ω

HB leg, also g steady-state consisted of a adjustment to

modulation is ce waveform phase system, ration actions, 27]. used in the 87 analog-to-

he converter’s by a voltage strumentation current was

5-NP current nd a MAX187

was used to ADC to the

mented with se level while which could

o help prevent re, (1) and (2)

ify the proposed for each leg.

V



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E TRANSACTIONS

re modified sorrent magnitudeTo provide a baFig. 10, wer

eration continure created sepe driver to mae results show distorted for a

alysis presententinues withouveform is notic

use severe damects of a faultcle, and thus fer occurring, asExperimental dault in , aμs after occuation one m

rification procet, with the fau0,0,1 . The

ected during thltage is 75 configuration ath the referenceExperimental dult detection prodetected and isd then verifiede the current den the fault occermodulation rl. Operation inthe experimen

en-circuit faultes not flow thected until curer the fault occpassed using th

g. 9. Diagram ofnsor circuitry used.

S ON INDUSTRIAL

o that fault detes greater than asis for comparre collected fues normally aparately for ake the corresthe load curren

approximately hed in Section t any correctivceably distorted

mage to some lot are only appfaults may nots shown in Fig.data demonstraare shown in Furring, and measurement ess, described ulty switch finfault is ultimathe test state, sV while theactions are take reduced to predata shown in ocess for a solated in less d in less than odelivered to thcurred, as the cregion to avoin the overmoduntal data showt occurs duringhrough the farrent should flocurs. After the he 0 state as p

f experimental set.

L ELECTRONICS

tection was on0.2A. rison, experimefor the case fter a fault. Op, and ,

sponding IGBTnt and converthalf of each cyII. While con

ve action, the d and has a dc-oads, e.g. motoarent during pt cause ill-effe. 10 for the ting the proposFig. 11. The fa

, is isolatcycle later. in Section III

nally tested ustely confirmedince the expec

e measured ken once the event overmodFig. 12 demon, open-circuthan two mea

one fundamenhe load was noconverter brieflid using the pulation region wn in Fig. 13,g the half-cycaulty switch. Tow through the

fault is isolateper step one o

tup, detailing the

nly permitted f

ental data, showwhere converpen-circuit fau

by forcing tT nonconductivter output voltaycle, matching tnverter operatiresulting curre-offset which cors. Note that tpart of an outpects immediate, fault.

sed technique fault was detectted as the fa

The three-stI, is then carrising the leg-stad as a deviationcted test leg-stavoltage is 0fault is verifie

dulation. nstrates a simi

uit fault. The faasurement cyclntal cycle. In thoticeably affectfly operates in tpotentially fauis more appare, where a le where curreThe fault is ne switch, 4814ed, Cell 1 is sof the verificati

current and volta

for

wn rter ults the ve. age the ion ent can the put ely

for ted

ault tep ied ate

n is ate V. ed,

ilar ault es, his ted the

ulty ent , ent not μs

oft-ion

processoutput is verifi

Expemisfirinmisfirincircuit uwas clenon-conmisfirinoccurs than twand cleoperatioExperim

,cycle. Tfault. Tone ofovermo

Fig. 10. and ,

Fig. 11. in detail

age

s. Because Celis 145V and s

fied the referencerimental data ng faults. As inng fault causeduntil its gate si

eared once the nducting and bng fault occurrand is misiden

wo measuremeneared 12.4mson then resummental data, shgate misfiring

The fault is detThe potentiallyf the three-stodulation brief

Experimental dat (bottom), if no

Performance for aduring detection/i

ll 1 is bypasseso overmodulace is adjusted t

were also con the previous d the affected signal is cycled,gate signal wa

back. Fig. 14 srring in the mintified as an opnt cycles. The ss after being mes with no hown in Fig. 1g fault occurrintected and miscy faulty cell istep verificatiofly occurs. Th

ta collected for ancorrective actions

an open-circuit fausolation and step t

ed, the maximuation occurs. Oto prevent overollected for simsection, the sim

switch to appea, i.e. the gate-ms turned from c

shows data for iddle of a cycpen-circuit faususpected fault detected, andreconfiguratio5, were also cong near the beclassified as ans soft-bypassedon process, ahe suspected fa

n open-circuit fault are taken.

ult in , , with three of the verific

um converter Once the fault rmodulation. mulated gate mulated gate-ar as an open-misfiring fault conducting to a , gate

cle. The fault ult within less

is then tested d steady-state on necessary. ollected for a eginning of a n open-circuit d during step and therefore fault is tested

t in , (top),

behavior showncation process.



IEEE

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Apreis ttradNonfor utilprois tCHapp

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Fig.nonfaul

E TRANSACTIONS

d cleared 15.5meration resumesAs given in Taesented in this therefore asymmditionally utinetheless, the this asymmetr

lized for the syoposed method therefore comp

HB. It is emphaplying the prop

. 12. Performance

. 13. Performancn-affected cycle. Olty cell during step

S ON INDUSTRIAL

ms after being s with no reconable IV, the cesection were 6metric, althougilized in asPWM strategy

ric converter is ymmetric CHBfor fault detec

patible for boasized that no mposed method t

e for an open-circu

e for an open-circOvermodulation is p one of the verific

L ELECTRONICS

detected, and nfiguration actiell input voltag60V, 70V, andgh not with inpsymmetric CHy used to genedistinct from t

B in the previction, isolationoth symmetric modifications ato asymmetric

uit fault in , o

cuit fault in ,apparent due to thation process.

then steady-staion necessary.ges for the CH

d 75V. The CHput voltage ratiHB converteerate gate signthe PWM schemious section. T, and verificatiand asymmet

are required whCHB converte

occurring mid-cycl

occurring duringhe soft-bypass of t

ate

HB HB ios ers. als me

The ion tric hen ers,

as the indepen

A mmultilevbeen vdata thaand veidentifiis desigleg, (ii)each lemeasur

le.

g athe

Fig. 14. shown in

Fig. 15. non-affecbypassed

PWM schemndent of the fau

V

method for detevel converters

verified using at the presente

erification enabied in less thangned to be im) requires one eg, (iii) identirement cycles

Performance fon detail during dete

Performance for cted cycle. Overmd during step one o

me used durult isolation pro

VI. CONCLUS

ecting open-cis has been pre

simulation aned procedure fobles open-circn one fundamemplemented ind

voltage sensorfies and isolafor a CHB leg

or a gate misfirinection/isolation an

a gate misfiring modulation is appof the verification

ring prefault ocedure.

SION

ircuit IGBT fasented in this

nd experimentaor fault detectiuit faults to bntal cycle. Thidependently for and one curreates faults in lg with cells,

ng fault in ,nd verification fina

fault in , occparent as the fauprocess.

operation is

aults in CHB paper. It has

ally obtained ion, isolation, be accurately is method: (i) or each CHB ent sensor for less than 2 , and verifies

, with behavior alization.

curring during alty cell is soft-



IEEE

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E TRANSACTIONS

ults in less than PWM strate

mmetric and asy

To enable opehnique, even wd (2). Proper gnitudes wh

rformance. Thqualities of (1)

d,

pectively. Three scenario

described in simpacts of th

o-cell asymmere, though the rlude more cells

False Alarms

A false alarm, eration, occursus, from (3) an

In the event of imately be claocess, though c

isolation and r a two-cell as(a) show the |

Missed Detect

A missed detecevent of a faul

plying (6) to (3ult event if,

r any CHB leg,isfying (7) forltages used.

Minimizing |For open-circun be minimizedulty cell satisfiein the event of (3) and (4) as,

d,

cordingly, |

hile the propost necessitate |quired as |

S ON INDUSTRIAL

one fundamengy used, andymmetric CHB

APPEN

en-circuit faultwith noise dis selection is fa

hich can cahis analysis is) and (2) to incl| E

| E

s where noise subsections A, his analysis on etric CHB legresults presentes or symmetric

i.e. a fault dete when d (4), a false al

a false alarm, tassified as fauconverter operverification stymmetric CHB| satisfying (5

tion

ction occurs whlt. Ideally, for a

3) and (4), a m

| |, the shaded arr a given , as

| uit fault eventsd when the faules (1) or (2). Wf a Cell open-

|

|| is not minim

ed open-circuit| minimiza

| decreases. Fo

L ELECTRONICS

ntal cycle, (iv) id (v) can be B converters.

NDIX

t detection usisturbances, isacilitated by dause undesirs achieved blude a noise ter

|

|

affects algoritB, and C, and selection are

, with ed can be natu

c voltages.

ection during h and (1) or

larm occurs if .

the fault locatioult free duringration may be teps of the proB leg, the hash5) for each cell

hen (1) or (2) ara Cell open-c

, 0, 0

missed detection

. rea of Fig. 16(bs (7) is indepe

s in asymmetrlt is initially de

When applying (-circuit fault, (6

|

| . mized if, for an

t fault detectioation, reduced or a two-cell a

is independentimplemented

ing the proposs included in (determining norable algorithby adjusting trm, , as, (

, (

thm performand in subsectione summarized.

, is considerurally extended

healthy conver(2) are satisfie

(on suspected w

g the verificatidisrupted duri

oposed techniquhed areas of Fl for a given .

re not satisfiedcircuit fault, 0,0. (

n occurs during

(b) shows the |endent of the

ric CHBs, |etected if only t1) and (2) to C6) can be appli

(

(ny ,

. (1on technique do

isolation time asymmetric CH

t of in

sed (1) ise hm the

(3)

(4)

nce n D

A red

d to

rter ed.

(5) will ion ing ue.

Fig.

d in

(6)

g a

(7) |

dc

| the

Cell ied

(8)

(9)

10) oes

is HB

leg, thefor a gi

D. Sele

The satisfyitwo-celand mi| | bythis valdetectio

⁄alarms

Ultimselectioto adjuand mimost frmay chthe othemissed

[1] H. asy22,

[2] L. pow

Fig. 16. fixed intwo-cella fault inof (d), thor missed

e hashed area oiven .

ecting

shaded and hing (5), (7), anll asymmetric Cinimization of y setting lue does not prons, or if a 2⁄ allows th

and missed detmately, while on, a system deust upon consissed detectionrequent operatinhoose to reduceer hand, maydetection in th

VSim, J. Lee, an

ymmetric zero-vol no. 2, pp. 27-37, MSun, Z. Wu, F. X

wer back flow

Noise magnituden the shaded and hasymmetric CHB

nitially occurs |hough operation ind detections will o

of Fig. 16(c) sh

hashed areas ofnd (10) for a gCHB leg. False

f | | can be2⁄ , as

rovide sufficiensymmetric Ce greatest |tections. the presented

esigner may dsidering the cons. That is, sinng state for a c

e false alarm pry be increased he event of an o

VII. REFEREN

nd K. Lee, "Deteltage switching staMar.-Apr. 2016. Xiao, X. Cai, andof nonregenerati

es, | |, satisfyinghashed areas of (aleg. The union of | is minimized i

n either region ooccur.

ows the | | sa

f Fig. 16(d) shgiven when ce alarms, missee achieved fors was done in nt noise immunHB is used, | while prev

d analysis mayetermine it is a

onsequences ofnce healthy opeconverter, a sysrobability by reto reduce the p

open-circuit fau

NCES ecting open-switcates," IEEE Ind. A

d S. Wang, “Supive cascaded h-b

g (5), (7), and (10a), (b), and (c), resf these areas is showif the system operor region ensure

atisfying (10)

how the | | considering a ed detections, r the greatest Section V. If

nity to missed then setting

venting false

y facilitate advantageous f false alarms eration is the stem designer educing . On probability of ult.

ch faults: using Appl. Mag., vol.

ppression of real bridge inverters

0) are shown for spectively, for a wn in (d). When rates in region es no false flags



IEEE

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

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S ON INDUSTRIAL

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ult in a grid-conlectron., vol. 27, nan, R. Zhu, and evel converters unvol. 63, no. 11, pp. , and M. Saeedifarbmodule failures wer Del., vol. 31, naragoza, J. Pou, verter fault detectwer Electron., vol

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g an EEE

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hase , pp

cell Ind.

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proach without exsed-loop PWM Al. 61, no. 9, pp. 496R. GopiReddy, L. power switches: al. 30, no. 5, pp 246

Military Handbook . Hirschmann, D.

eliability predictioans. Power ElectroLezana and G.

nverters under fau 7, pp. 2697–2703Lu and S. K. Sha

d protection methol. 45, no. 5, pp 177Lamb, A. Singh, te based converterwer Syst., vol. 31,

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AC regenerative dri60-4970, Sept. 201M. Tolbert, and B

a literature survey65-2473, May 2015k (MIL-HDBK-21

Tissen, S. Schron for inverters in on., vol. 22, no. 6, Ortiz, “Extended

ult condition,” IEE3, Jul. 2009. arma, “A literatureods for power inv

70-1777, Sep./Oct.and B. Mirafzal, rs in power enginno. 4, pp. 2957-29

acob Lamb (S’1mathematics and ngineering from lagstaff, AZ, USA

owards the Ph.D. Research LaboratoManhattan, KS, US

His research intnd switching algeconfigurable conv

ehrooz Mirafzal .Sc. degree from Ifahan, Iran, in 19ass honors) from

Mazandaran, Iran, inMarquette Universit

ectrical engineerinesearch Engineer, cademic institution008, he was wia Senior Developand developmen

was an Assistant e is currently an AS. His current reseodern energy conv

hed over 60 articee U.S. patents.

recipient of the 2nsactions Prize Papnd Energy Societya 2014 U.S. Nats served as the T09, and is currentl

Applications.

Wang, and B. J. Bfor smart switc

es," IEEE Trans. P4. J. M. Cardoso, "r open-circuit fauives," IEEE Trans14. B. Ozpinecci, “Powy,” IEEE Trans. P5. 7F),” Dept. Defe

roder, and R. WHybrid electrical pp. 2511–2517, N

d operation of caEE Trans. Ind. El

e review of IGBTverters,” IEEE Tr. 2009. "Rapid implemen

neering laboratorie964, Jul. 2016.

13) received the the B.S.E. degre

Northern ArizoA, in 2013. He is cu

degree in the Poory, Kansas StA. terests include pogorithms for fauverters.

(S’01–M’05–SM’Isfahan University994, the M.Sc. de

m the University n 1997, and the Phty, Milwaukee, Wng. From 1997 toas well as a Lectu

ns in Isfahan, Iranith Rockwell Aupment/Project Engt related to motoProfessor at Flori

Associate Professorearch interests inclversion systems ancles in profession

2008 second bestper Award publish

y Transactions Pritional Science FoTechnical Co-Chaly an Associate Ed

Blalock, "A di/dt ching and fast Power Electron.,

A voltage-based ult diagnosis in s. Ind. Electron.,

wer cycle testing Power Electron.,

nse, Dec. 1991,

W. De Doncker, vehicles,” IEEE

Nov. 2007. ascade multicell lectron., vol. 56,

fault diagnostic rans. Ind. Appl.,

ntation of solid-es," IEEE Trans

B.S. degree in ee in electrical ona University, urrently working ower Electronics tate University,

ower electronics ult tolerance in

’07) received the y of Technology, egree (with first of Mazandaran,

h.D. degree from WI, in 2005, all in

2000, he was a urer, with several n. From 2005 to utomation/Allen-gineer, where he or-drive systems. ida International r at Kansas State lude applications nd motor-drives. nal journals and

t IEEE Industry hed in 2007, the ze Paper Award

oundation (NSF) air of the IEEE ditor of the IEEE

ieee transactions on industrial electronics open …misidentification, e.g. an intermittent gate...

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