ieee transactions on electromagnetic …measurement and analysis of glass interposer power...

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 58, NO. 6, DECEMBER 2016 1747

Measurement and Analysis of Glass Interposer PowerDistribution Network Resonance Effects on a

High-Speed Through Glass Via ChannelYoungwoo Kim, Student Member, IEEE, Jonghyun Cho, Member, IEEE, Jonghoon J. Kim, Kiyeong Kim,

Kyungjun Cho, Subin Kim, Srikrishna Sitaraman, Venky Sundaram, Pulugurtha Markondeya Raj,Rao Tummala, Fellow, IEEE, and Joungho Kim, Fellow, IEEE

Abstract—In this paper, we measured and analyzed glass inter-poser power distribution network (PDN) resonance effects on ahigh-speed through glass via (TGV) channel for the first time. Toverify the glass interposer PDN resonance effects on the TGV chan-nel, glass interposer test vehicles were fabricated. With these testvehicles, glass interposer PDN impedance, channel loss, far-endcrosstalk, and eye diagram are measured. Based on these mea-surements, glass interposer PDN resonance effects on the signalintegrity of the high-speed TGV channel are analyzed. Due tolow loss of the glass substrate, sharp high PDN impedance peaksare generated at the resonance frequencies. High PDN impedancepeaks at the PDN resonance frequencies, which affect return cur-rent of the TGV channel, increase channel loss, crosstalks, andPDN noise coupling in the frequency domain and degrade eye dia-gram in the time domain. To suppress these glass interposer PDNresonance effects, a ground shielded-TGV scheme is proposed. Theproposed ground shielded-TGV scheme includes two ground TGVs200 μm away from the signal TGV considering the design rulesand includes package ground underneath the glass interposer. Ef-fectiveness of the suggested grounding scheme on the resonanceeffects suppression is verified with three-dimensional electromag-netic simulation. The proposed shielded-TGV design successfullysuppressed the glass interposer PDN resonance effects that resultsin the suppression of insertion loss, shielding of the crosstalk, andimprovement of the eye diagram of the high-speed TGV channel.

Index Terms—Glass, high-speed channel, interposer, measure-ment, power distribution network (PDN), resonance, through glassvia (TGV).

Manuscript received March 10, 2016; revised June 16, 2016; accepted June30, 2016. Date of publication July 20, 2016; date of current version October 3,2016. This work was supported in part by the Ministry of Knowledge Economythrough the International Collaborative R&D Program “Glass interposer basedRF FEM for Next Generation Mobile Smart Phone” under Grant N0000899, andin part by the R&D Convergence Program of the Ministry of Science, ICT andFuture Planning and the National Research Council of Science and Technologyof Republic of Korea under Grant B551179-12-04-00.

Y. Kim, J. J. Kim, K. Cho, S. Kim, and J. Kim are with the Department of Elec-trical Engineering, Korea Advanced Institute of Science and Technology, Dae-jeon 305-701, Korea (e-mail: [email protected]; [email protected];[email protected] [email protected]; [email protected]).

J. Cho is with Missouri S&T EMC Laboratory, Rola, MI 65409, USA (e-mail:[email protected]).

K. Kim is with Samsung Electronics, Kiheung 65665, Korea (e-mail:[email protected]).

S. Sitaraman, V. Sundaram, P. M. Raj, and R. Tummala are with 3D-System Packaging Research Center, Georgia Institute of Technology, Atlanta,GA 30332, USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TEMC.2016.2587824

I. INTRODUCTION

R ECENTLY, the realization of high-speed electrical sys-tems with wider bandwidth, superior electrical perfor-

mances, smaller dimensions, and lower manufacturing costhas been a continuous challenge. 2.5-Dimensional (2.5-D)integration based on through silicon via (TSV) and siliconinterposers has attracted substantial attention as a promising so-lution toward current industrial challenges due to their improvedelectrical performances and compact design [1]–[4]. The TSVtechnology enables vertical interconnection between homoge-neous or heterogeneous integrated circuits (ICs) that providemuch shorter channel length compared to the conventional, lat-eral integration. The silicon interposer technology increases ICs’integration density and the number of channels since it allowsvery fine pitch metallization [5]. Because of these merits, 2.5-Dintegration based on both TSV and silicon interposer technol-ogy enables the system to transmit a much larger amount ofdata simultaneously that can significantly increase the systembandwidth [6]. Even though the silicon interposer-based 2.5-Dintegration provides promising solutions to current industrialchallenges, the manufacturing cost still remains high due to thefollowing reasons: limited wafer size and additional fabricationsteps required to isolate the conductors from the conductivesilicon substrate. Furthermore, the conductivity of the siliconsubstrate can cause significant signal integrity (SI) issues [7].

In order to mitigate these problems, glass as an interposer sub-strate material is proposed. Glass interposers have several advan-tages namely: excellent dimensional stability, closely matchedcoefficient of thermal expansion (CTE) to silicon dies to bemounted, availability of glass substrates in large and thin panelsizes compared to that of silicon wafers, and lastly, excellentelectrical resistivity of the glass substrate that contributes tolow signal loss up to gigahertz range [8]. Therefore, 2.5-D in-tegration based on the glass interposer is a potential means ofachieving high-bandwidth and high-integration density electri-cal systems with reduced manufacturing cost.

The glass interposer consists of a low-loss glass substrate,polymers, through glass vias (TGVs), and fine-pitch metals fordesigning channels and power distribution networks (PDNs) onboth sides of the thin glass substrate. The PDN of the glassinterposer consists of power and ground planes for supplying astable power to the assembled dies. Since the glass substrate hashigh-resistivity, low-loss channel characteristic is maintained up

0018-9375 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

http://www.ieee.org/publications_standards/publications/rights/index.html

1748 IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 58, NO. 6, DECEMBER 2016

Fig. 1. (a) Low loss of the glass substrate generates high PDN impedancepeaks at the resonance frequencies. These high impedance peaks cause signaland power integrity problems. (b) Transmitted signal through high-speed TGVchannel is distorted by the glass interposer PDN resonance. Glass interposerPDN resonance generates high PDN impedance peaks which disconnect returncurrent of the TGV channel. Therefore, channel loss and crosstalk increase.Received signal is deteriorated significantly due to the glass interposer PDNresonance associated with the low loss of the glass.

to high-frequency range that enables the high-speed signaling.However, this high-resistive, low-loss glass substrate generateshigh PDN impedance peaks at the PDN resonance frequenciesshown in Fig. 1(a). These high PDN impedance peaks discon-nect the return current of the TGV channel, increase insertionloss of the channel, and induce crosstalk problems. Fig. 1(b)describes the degradation of the received signal in the high-speed TGV channel due to the glass interposer PDN resonance.Furthermore, when the return current of the TGV channel isdisconnected due to high PDN impedance at the resonance

frequencies, the return current is loaded to the glass interposerPDN that propagates through the PDN and causes PDN to chan-nel crosstalk problems. In organic packages and PCBs, previ-ous studies report that at the PDN resonance frequencies, highPDN impedance peaks are generated that cause severe signaland power integrity problems [9]–[13]. Also signal and powerintegrity problems and their interactions are widely exploredtopics at the organic package and the PCB level [14], [15].Since the resistivity of the glass substrate is higher than that oforganic or silicon, sharper and higher PDN impedance peaksare generated at the PDN resonance frequencies in the glassinterposer [16], [17]. Therefore, a study dealing with the sig-nal/power integrity analysis of the glass interposer at the PDNresonance frequencies is necessary.

In this paper, we first measure and analyze the glass interposerPDN resonance effects on a high-speed TGV channel. Single-ended TGV channels and glass interposer PDN impedance aremeasured and analyzed in the frequency domain and the timedomain. To experimentally verify the studies, glass interposertest vehicles, composed of a low-loss glass substrate, PDNs,and TGV channels are fabricated for measurement. With thesetest vehicles, glass interposer PDN impedances, channel losses,and crosstalks are measured in the frequency domain up to20 GHz and eye diagrams are measured in the time domain withand without the input signal’s data rate corresponding to thePDN resonance frequencies. Based on these measurements, theglass interposer PDN resonance effects on the SI of the high-speed TGV channel are analyzed. High PDN impedance at theresonant frequencies causes return current discontinuity of theTGV channels, resulting in increased channel loss, PDN noisecoupling, and crosstalk. Due to these problems, the receivedeye diagram of the TGV channel is degraded severely.

To suppress these glass interposer PDN resonance effects onthe TGV channel, we propose the ground shielded-TGV schemeto provide a return current path that is less affected by the reso-nance and crosstalk effects. The proposed design includes twoground TGVs placed 200 μm away from the signal TGV consid-ering the design rules and package ground underneath the glassinterposer. We verified the effectiveness of the proposed ground-ing scheme for the glass interposer PDN resonance suppressionin the simulation level. The proposed ground TGV design suc-cessfully suppressed the glass interposer PDN resonance effectsby providing the return current path less affected by the PDNresonances. By adopting the proposed ground TGV scheme,PDN impedance near the signal TGV is reduced significantly atthe resonance frequencies and as a result, the insertion loss ofthe TGV channel at these frequencies is reduced by more than3 dB below 15 GHz. We also verify effectiveness of the proposedTGV scheme by simulating the eye diagram of the TGV channelat the data rate corresponding to the resonance frequency. Byadopting the proposed grounding scheme, the eye opening isincreased from 61.4% to 69.8% of the peak-to-peak voltage andthe timing jitter is decreased from 5.3% to 4% of the one-unitinterval. Also far-end crosstalk (FEXT) induced by the signalTGV to PDN noise coupling is suppressed from 19.5% to 1.8%of the input voltage. We verified the effectiveness of the groundTGV as a safer-return current path and shielding the crosstalk

KIM et al.: MEASUREMENT AND ANALYSIS OF GLASS INTERPOSER POWER DISTRIBUTION NETWORK RESONANCE EFFECTS 1749

induced by the resonance. Without proper ground TGV design,coupled noise from the signal TGV to the glass interposer PDNpropagates further due to the low loss of the glass substratecausing severe problems to the glass interposer channels andTGV channels.

II. FABRICATED GLASS INTERPOSER TEST VEHICLES FOR THE

PDN IMPEDANCE AND SI MEASUREMENTS

Two test vehicles were designed and fabricated to measureand analyze the glass interposer PDN resonance effects on thehigh-speed TGV channel. The total of two glass interposercoupons were fabricated and each coupon includes several testvehicles with some of duplicated patterns to protect them fromunexpected local cracks of the glass substrate developed duringthe fabrication processes. Freshly drawn glass itself is a verystrong material but TGV and dicing processes generate defectsin the glass that dramatically weaken the strength of the glass.Low-loss polymer is laminated on both side of the glass sub-strate to build up the metal layers and at the same time to preventglass cracking [18], [19]. Even though polymer layers providestrength to the glass interposer, stress from metal layers may stillcause the glass crack; therefore, we duplicated the designs toprotect them from the cracks. Fig. 2 depicts the cross-sectionalview and the design rules of the glass interposer fabricated.A total of four metal layers exist for the interposer channelsand PDNs. Two metal layers are laminated on each side of theEN-A1 glass substrate to form the double sided interposers.Since copper used for platting metal layers is not adhesive tothe glass substrate, additional low-loss polymer, ZS-100 is usedbetween the glass substrate and the metal layers. Lamination ofthe low-cost and low-loss material layers is well-known technol-ogy to provide strength to the brittle substrate, which is also usedin silicon interposers [20]. In the glass interposer, this low-losspolymer allows easy and reliable metallization with low-costprocesses, minimizes direct moisture contact with the glass,and prevents glass cracks. To analyze the glass interposer PDNresonance effects on the signal/power integrity, we designedglass interposer test vehicles with TGV channels transitioningthrough power and ground planes. We targeted a scenario thatTGV channels located far away from the ground and powerTGVs. In the actual interposer, there exist many power/groundvias to operate the assembled chips. Designed glass interposertest vehicles also have several power/ground TGVs to form de-coupling capacitor pads and to measure the PDN impedance,but these power/ground TGVs are located far-away from thesignal TGVs; therefore, we can effectively analyze the glassinterposer PDN resonance effects on the TGV channel. First,power/ground plane are designed in M2/M3 for all test vehicles.On the M1 and M4 layers, interposer channels are designed. De-signed interposer channels include single-ended microstrip linepatterns and crosstalk measurement patterns. To analyze the in-terposer PDN resonance loading effects on the signal channels,some channels include via transition structures. Fig. 2 depictscross-sectional view of the TGV-transition structure in the de-signed glass interposer test vehicles. Channels on M1 and M4are interconnected with microvias and TGVs.

Fig. 2. Cross-sectional view of the glass interposer fabricated. Double sidedglass interposer coupons consist of four metal layers, glass substrate, polymer,micro-vias, and TGVs. To analyze the glass interposer PDN resonance effects,power, and ground plane are located in the M3 and M2 layer, respectively, andsignal channels on M1, M4 layers interconnected with TGVs.

TABLE IPHYSICAL DIMENSIONS AND MATERIAL PROPERTIES OF THE FABRICATED

GLASS INTERPOSER COUPONS

Symbol Value

Physical Dimensions hg la s s 100 μmtp o l 1 22.5 μmtp o l 2 17.5 μmtm 10 μm

dT G V 100 μmdp a d T G V 120 μm

dμ VIA 45 μmdp a d μ VIA 75 μm

Material Properties εg la s s 5.3 at 2.4 GHzεp o l 3 at 10 GHz

tan δg la s s 0.004 at 2.4 GHztan δp o l 0.005 at 10 GHz

σm 5.8 × 107 σ/m

The physical dimensions and material properties of the testvehicles are summarized in Table I. The height of the glasssubstrate is (hglass) 100μm and the thickness of the polymerlayers 1 and 2 (tpol 1 , tpol 2) are 22.5 and 17.5 μm, respec-tively. Each metal layer that consists of copper has thickness of10μm. The TGV diameter (dTGV ) and TGV pad (dpad TGV )are 120 and 90 μm, respectively. Due to the limitation asso-ciated with the process and design rules, microvia should beused and the diameter of the microvia (dμVIA) and TGV pad(dpad μVIA) should be 45 and 75 μm, respectively. Relative per-mittivity of the glass substrate (εglass) and polymer (εpol) are5.3 (at 2.4 GHz) and 3 (at 10 GHz), respectively, with losstangent (tan δglass , tan δpol) of 0.004 (at 2.4 GHz) and 0.005(at 10 GHz). The low loss of the glass substrate and poly-mer layer allows high-speed signaling up to tens of gigahertzrange compared to the organic and silicon substrate but, at thesame time, cause PDN resonance problems, which is reportedin the previous study performed in the simulation level [16]

To analyze the glass interposer PDN resonance effects onthe SI of the high-speed TGV channel, two test vehicles aremeasured in the frequency and time domain. Figs. 3(a) and 4(a)show the top view of the test vehicles and Figs. 3(b) and 4(b)show the cross-sectional view of the TGV channel.


Fig. 3. Test vehicle-A for measuring the glass interposer PDN resonanceeffects on insertion loss is shown. Top view of the test vehicle-A is shown in(a) that includes single ended high-speed interposer channels with and withoutTGV transitions. Insertion loss and eye diagram are measured for each channelfor the comparison. Probing pad to measure the PDN impedance adjacent to thesignal TGV is also located to compare insertion loss with PDN impedance. Inthe (b), cross-sectional view of the interposer channel with TGV transitions isshown.

The test vehicle described in Fig. 3(a) is designed and fabri-cated to measure the insertion loss and the eye diagram of theglass interposer channels and PDN impedance near the signalTGV. There are two interposer channels; one is designed on thetop layer (M1) in the form of single-ended microstrip line withthe line width of 50 μm and the length of 12 mm. The other isthe single-ended microstrip line with TGV transitions. Channellengths on M1 and M4 layers described as lM 1 and lM 4 as 2 and8 mm, respectively. Channels on M1 and M4 are interconnectedwith TGVs and its cross-sectional view is depicted in Fig. 3(b).Insertion loss profiles in the frequency domain and eye diagramsin the time domain are measured with GSG-type microprobes.On M2 and M3, power and ground planes with 16 and 14 mmin the x and y directions were designed. 200 μm away from thesignal TGV, a GS probing pad to measure the PDN impedanceis designed. Each measuring pad is named with port numbersfor easier comparison between graphs in next section.

The test vehicle described in Fig. 4(a) is designed and fabri-cated to measure the FEXT induced by the PDN resonance inthe frequency and time domains. On M2 and M3, power andground planes with 16 and 16 mm in the x and y directions aredesigned. Two coupled channels are designed with and without

Fig. 4. Test vehicle-B for measuring the glass interposer PDN resonanceeffects on FEXT induced by TGV to PDN noise coupling is shown. Top viewof the test vehicle-B is shown in (a) that includes coupled high-speed interposerchannels with and without TGV transitions. FEXT is measured in both frequencydomain and time domain. In the (b), cross-sectional view of the interposerchannel with TGV transitions is shown.

TGV transitions to compare the PDN resonance impacts on theTGV channels. The distance between coupled lines is 1.5 mm,which is much larger than the width of each line designed tobe 50 μm. For the coupled channels with the TGV transitions,channel lengths on M1 and M4 layers described as lM 1 andlM 4 are set to be 4 mm each. These channels are measuredwith GSSG-type microprobes to provide 50 Ω termination tothe other probing pads except for the pad where we measuredFEXT. In the later sections, we use term T.V (test vehicle) Aand B for the test vehicles shown in Figs. 3 and 4, respectively.

Fig. 5(a) shows photographs of the fabricated glass interposercoupons including Test vehicle-A and Test vehicle-B depictedin Figs. 3 and 4. There are several more glass interposer test ve-hicles, but in this study, we only used two among these test vehi-cles. In Fig. 5(a), test vehicles that we used for the measurementand analysis are shown inside the black-square. As mentionedearlier, we duplicated the same test vehicles in each coupon sincecracks in the glass substrate can be generated during the fab-rication processes, which might damage the test vehicles. Alsoto increase the fabrication yield, we included some dummy pat-terns. For the further studies, we also included some decouplingcapacitor pads. In each test vehicle, we included eight decou-pling capacitor pads with dimension of 3 mm × 1.8 mm. Eachpad has six TGVs interconnecting the pad with power plane in


Fig. 5. Two glass interposer coupons are designed and fabricated. Each couponconsists of several test vehicles shown in Figs. 3 and 4. From the glass interposercoupon shown in (a), test vehicles for the measurement of PDN resonance effectson the signal/power integrity are measured. (b) Test vehicles are measured usingmicroprobes. (c) Glass interposer PDN impedances are measure at variouslocations. Decoupling capacitor pads, TGVs, and channels are marked.

M3. In Figs. 3 and 4, these dummy patterns and decoupling ca-pacitor pads are neglected for easier understanding. Also, whenwe conducted simulation to suppress the glass interposer PDNresonance effects, these dummy patterns and pads are not in-cluded since including these in the 3-D-electromagnetic simula-tion will require tremendous amount of time and computationalresources. Due to these reasons, we do not compare the mea-sured and simulated result directly. However, these two resultshave very similar tendency in the frequency domain and the timedomain. In this paper, we first measure the glass interposer testvehicles and analyze the glass interposer PDN resonance effectson high-speed TGV channel and verify the proposed resonancesuppression scheme using simulation.

Fig. 5(b) and (c) shows photographs of the fabricated glassinterposer coupons under the measurement. We used a micro-probe (Picoprobe GSG, GSSG and GS type with 250 μm pitch,GGB industries Inc.), a calibration kit (#CS-9 and # CS-14,GGB industries Inc.], and coaxial cables (W.L. Gore & As-sociates, Inc.) for both time- and frequency-domain measure-ments. The frequency-domain measurements of glass interposerPDN impedance and channels are conducted up to 20 GHz us-ing a vector network analyzer (VNA). The VNA, model N5230Afrom Agilent Technologies, has a bandwidth covering the fre-quency range from 300 kHz to 26.5 GHz. In the time-domainmeasurements, a pulse pattern generator (PPG) model MP-1763C from Anritsu and a digital sampling oscilloscope modelTDS800B from Tektronix with bandwidth of 20 GHz are used.In the following section, measurement results will be shownwith analysis.

Fig. 6. Measurement result of test vehicle-A shown in Fig. 3. (a). Measuredinsertion loss of the glass interposer channels with and without TGV transitionsis compared. (b) Measured insertion loss of the channel with TGV transitionsis compared with the PDN impedance measured adjacent to the signal TGV. Atthe frequencies where high PDN impedance peaks are generated by the moderesonances, insertion loss of the glass interposer channel increased dramatically.Mode numbers of the resonance are marked in the parenthesis.

III. MEASUREMENT AND ANALYSIS OF THE GLASS

INTERPOSER PDN RESONANCE EFFECTS ON A HIGH-SPEED

TGV CHANNEL

In this section, effects of the glass interposer PDN resonanceon the high-speed TGV channel are measured and analyzed. Inthe previous studies, these issues in glass interposers are reportedonly in the simulation level. We first verified these effects bymeasuring the actual glass interposer test vehicles fabricated.

A. Measurement and Analysis of the Glass Interposer PDNResonance Effects on the Insertion Loss and Eye Diagram ofthe High-Speed TGV Channel

In Fig. 6, measured insertion losses of the glass interposerchannels and the PDN impedance are compared. Test vehicle-Ais measured. The measured insertion losses of the glass inter-poser channel with and without TGV transitions are shown inFig. 6(a). Up to 20 GHz, insertion loss profile is similar forboth channels, but at certain frequencies, insertion loss dra-matically increased in the channel with TGV transitions. Thisphenomenon can be explained by analyzing the graph shown in


Fig. 6(b) that compares the measured insertion loss of the chan-nel with TGV and the PDN impedance measured adjacent to thesignal TGV. The PDN impedance adjacent to the signal TGVhas low impedance up to 20 GHz; therefore, the power/groundplane is a good return path except at the resonance frequencies.When the signal TGVs are located far-away from the groundTGVs, displacement current flows between the power and theground planes to form a return current path. As frequency in-creases, glass interposer PDN inductance also increases affect-ing the return current path. Also, the dielectric loss increasesas frequency increases; therefore, the loss of the TGV channelsalso increases. However, in the glass interposer, return currentis more severely affected by the mode resonances than otherPDN factors. At the mode resonance frequencies wherein highPDN impedance peaks (higher than the PDN impedance de-termined by the PDN inductance) are generated, return currentof the channel is affected more severely since high impedancePDN takes more power than the receiver. Low loss of the glasssubstrate (high Q-factor) generates sharp PDN impedance peaksaffecting the return current of the TGV channel. The magnitueof these impedance peaks is determined by the loss tangent ofthe glass substrate. Due to this reason, return current is dis-continued and the insertion loss increased significantly for thechannel with TGV transitions at the resonance frequencies. Atthese frequencies, signal quality at the receiver side is expectedto be degraded. Appearance of high impedance peaks at thesefrequencies depends on the size of the PDN, locations of thesignal TGV, and material properties of the glass substrate andpolymer. Therefore, if we measure TGV channels’ insertionloss or PDN impedance at other locations, different insertionloss profiles and impedance properties will be obtained.

Eye diagrams are measured to verify this glass interposerPDN resonance loading effect on the interposer channel withTGV as shown in Fig. 7. Eye diagrams of the glass interposerchannel with and without TGV transitions are measured. Thegenerated data pattern from PPG is a pseudo-random-binary-sequence (PRBS) of 28 − 1, with a rise-and-fall time of 30 psand data rate of 7880 Mbps, which corresponds to PDN’s (1, 0)mode resonance frequency. Fig. 7(a) shows the eye diagram ofinterposer channel without TGV transitions. The eye-openingvoltage and timing jitter are 362.2 mV (72.4% of the peak-to-peak voltage) and 18.4 ps (14.5% of the 1-unit interval) at7880 Mbps. Fig. 7(b) shows the eye diagram of interposer chan-nel with TGV transitions. The eye-opening voltage and timingjitter are 291.9 mV (58.4% of the peak-to-peak voltage) and24.4 ps (19.2% of the 1-unit interval) at 7880 Mbps. At theresonance frequency, signal quality is degraded both in the fre-quency domain and the time domain.

B. Measurement and Analysis of the FEXT Induced by theSignal TGV to PDN Noise Coupling at the Glass InterposerPDN Resonance Frequencies

We also measured FEXT in the frequency domain and the timedomain. Test vehicle-B shown in the Fig. 4(a) was measured.First, we measured coupling parameters of coupled channelswith and without TGV transitions in the frequency domain. We

Fig. 7. Eye diagrams of TV-A are measured. Eye diagrams of the glass inter-poser channel with and without TGV transitions are shown. PRBS signal withdata rate of 7880 Mbps that corresponds to PDN’s (1, 0) mode resonance fre-quency is injected. (a) Without TGV transitions and (b) with TGV transitions.In the channel with TGV transitions, eye diagram is degraded at the resonancefrequency due to high insertion loss of the channel.

also measured PDN impedance from the probing pad of thetest vehicle-B defined as port 9. Frequency-domain measure-ment results are plotted in Fig. 8. The distance between coupledchannels in the test vehicle-B is much larger than the channelwidth; therefore, it is less vulnerable to the crosstalk issues.In Fig. 8(a), FEXT in the frequency domain is compared forthe coupled interposer channels with and without TGV tran-sitions. Also, in Fig. 8(b), PDN impedance measured near thesignal TGV is plotted. By comparing the coupled parameterof channels with TGV transition (S85 of test vehicle-B) andPDN impedance measured near the signal TGV (Z99 of testvehicle-B), we can conclude that for the channel with signalTGV transition, due to the high PDN impedance at the moderesonance frequencies, return current discontinuity occurs andthis captured return current propagates along the PDN. Thiscaptured return current in the PDN can be coupled to the otherchannels inducing crosstalk problems.

We also validated this FEXT induced by the PDN res-onance effect in the time domain. This result is shown inFig. 9. We injected 7940 Mbps clock signal (0 to 1 V, 30 psrise-and-fall time and all ports terminated with 50 Ω) that cor-responds to the (1, 0)/(0, 1) mode resonance frequency of the test


Fig. 8. Measurement result of test vehicle-B shown in Fig. 4. (a) MeasuredFEXT of interposer channels with and without TGV transitions is comparedin the frequency domain. More FEXT is induced to the adjacent channeldue to the resonances in the case of channel with TGV transitions. (b) PDNimpedance measured near the signal TGV is shown. At the frequencies wherehigh impedance peaks occur, coupling also increased.

Fig. 9. Measured FEXT in the time domain for the TGV channel at theresonance and nonresonance frequency is shown. At the resonance frequency,more noise is induced to the adjacent channel.

vehicle-B’s PDN to the coupled channel with TGV transitions.53-mV (5.3% of the input voltage) FEXT voltage is measured.This value is 10 times larger than the case when we injected10,000 Mbps clock signal which is nonmode resonance fre-quency to the same coupled channels.

We can conclude that PDN resonance of the glass interposergenerates high impedance peaks and this high impedance peakscause many SI/PI issues. When there are signal via transitionsusing TGVs, high impedance peaks generated by the inter-poser PDN mode resonances disconnect return current path ofthe channel at certain frequencies. Therefore, return current isloaded in the PDN, increasing the channel loss, degrading eyediagram, and inducing PDN noise causing crosstalk to the ad-jacent channels. To fully take the advantages of the glass listedin Section I, design that could suppress these PDN resonanceeffects on TGV channels is necessary. In the following sec-tion, we propose grounding scheme that provides return currentpath less vulnerable to the glass interposer PDN resonance andthat shields noise coupling. We validate the effectiveness of thesuggested grounding scheme using the full 3-D-EM simulator,Ansys HFSS.

IV. SUPPRESSION OF THE GLASS INTERPOSER PDNRESONANCE EFFECTS ON THE HIGH-SPEED TGV CHANNEL

As mentioned in the previous section, glass interposer PDNserves as a good return current path. However, at the glass in-terposer PDN resonance frequencies, many problems occur andthese issues are measured and analyzed. One of the most well-known resonance suppression methods is ground design thatsuppresses resonance effects and decoupling capacitor schemes,which control the PDN impedance [21]–[23]. However, currentglass interposer design rules limit the effectiveness of the de-coupling capacitors due to large pad design [16]. In this section,the effectiveness of proposed ground TGV design on the glassinterposer PDN resonance suppression is validated in the sim-ulation level. In Fig. 10, the proposed grounding scheme tosuppress the resonance effects is shown. The same structuresand materials are used that were mentioned in Figs. 3 and 4 ex-cept that we have also added two ground TGVs, 200 μm awayfrom the signal TGVs for the channels with TGV transitions,which are vulnerable to the PDN resonances. These groundTGVs serve as return current path and noise shield for the TGVchannels. For the simulation simplicity, we ignore some dummypads and vias placed for safer fabrication of the test vehicles.Due to these reasons, simulation and measurement data showsome difference in value; however, almost identical electricalcharacteristics are maintained. We also placed package groundunderneath the glass interposer. Ground balls underneath theglass interposer interconnect ground TGVs with the packageground. In Fig. 10(b), cross-sectional view near the signal TGVis depicted. We now use term “TGV-shielded test vehicle” forthe TGV channels with the proposed grounding scheme.

We verify the effectiveness of the proposed grounding schemeon resonance effects suppression by simulating the insertionloss, PDN impedance near signal TGV, and eye diagram. We alsosimulate FEXT in the frequency domain and the time domain. In


Fig. 10. Proposed TGV-shielded scheme for the resonance effects suppres-sion. (a) Two ground TGVs are located 200 μm away from the signal TGVsto provide return current path less vulnerable to the resonance. Ground ball un-derneath the glass interposer interconnects Ground TGV with package ground.For the glass interposers on the package, the same structures and materials areused shown in Figs. 3 and 4. (b) Cross-sectional view near the signal TGV isdepicted.

the simulation level, we verify the effectiveness of the proposedground TGV shielding for the glass interposer channel operatingat the data rate of the high-bandwidth memory (HBM) channelfrom the FEXT induced by the PDN resonance.

A. Effectiveness of the Proposed Shielded-TGV Design on thePDN Impedance, Insertion Loss of the TGV Channel, and theEye Diagram of the High-Speed TGV Channel

To verify the effectiveness of the proposed ground TGV de-sign on the insertion loss of the channel, we simulated and com-pared interposer channels including TGV transitions with andwithout the proposed grounding scheme. In Fig. 11(a), insertionlosses of channel with and without proposed grounding schemeare compared. Frequency range under 15 GHz, placing groundTGVs lowered the insertion loss at the resonance frequenciessince the return current path is less affected by the PDN. Thiscan be clearly explained by comparing the PDN impedance seennear the signal TGV, which is shown in Fig. 11(b). Frequencyrange below 15 GHz, PDN impedance is lowered at the moderesonance frequencies by placing the ground TGVs. Due to theadditional ground TGVs, via clearance and the package groundunderneath the glass interposer that generates interlevel PDN,mode resonance frequencies are shifted slightly. Even thoughthere are some shifts in the resonance frequencies, values of thePDN impedance peaks are lowered significantly by placing the

Fig. 11. (a) Simulated insertion losses of channel with and without groundTGVs are compared. Frequency range below 15 GHz, placing ground TGVslowered the insertion loss at the resonance frequencies. (b) Placing groundTGVs also lowered the PDN impedance near signal TGVs.

ground TGVs. Due to this reason, in some frequencies, insertionloss is decreased more than 3 dB.

We also simulated eye diagram to verify the effectiveness ofthe proposed ground TGV design on the resonance suppressionin the time domain. S-parameter touchstone files are extractedfrom the insertion loss and PDN impedance simulation setups.We have injected PRBS signal with data rate of 9414 Mbpsand 30ps rise-and-fall time that corresponds to PDN’s (1, 0)mode resonance frequency. Both channels have the same di-mension with TGV transitions, which is shown in Fig. 3(a), butthe only difference is the existence of the ground TGVs nearthe signal TGVs and the package ground. In Fig. 12, simu-lated eye diagrams are compared. Fig. 12(a) is simulated eyediagram of the TGV channel without the proposed ground de-sign. The eye-opening voltage and timing jitter are 307 mV(61.4% of the peak-to-peak voltage) and 5.64 ps (5.3% of the1-unit interval) with the input of PRBS signal with data rate of9,414 Mbps. Fig. 12(b) is simulated eye diagram of the TGVchannel with the proposed ground design. The eye-opening volt-age and timing jitter are 349 mV (69.8% of the peak-to-peakvoltage) and 4.27ps (4.0% of the 1-unit interval) with the inputof PRBS signal with the data rate of 9,414 Mbps. As can be seen


Fig. 12. Eye diagrams are simulated to verify the effectiveness of groundTGVs for the resonance effects suppression. PRBS signal with data rate thatcorresponds to (1, 0) mode resonance frequency is injected to the channels.(a) Eye diagram of the TGV channel without ground TGV. (b) Eye diagramof channel with ground TGV-shield. By locating ground TGVs, eye diagramdegraded due to the PDN resonance is improved.

from the insertion loss profile in the frequency domain, at thisfrequency (4.707 GHz), which corresponds to the injected datarate (9,414 Mbps), insertion loss is lowered 3.78 in dB scale byadopting the suggested ground design.

Due to this reason, eye opening is increased and the tim-ing jitter decreased. Placing the proposed ground TGV designto provide that return current paths are less affected by thePDN resonance lowered PDN impedance near signal TGV andimproved performance of the interposer channel both in thefrequency domain and the time domain.

B. Effectiveness of the Proposed Shielded-TGV Design on theSuppression of FEXT Induced by the PDN Resonance

We also proved the effectiveness of the proposed ground TGVdesign on the FEXT induced by the glass interposer PDN res-onance. As mentioned in the previous section, the distance be-tween coupled channels is set to be 1.5 mm; therefore, groundTGVs can be located between coupled channels’ signal TGVssince the TGV pitch is set to be 200 μm. We simulated FEXTbetween coupled TGV channels shown in Fig. 4(b) with and

Fig. 13. (a) FEXT of interposer channels including TGV transitions with andwithout proposed ground design is simulated in the frequency domain. (b) FEXTin the time domain is simulated with clock signal data rate that corresponds tothe resonance frequency. By locating ground TGVs, FEXT induced by the PDNresonance is suppressed significantly both in the frequency and time domain.

without the proposed ground TGV design. In Fig. 13(a), compar-ison of the FEXT in the frequency domain is shown. Comparedto the measurement result shown in Fig. 8(a) with dotted-line,simulated FEXT result is larger than the measured FEXT in thefrequency domain; however, the tendency of sudden increasein FEXT at mode resonance frequencies is maintained. As canbe seen in Fig. 13(a), suggested ground TGV design loweredFEXT in the frequency range under 15 GHz. When the TGVchannels are designed without ground TGVs, return current iskept in the PDN at the mode resonance frequencies due to thehigh PDN impedance. This return current held in the PDN canbe regarded as a PDN noise, which is a source of the FEXT.In the frequency domain, we verified the effectiveness of theground TGV design on FEXT reduction in the simulation level.

Using the S-parameter extracted from the frequency-domainsimulation, noise coupling in the time domain is also conducted,which is shown in Fig. 13(b). 8,826 Mbps clock signal (0 to 1 V,


30 s rise-and-fall time, and all ports terminated with 50 Ω)that corresponds to the (1, 0)/(0, 1) mode resonance frequencyis injected. Coupled channel without ground TGVs, 195 mV(19.5% of the input voltage) FEXT voltage is induced. Thissimulated FEXT value in the time domain is larger than themeasured result since more coupling in the frequency domainis obtained in the simulation. Since the time-domain simulationis based on the S-parameters extracted during the frequency-domain simulation, this tendency is also reflected in the time-domain simulation. By placing the proposed ground TGV designto the couple TGV channel, FEXT voltage induced to the victimis channel reduced to 18 mV which is 1.8% of the input voltage.Coupled TGV channel with proposed ground TGVs suppressedFEXT voltage induced by the PDN resonance to 10% of thecoupled TGV channel without ground TGVs.

To analyze how severe FEXT induced by the PDN resonanceon the glass interposer channel is and to verify the effective-ness of the suggested ground TGV for shielding this FEXT,we simulated eye diagram of the TGV channel with the datarate of 2 Gbps that corresponds to that of HBM channel and8,826 Mbps clock signal as an aggressor. Results are shown inFig. 14. We used same setup and the port configuration of thetest vehicle-B [see Fig. 4(b)].

We injected PRBS of 28 − 1, 0 to 1.2 V with rise-and-falltime of 30 ps and the data rate of 2 Gbps to the port 7 as aninput signal. As an aggressor, 8,826 Mbps clock signal (0 to1 V, 30 s rise-and-fall time and all ports terminated with 50 Ω)that corresponds to the (1, 0)/(0, 1) mode resonance frequencywas injected. Port 6 is terminated with 50 Ω and port 8 wherewe monitor the received eye diagram is terminated with 2-pFcapacitor. This input data and receiver condition correspond tothose of HBM channel [24], [25]. Eye diagram of the TGVchannel without aggressor is shown in Fig. 14(a) as a reference.Since 2 Gbps input data rate is nonmode resonance frequencyand due to low loss characteristics of the TGV channel, eyeopening is 90.4% of the peak-to-peak voltage and timing jitteris 2.02% of 1UI. However, when we injected clock signal as anaggressor, received eye diagram is deteriorated severely due toFEXT. Since the distance between two coupled channels is muchlarger than the width of the channel, we can conclude that thisFEXT is induced from signal TGV to PDN and then PDN to thechannel due to the glass interposer PDN resonance. This resultis shown in Fig. 14(b). Compared to the eye diagram shownin Fig. 14(a), eye opening is reduced to 81.4% of the peak-to-peak voltage from 90.4% of the peak-to-peak voltage. Alsotiming jitter is increased to 7.68% of 1UI from 2.02% of 1UI.Effectiveness of the proposed ground TGV design for shieldingthe FEXT caused by the glass interposer PDN is shown inFig. 14(c). By applying the proposed ground TGV design to theTGV channels, FEXT is mostly shielded. This can be validatedby comparing the eye diagrams shown in Fig. 14(a) and (c). Theproposed ground TGV design almost eliminated FEXT issuescaused by the glass interposer PDN resonance.

We have verified the effectiveness of the proposed groundTGV design on the PDN resonance suppression by analyzingthe simulated insertion loss, PDN impedance, eye diagram, andFEXT. Even though placing ground TGVs near the signal TGVs

Fig. 14. Effectiveness of the proposed ground TGV-shield design for shieldingthe FEXT caused by the glass interposer PDN is shown. (a) Eye diagram withoutaggressor is simulated. (b) Eye diagram is severely deteriorated due to FEXTinduced by the resonance. Clock signal with data rate corresponding to theresonance frequency is applied as an aggressor. In this case, (c) proposed groundTGV design eliminated FEXT induced by the glass interposer PDN resonance.


may limit rout ability in the glass interposers, due to the PDNresonance problems associated with the low loss of the glasssubstrate, ground TGV design seems inevitable in glass inter-posers. Considering current design rules of the glass interposer,ground TGV design that can suppress the resonance effects re-gardless of the position is one of the most promising solutionsto the glass interposer PDN resonance problems. In the actualinterposers, such as HBM modules, there exist five to six metallayers for the signal, power, and ground nets [25]. If the glass in-terposer is adopted in the systems for low-cost and high-densityintegration, more careful design and analysis should be requiredsince PDN to SI interaction due to the resonance would be muchmore complex with more various PDNs.

V. CONCLUSION

In this paper, the glass interposer PDN resonance effectson a high-speed TGV channel are measured and analyzedfor the first time. Although glass interposer PDN serves as agood return current path, due to the low loss of the glass sub-strate, sharp PDN impedance peaks are generated at the moderesonance frequencies. These high impedance peaks causes re-turn current discontinuity, which can result in the increasedinsertion loss when there exist signal reference changes usingTGVs. The measured eye diagram of the channel with signalTGV transitions has smaller eye-opening voltage and largertiming jitter at the data-rate corresponding to the resonance fre-quency, compared to those of the channel without any signalTGV transition. Furthermore, we measured the PDN resonanceeffects on the FEXT in the frequency domain and the time do-main. For the coupled channels, more FEXT was induced at theresonance frequencies. Without PDN resonance suppression,the performance of the system based on the glass interposercould be severely degraded.

For PDN resonance suppression, we proposed a groundingscheme including ground TGVs adjacent to the signal TGVs andpackage ground. By applying the proposed grounding scheme,in the simulation level, we suppressed PDN impedance near thesignal TGV and as a result, the insertion losses of the channelat the resonance frequencies were suppressed below 15 GHz,with the maximum reduction of 3.78 dB. Also, by applyingthe proposed design, the eye diagram at the resonance datarate was greatly improved: The eye height was increased from61.4% to 69.8% of the peak-to-peak voltage and the timing jitterdecreased from 5.3% to 4% of the one-unit interval. In the caseof FEXT, the coupled voltage was reduced to 10% compared tothe TGV channel without the ground TGVs. Therefore, whendesigning glass interposer PDN and channels, a proper groundTGV design is crucial.

2.5-D integration based on glass interposers is a potentialmeans of achieving high-bandwidth and high-integration den-sity electrical systems with reduced manufacturing cost. In orderto take advantages of glass interposers, PDN resonance shouldbe carefully suppressed. For this reason, the measurement-basedanalysis of the glass interposer PDN and TGV channels, as wellas the PDN resonance suppression method using ground TGV,provide useful design guidance for the glass interposer PDN and

TGV channel. By mending these SI/PI problems associated withthe glass interposer PDN resonance, glass interposer technolo-gies can surely achieve both the superior electrical performancesand significant cost reduction at the same time.

REFERENCES

[1] J. Pak, C. Ryu, and J. Kim, “Electrical characterization of through sili-con via(TSV) depending on structural and material parameters based on3D full wave simulation,” in Proc. IEEE Int. Conf. Electronic MaterialPackaging, Daejeon, Korea, Nov. 2007, pp. 1–6

[2] P. G. Emma and E. Kursun, “Is 3D chip technology the next growth enginefor performance improvement,” IBM J. Res. Develop., vol. 52, no. 6,pp. 541–552, Nov. 2008.

[3] Technology Roadmap of DRAM for Three Major Manufacturers:Samsung, SK-Hynix and Micron, 2013. [Online]. Available: http://www.techinsights.com

[4] R. R. Tummala et al., “Trend from ICs to 3D ICs to 3D systems,” in Proc.IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, Sep. 2009,pp. 439–444.

[5] M. Sunohara, T. Tokunaga, T. Kurihara, and M. Higashi, “Silicon inter-poser with TSVs (through silicon vias) and fine multilayer wiring,” inProc. IEEE 58th Electronic Components Technology Conf., Orlando, FL,USA, May 2008, pp. 847–852.

[6] H. Lee et al., “Electrical performance of high bandwidth memory (HBM)interposer channel in terabyte/s bandwidth graphics module,” in Proc.IEEE Int. 3D Systems Integration Conf., Sendai, Japan, Aug. 2015,pp. TS2.2.1–TS2.2.4.

[7] H. Kim, H. Lee, J. Cho, Y. Kim, and J. Kim, “Electrical Design of sili-con, glass and organic interposer channels,” presented at the Pan PacificMicroelectronics Symposium, Kauai, HI, USA, Feb. 3, 2014.

[8] V. Sukumaran, T. Bandyopadhyay, V. Sundaram, and R. R. Tummala,“Low-cost thin glass interposers as a superior alternative to silicon andorganic interposers for packaging of 3-D ICs,” IEEE Trans. Compon.,Packag. Manuf., vol. 2, no. 9, pp. 1426–1433, Sep. 2012.

[9] J. Pak, J. Kim, H. Lee, J. Byun, and J. Kim, “Coupling of through-hole signal via to power/ground plane resonance and excitation of edgeradiation in multi-layer PCB,” in Proc. IEEE Int. Symp. ElectromagneticCompatibility, Boston, MA, USA, Aug. 2003, pp. 231–235.

[10] J. Kim, K. Shringarpure, J. Fan, J. Kim, and J. L. Drewniak, “Equivalentcircuit model for power bus design in multi-layer PCBs with via arrays,”Microw. Wireless Compon. Lett., vol. 21, no. 2, pp. 62–64, Feb. 2011.

[11] M. Swaminathan, J. Kim, I. Novak, and J. Libous, “Power distributionnetworks for system-on-package status and challenges,” IEEE Trans. Adv.Packag., vol. 27, no. 2, pp. 286–300, May 2004.

[12] J. Choi and M. Swaminathan, “Decoupling capacitor placements in powerdelivery networks using MFEM,” IEEE Trans. Compon., Packag. Manuf.,vol. 1, no. 10, pp. 1651–1661, Oct. 2011.

[13] J. Park et al., “Modeling and measurement of simultaneous switchingnoise coupling through signal via transition,” IEEE Trans. Adv. Packag.,vol. 29, no. 3, pp. 548–559, Aug. 2006.

[14] J. Fan, B. Archambeault, J. L. Knighten, J. Drewniak, and S. Connor,“Noise coupling between signal and power/ground nets due to signal viastransitioning through power/ground plane pair,” in Proc. IEEE Int. Symp.Electromagnetic Compatibility, Detroit, MI, USA, Aug. 2008, pp. 1–5.

[15] R. Cecchetti, S. Piersanti, F. de Paulis, A. Orlandi, and J. Fan, “Analyticalevaluation of scattering parameters for equivalent circuit of through siliconvia array,” IET Electron. Lett., vol. 51, no. 13, pp. 1025–1027, Jun. 2015.

[16] Y. Kim et al., “Analysis of power distribution network in glass, siliconinterposer and PCB,” in Proc. IEEE Int. Symp. Electromagnetic Compat-ibility, Raleigh, NC, USA, Aug. 2014, pp. 470–474.

[17] G. Kumar et al., “Design and demonstration of power delivery networkswith effective resonance suppression in double-sided 3-D glass interposerpackages,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 6, no. 1,pp. 87–99, Jan. 2016.

[18] S. R. McCann, Y. Sato, V. Sundaram, and R. R. Tummala, “Study ofcracking of thin glass interposers intended for microelectronic packagingsubstrates,” in Proc. IEEE 65th Electronic Components Technology Conf.,Las Vegas, NV, USA, May 2015, pp. 1938–1944.

[19] S. R. McCann, Y. Sato, V. Sundaram, R. R. Tummala, and K. Sitara-man, “Prevention of cracking from RDL stress and dicing defects inglass substrates,” IEEE Trans. Dev. Mater. Rel., vol. 16, no. 1, pp. 43–49,Mar. 2016.


[20] J. Yook, J. Kim, S. Park, J. Ryu, and J. Park, “High density and low-costsilicon interposer using thin-film and organic lamination processes,” inProc. IEEE 62nd Electron. Components Technology Conf., San Diego,CA, USA, May 2012, pp. 274–278.

[21] B. Zhao et al., “Analytical PDN voltage ripple calculation using simplifiedequivalent circuit model of PCB PDN,” in Proc. IEEE Symp. Electromag-netic Compatibility Signal Integrity, Santa Clara, CA, USA, Mar. 2015,pp. 133–138.

[22] K. Shringarpure et al., “On finding the optimal number of decouplingcapacitors by minimizing the equivalent inductance of the PCB PDN,” inProc. IEEE Int. Symp. Electromagnetic Compatibility, Raleigh, NC, USA,2014, pp. 218–223.

[23] F. De Paulis, Y. Zhang, and J. Fan, “Signal/power integrity analysis formultilayer printed circuit boards using cascade s-parameters,” IEEE Trans.Electromag. Compat., vol. 52, no. 4, pp. 1008–1018, Nov. 2010.

[24] High Bandwidth Memory (HBM) Dram. JEDEC Standard JESD235,2013.

[25] K. Cho et al., “Design optimization of high bandwidth memory (HBM)interposer considering signal integrity,” in Proc. IEEE Electrical Des.Advanced Packaging Syst. Symp., Seoul, Korea, Dec. 2015, pp. 15–18.

Youngwoo Kim (S’16) received the B.S. degree inelectrical engineering from Korea University, Seoul,Korea, in 2013, and the M.S. degree in electricalengineering from Korea Advanced Institute of Sci-ence and Technology (KAIST), Daejeon, Korea, in2015, where he is currently working toward the Ph.D.degree.

His research interest includes signal/power in-tegrity co-design and analysis in 2.5-D/3-D systemsand glass interposer technologies for low-cost/high-density integration.

Jonghyun Cho (S’09–12–M’13–16) received theB.S., M.S., and Ph.D. degrees in all electrical engi-neering from the Korea Advanced Institute of Scienceand Technology (KAIST), Daejeon, Korea, in 2008,2010, and 2013, respectively.

He was with KAIST as a Postdoc until the end of2014. During the period at KAIST, he successfullyperformed several projects, which included 3-D-ICTSV modeling, silicon, and glass interposer design,and POP PKG design for mobile phone AP. He hasbeen at Missouri S&T EMC Laboratory as a Visiting

Assistant Research Professor since 2015. His current research interests includeSI/PI/RFI issues on system including chip, PKG, PCB, 2.5-D, and 3-D-IC, andalso WPT.

Jonghoon J. Kim received the B.S. and M.S. degreesin electrical engineering from the Korea AdvancedInstitute of Science and Technology (KAIST), Dae-jeon, Korea, in 2011 and 2013, respectively, wherehe is currently working toward the Ph.D. degree inelectrical engineering.

His current research interests include signal in-tegrity and power integrity design and verification ofmagnetic probing structure for current measurementand rubber-based test interposer for the LPDDR4memory test.

Kiyeong Kim received the B.S., M.S., and Ph.D.degrees all in electrical engineering from Korea Ad-vanced Institute of Science and Technology, Daejeon,Korea, in 2009, 2011, and 2015, respectively.

He has been with the Mobile CommunicationBusiness in Samsung Electronics, Korea, since 2015.His current research interests include statistical SIsimulation and modeling for high-speed PCB chan-nels in mobile systems and PMIC noise estimationand PMIC noise reduction methodology developmentin mobile systems.

Kyungjun Cho received the B.S. degree in electronicengineering from Ajou University, Suwon, Korea, in2014, and he is currently working toward the M.S.degree in electrical engineering with the Korea Ad-vanced Institute of Science and Technology, Daejeon,Korea.

His current research interests include design andanalysis of silicon interposer for high-bandwidthmemory considering signal integrity and powerintegrity.

Subin Kim received the B.S. degree in electricalengineering from the Korea Advanced Institute ofScience and Technology (KAIST), Daejeon, Korea,in 2015, where he is currently working toward theM.S. degree.

His current research interests include power in-tegrity issues in power distribution network (PDN) in3-D IC and on-interposer adaptive PDN design.

Srikrishna Sitaraman received the B.E. degree inelectronics and communications engineering fromthe Anna University, Chennai, India, in 2010, and theM.S. and Ph.D. degrees in electrical and computerengineering from the Georgia Institute of Technol-ogy, Atlanta, USA, in 2012 and 2015, respectively.

He joined TE Connectivity in August 2015 andsince then he has been working on microelectronicspackaging for RF and power modules. His researchinterest includes 3-D packaging and integration, em-bedded passives, and system miniaturization.

Venky Sundaram received the B.S. degree in Met-allurgical engineering from the Indian Institute ofTechnology, Mumbai, India, and the M.S. and Ph.D.degrees in materials science and engineering fromGeorgia Institute of Technology (Georgia Tech), At-lanta, USA.

He is the Director of Research and Industry Rela-tions with the 3-D Systems Packaging Research Cen-ter, Georgia Tech. He is the Program Director for theGlass Interposer industry consortium with more than50 active global industry members. He is a globally

recognized expert in packaging technology and a co-founder of Jacket MicroDevices, an RF/wireless start-up acquired by AVX. He has published morethan 100 publications and holds more than 15 patents. His current research in-terests include system-on-package technology, 3-D packaging and integration,ultrahigh-density interposers, embedded components, and systems integrationresearch.

Dr. Sundaram is the Co-Chairman of the IEEE CPMT Technical Commit-tee on High Density Substrates and is on the Executive Council of IMAPS asthe Director of Education Programs. He was a recipient of several best paperawards.


Pulugurtha Markondeya Raj received the B.S. de-gree in Metallurgy and Material Engineering from theIndian Institute of Technology, Kanpur, in 1993, theM.S. degree in Metallurgy from the Indian Instituteof Science, Bangalore, in 1995, and the Ph.D. degreein ceramic engineering from Rutgers University, in1999.

He is currently a Research Professor and Pro-gram Manager for the Power and RF functional com-ponents and modules program at the 3-D SystemsPackaging Research Center (PRC), Georgia Institute

of Technology, Atlanta, USA. At PRC, he provides leadership in the areas ofpower-supply component integration on silicon, glass, and organic substratesfor power conversion and integrity, RF and precision components (antennas,diplexers, matching networks, nonlinear devices), and fine-pitch interconnec-tions. He co-developed several technologies that include low-cost capacitor andinductor integration, advanced thin film precision analog, and RF componentswith nanomagnetic and nanocomposite dielectrics, and their package integra-tion as functional modules.

He coauthored 250 publications, 11 books, 8 patents with others pending.Dr. Raj received more than 15 “Best Paper” awards for his conference and

journal publications that include the “Distinguished Scholar Award” from theMicrobeam Analysis Society, the IEEE TRANSACTIONS OF ADVANCED PACKAG-ING Commendable paper Award, IEEE Outstanding Technical Paper, IEEE Elec-tronics and Component Technology Conference (ECTC) Best-Poster Award, andthe Philips Best Paper Award. He is the Co-chair for IEEE CPMT Nanopack-aging technical committee, and the track chair for nanopackaging at the IEEE-NANO conference. He is also the Co-chair and has served as session chair forthe “High-speed, Wireless & Components” thrust in the CPMT, ECTC.

Rao R. Tummala (F’93) received the B.S. degreein Metallurgy from the Indian Institute of Science,Bangalore, India, and the Ph.D. degree in MaterialScience and Engineering from the University of Illi-nois at Urbana–Champaign, Champaign, IL, USA.

He was an IBM Fellow, pioneering the first plasmadisplay and multichip electronics for mainframes andservers. He is currently a Distinguished and En-dowed Chair Professor, and the Founding Directorof the National Science Foundation Engineering Re-search Center with the Georgia Institute of Technol-

ogy (Georgia Tech), Atlanta, GA, USA, pioneering Moore’s law for systemintegration. He has authored about 500 technical papers, the first modern bookentitled Microelectronics Packaging Handbook, the first undergraduate textbookentitled Fundamentals of Microsystems Packaging, and the first book entitledIntroducing to System-on-Package Technology, and holds 74 patents and inven-tions.

Prof. Tummala is a member of the National Academy of Engineering, andwas the President of the IEEE Components, Packaging, and ManufacturingTechnology Society and the International Electronic Packaging Society. He hasreceived many industry, academic, and professional society awards, includingthe Industry Week’s Award for improving U.S. competitiveness, the IEEE’sDavid Sarnoff Award, the IMAPS’ Dan Hughes Award, the Engineering Ma-terials Award from ASM, and the Total Excellence in Manufacturing Awardfrom SME. He received the Distinguished Alumni Awards from the Universityof Illinois at Urbana–Champaign, the Indian Institute of Science, and GeorgiaTech. In 2011, he was a recipient of the Technovisionary Award from the In-dian Semiconductor Association and the IEEE Field Award for contributions inelectronics systems integration and cross-disciplinary education.

Joungho Kim (SM’14–F’16) received the B.S. andM.S. degrees from Seoul National University, Seoul,Korea, in 1984 and 1986, respectively, and the Ph.D.degree from the University of Michigan, Ann Arbor,MI, USA, in 1993, all in electrical engineering.

He joined the Memory Division, Samsung Elec-tronics, Suwon, Korea, in 1994, where he was in-volved in gigabit-scale DRAM design. In 1996, hejoined the Korea Advanced Institute of Science andTechnology (KAIST), Daejeon, Korea, where he iscurrently a Professor with the Department of Elec-

trical Engineering. He is also the Director of the 3-D Integrated Circuit (IC)Research Center supported by SK Hynix Inc., and the Smart Automotive Elec-tronics Research Center supported by KET Inc. He has given more than 219invited talks and tutorials in academia and related industries. In particular, hismajor research interests include chip-p ackage-printed circuit board (PCB) co-design and co-simulation for signal integrity, power integrity, ground integrity,timing integrity, and radiated emission in 3-D IC, through-silicon via (TSV), andinterposer. He has authored or co-authored more than 404 technical papers inrefereed journals and conference proceedings. He has authored a book entitledElectrical Design of Through-Silicon-Via (Springer, 2014). His current researchinterests include electromagnetic compatibility (EMC) modeling, design, andmeasurement methodologies of 3-D IC, TSV, interposer, system-in-package,multilayer PCB, and wireless power transfer (WPT) technology for 3-D IC.

Dr. Kim was a recipient of the Outstanding Academic Achievement FacultyAward of KAIST, in 2006, the KAIST Grand Research Award, in 2008, the Na-tional 100 Best Project Award, in 2009, the KAIST International CollaborationAward, in 2010, the KAIST Grand Research Award, in 2014, respectively, andthe Technology Achievement Award from the IEEE Electromagnetic Societyin 2010. He was the Conference Chair of the IEEE WPT Conference in JejuIsland, Korea, in 2014, the Symposium Chair of the IEEE Electrical Design ofAdvanced Packaging and Systems Symposium, in 2008, and the TPC Chair ofthe Asia-Pacific International EMC Symposium, in 2011. He was appointed asthe IEEE

Electromagnetic Compatibility (EMC) Society Distinguished Lecturer from2009 to 2011. He is a TPC Member of Electrical Performance of ElectronicPackaging and System. He is an Associate Editor of the IEEE TRANSACTIONS

ON ELECTROMAGNETIC COMPATIBILITY. He served as a Guest Editor of the Spe-cial Issue of the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY

for PCB level signal integrity, power integrity, and electromagnetic interfer-ence/EMC in 2010, and the Special Issue of the IEEE TRANSACTIONS ON AD-VANCED PACKAGING for through-silicon-via, in 2011. Recently, he published abook, “Electrical Design of Through Silicon Via,” by Springer, in 2014.

ieee transactions on electromagnetic …measurement and analysis of glass interposer power...

Documents