A Novel Analytical Model for Small Signal

Parameter for Separate Gate InAlAs/InGaAs

DG-HEMT

Parveen,Sweety Supriya,Jyotika Jogi* Micro-Electronic Research Laboratory,

Department of Electronic Science,

A.R.S.D. College

University of Delhi South Campus

New Delhi-110021, India

jogijyotika@rediffmail.com

Dushyant Gupta Department of Electronics,

University College

Kurukshetra University

Kurukshetra-136119, India

gupty2kuk@yahoo.co.uk

Abstract— This paper presents a 3-port Small Signal Equivalent

circuit (SSEC) for Separate Gate InAlAs/InGaAs/InP DG-

HEMT. The various small signal parameters like

transconductance, drain conductance and gate to source

capacitance are obtained. The effect of donor layer doping

concentration (Nd), gate width (W), donor layer doping

thickness (dd) and dual gate control on the various RF

performance parameter including transconductance, drain

conductance, gate to source capacitance and cut-off frequency

are studied. The dual gate control achieved in the DG-HEMT is

observed to exhibit improved cut-off frequency. The analytical

results obtained are compared with Silvaco Altas 2D device

simulation results and found to be in good agreement.

Keywords— small signal equivalent circuit (SSEC), separate

gate DG-HEMT, silvaco atlas 2- D device simulato.

I. INTRODUCTION

In order to meet, the ever growing industrial demand for higher frequency and low noise performance, continuous improvement in device technology is required. Conventional InP based single gate HEMT (SG-HEMT) have exhibited superior microwave performance. However, SG-HEMTs have already reached their limit of scaling. Any further improvement in device performance can be achieved only through alternative device structures. One such structure is the dual gate structure in which two gates are used to control the flow of current in the channel [1-3]. In the structure, being considered in this paper, the two gates are placed on either side of the channel which in turn is formed between two identical heterostructures. The Sub-100nm InAlAs/InGaAs DG-HEMT is fabricated through transferred substrate technique [4] and has exhibited improved microwave and noise performance. It is also the most promising candidate for high frequency and low noise application.

In the present work an analytical charge control model is used to obtain the various small signal parameters of the device. Intrinsic small-signal equivalent circuit (SSEC) for the separate gate DG-HEMT is developed. The SSEC is further used to analyze the microwave performance of the device. By using the various small signal parameters, the cut-

off frequency (Ft) of the dual gate DG- HEMT is obtained. Analytical results are compared with the simulated result obtained using Silvaco Atlas Device 2D simulator and show good match between them, thus validating the analytical model.

II. MODELFORMULATION

The symmetric DG-HEMT with separate gate geometry is shown in Fig.1. The doping profile, doping concentration, nature of schottky layer and the dimensions of various layers in both the heterostructures are taken to be identical for analytical simplicity.

Figure 1. Schematic representation of the Symmetric DG-HEMT

The current flowing through the channel with sheet-

carrier concentration nsj(x) is given by:

(x).v(x)sj

W.q.ndsj

I (1)

where j=1 and 2 for gate1 voltage (Vgs1) and gate2 voltage

(Vgs2) respectively. The sheet carrier concentration, nsj(x) can

be approximated as [5] and x is a point in the channel along x-

direction.

1V

)(jc

Vgm

Vgsj

V

tanhα1αso

n)(sj

n

x

x (2)

and the maximum 2DEG concentration is given by

ΔdddN2

1

Δdd2dN

q

kTf1ΔEfΔEcΔE

q

d2εε

son

(3)

where,

d=ds+dd+di is the total thickness of the InAlAs layer and ds,

da, di are the various layer thickness as indicated in fig.1,

∆d is the distance of the 2-DEG from the heterointerface,

∆Ec is the conduction-band discontinuity at the

InAlAs/InGaAs interface,

∆Ef is the position of the Fermi-level below the bottom of the

conduction-band,

∆Ef1 is the small energy arising from the linear approximation

of nsj versus fermi-level,

Nd is the donor layer doping concentration of the δ-doped

layer (~ 0.25x1025 cm-3),

Vcj(x) is the potential in the channel,

α is a fitting parameter,

V1 and Vgm used in the analysis are given by

K

nα1V so

1

(4)

K

soα.n

thV

gmV (5)

where,

Δdd

da

di

d q

dε

K (6)

Threshold Voltage;

2ε

ddqNΔEΔEφV

2

idd

fcBth

(7)

where, φB (0.56eV) is the barrier potential, ε (12.47F/m) is the

permittivity of the material.

The velocity-field relationship used in the present analysis

is given as

x

x

E

satv

0μ

1

cE

0μ

v

(8)

µ0 (0.83 m2/V-sec) is the electron mobility in the channel.

where

dx

jcdV

E(x)

x

(9)

The total device current for DG-HEMT is obtained by

substituting (2) and (8) in (1)

ds2

Ids1

Ids

I (10)

sat.v

gL

ds.V

0μ

1

jX

gL

0.μ

soq.W.n

dsjI

(11)

0jX

j1X

2

1.Vα1

jX (12)

12α

0jy

10j

y

lnα1

α12α

0j.y 2α2

0jyln

0jX (13)

12α

1jy

11j

y

lnα1

α12α

1j.y 2α2

1jyln

1jX (14)

1V

gmV

gsjV

tanhα1α0j

y (15)

1V

dsV

gmV

gsjV

tanh α1α1j

y (16)

A. Small Signal Equivalent circuit (SSEC)

Figure2 shows the 3-port intrinsic small signal equivalent

(SSEC) circuit for the separate gate DG-HEMT. Here, port 1 is between gate1 to source, port2 is between gate2 to source and port3 is between drain and source. Rinj is the charging resistance at both gates i.e. gate1 and gate2.Ym is the current controlled source and it is given by

2

1jmj

Ym

Y (17)

Figure 2. Small Signal Equivalent Circuit (SSEC) including only intrinsic

element for separate gate DG-HEMT

where

j

iωωexpmj

Gmj

Y (18)

τj represents the transient time of electron, ω is the angular velocity and Gmj is the transconductance of the device and it is defined as the change in the ratio of the total current with respect to the change in the applied gate to source voltage at constant drain to source voltage. In the present model, since the two gates are biased separately the transconductance will also be different with respect to the two gates. This is obtained by using (10).

jibut 1,2i whereconstantgsi

dsV

constantVgsj

ds

mjdV

dIG

(19)

Gd represents the drain conductance of the device and it is given by change in the ratio of the total current with respect to the change in the drain to source voltage at constant gate to source voltage of the device and is obtained by using (10).

1,2j where

constantVds

ds

dgsjdV

dIG

(20)

Cgsj represents the gate to source capacitance at both the gates of the circuit. It is given by the change in the total charge with respect to the change in gate to source voltage and it is obtained by using (2).

Cgdj represents the gate to drain capacitance and it is defined as the change in the total charge with respect to the change in gate to drain voltage and it is again obtained by using (2).

III. RESULTS AND DISCSSION

0

10

20

30

40

50

60

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4

Simulating

Analyitcal

Gate2 Voltage (Vgs2) (V)

Dra

in t

o s

ou

rce C

urre

nt

(Id

s) (

mA

)

Figure 3. Drain to source current vs. gate2 voltage (Vgs2); Vds=0.5 , Vgs1= -0.4

Figure3 shows the variation of drain current with gate2

voltage (Vgs2) at Vds= 0.5 and Vgs1= -0.4. The analytical results obtained agree well with those obtained using SILVACO ATLAS device [6] simulator.

Figure4 represents the variation of drain current with gate2 voltage when Vds = 0.5V and Vgs1 changes from -0.4V to -0.1V with a step size of 0.1V. It is observed that drain current increases with Vgs1 at any particular value of Vgs1 and Vds. Thus, implying a possibility of using one of the gates as an extra controlling port.

0

10

20

30

40

50

60

70

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4

Series1

Series2

Series3

Series4

D

ra

in t

o S

ou

rce c

urre

nt

(Id

s) (

mA

)

Vgs1= -0.1

Vgs1= -0.2 Vgs1= -0.3 Vgs1= -0.4

Gate2 Voltage (Vgs2) (V)

Figure 4. Drain to source current vs. gate2 voltage (Vgs2); Vds=0.5.

0

10

20

30

40

50

60

70

80

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6

Simulating

Analyitcal

Gate2 Voltage (Vgs2) (V)

Tra

nsc

on

du

cta

nce

( G

m2)

(mS

)

Figure 5. Transconductance (Gm2) vs. gate2 voltage (Vgs2); Vds= 0.5, Vgs1= -

0.4

Figure5 shows the variation of the transconductance (Gm2)

with gate2 voltage (Vgs2) and shows the comparison between analytical and simulating result for Vds=0.5 and Vgs1 = -0.4.

Figure6 shows the variation of the total transconductance with gate2 voltage (Vgs2) at Vds=0.5 and for different value of Vgs1. The gate1 voltage controls the total transconductance of the device. As the gate1 voltage (Vgs1) decreases, the transconductance of the device also decreases.

Table. I shows the percentage error of the analytical and simulating result when Vds= 0.5 and Vgs1= -0.4 for the drain to source current (Ids) and transconductance (Gm2). From the table we can observe that as the gate2voltage increases, percentage of the error also increases.

TABLE I. MODEL ERROR TABLE

S. No.

Percentage of Error in the proposed method

Gate2 Voltage

(Vgs2 in volts)

% Error in

Drain to source

current (Ids )

% Error in

Transcon-

ductance

(gm )

1. -0.1 1.47 4.12

2. 0 0.65 0.01

3. 0.1 0.18 2.60

4. 0.2 3.70 5.20

5. 0.3 8.09 8.9

Figure7 and 8 show the variation of transconductance with gate2 voltage (Vgs2) at Vds=0.5, Vgs1= -0.4, as the function of the donor layer doping concentration (Nd) and gate width (W) of the device respectively. It is observed that

as the donor layer doping concentration of the device increases, the peak of

50

70

90

110

130

150

170

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4

1

2

3

Gate2 Voltage (Vgs2) (V)T

ra

nsc

on

du

cta

nce

(Gm

) (m

S)

Vgs1= 0V

Vgs1= -0.1VVgs1= -0.2 V

Figure 6. Transconductance (Gm) vs. gate2 voltage (Vgs2); Vds=0.5

the transconductance shifts and as the gate width of the

device decreases, the transconductance of the device also

decreases. Thus, suggesting the use of engineering of the

separate gate geometries to obtain better transconductance.

Figure9 shows the variation of drain conductance (Gd) with

drain to source voltage at Vgs2=0V when gate1 voltage (Vgs1) = -0.1V and -0.3V. As the gate1 voltage (Vgs1) becomes more negative, decrease in the drain conductance (Gd) is observed.

0

10

20

30

40

50

60

70

80

90

100

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

1

1

Gate2 Voltage (Vgs2) (V)

Tra

nsc

on

du

cta

nce

( G

m2)(

mS

) Nd= 0.2x1025 cm-3

Nd= 0.3x1025 cm-3

Figure 7. Transconductance (Gm2) vs. gate2 voltage (Vgs2); Vds=0.5, Vgs1= -

0.4

0

10

20

30

40

50

60

70

80

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

W=100umW=90umW=80um

Gate2 Voltage (Vgs2)(V)

Tra

nsc

on

du

cta

nce

( G

m2)(

mS

)

Figure 8. Transconductance (Gm2) vs. gate2 voltage (Vgs2); Vds=0.5, Vgs1= -

0.4

Figure10 shows the variation of gate to source

capacitance with gate2 voltage (Vgs2) at Vds=0.1, as a function of donor layer thickness (dd). As the donor layer thickness increases, a decrease in the gate to source capacitance is observed. This is attributed to the depletion of the 2DEG due to more negative bias on gate. Thus, showing a weaker gate control at thicker donor layer.

Figure11 shows the variation of cut-off frequency (Ft)

with gate1 voltage (Vgs1) at Vds= 0.1, Vgs2=0, -0.3. As the gate2

0

0.5

1

1.5

2

2.5

3

3.5

0 0.03 0.06 0.09 0.12 0.15

Drain to source Voltage (Vds) (V)

Dra

in C

on

du

ctn

ace(G

d)

(S)

Vgs1= -0.1 V

Vgs1= -0.3 V

Figure 9. Drain conductance (Gd) vs. drain to source voltage (Vds) ;Vgs1= -

0.1

0

5

10

15

20

25

30

35

40

45

-0.45 -0.3 -0.15 0 0.15 0.3 0.45

Series1

Series2

Series3

Gate2 Voltage (Vgs1) (V)

Ga

t to

So

urce C

ap

acit

an

ce

(Cg

s2)(

Ff)

dd=50Ao

dd=70Ao

dd=30Ao

Figure 10. Gate2 source capacitance (Cgs2) vs. gate2 voltage (Vgs2); Vds= 0.1

voltage becomes more negative there is a decrease in the cut-off frequency of the device because of decrease in the total transconductance and increase in the total gate to source capacitance of the device.

305

315

325

335

345

355

-0.45 -0.25 -0.05 0.15 0.35

Series1

Series2

Gate1 Voltage (Vgs1) (V)

Cu

toff

Freq

uen

cy

(Ft)

(G

Hz)

Vgs2= -0.3V

Vgs2= 0V

Figure 11. Cut-off frequency (Ft) vs. gate1 voltage (Vgs1); Vds=0.1, Vgs2=0

and Vgs2=-0.3

IV. CONCULSION

A novel 3-port small signal equivalent circuit is proposed for

separate gate InAlAs/InGaAs DG-HEMT. The various small

signal signal parameters like transconductance (Gm), drain

conductance (Gd) and gate-to-source capacitance (Cgs) are obtained. The effect of the dual gate control, donor layer doping concentration (Nd), gate width (W), and donor layer thickness (dd) are studied. The results obtained show an improved performance of the DG-HEMT due to better gate control. The proposed SSEC is used to obtain the cut-off frequency of the device as a function of the two gate voltages. A cut-off frequency of 351GHz and 338GHz is obtained for Vgs1= 0V, Vgs1= -0.3V when Vds=0.1V respectively. Comparison of analytical results with the ATLAS device simulator results shows good agreement. This SSEC can be further used to model the microwave performance of the device.

ACKNOWLEDGMENT

The authors acknowledge University Grants Commission for providing financial support for this work.

REFERENCES

[1] N. Wichmann, I.Duszynski, S.Bollaert, J.Mateos, X.Wallart and A.Cappy, “100nm InAlAs/InGaAs Double-Gate HEMT using transferred substrate,” IEDM 04, pp. 1023-1026, 2004.

[2] B.G.Vasallo, N.Wichmann, S.Bollaert, Y.Roelens, A. Cappy, T. Gonzalez,D.Pardo and J. Mateos, “Comparison Between the Dynamic Performance of Double- and Single-Gate AlInAs/InGaAs HEMTs”, IEEE Trans Electron Device vol.54, no.11, pp. 2815-2822, 2007.

[3] B.G.Vasallo, N.Wichmann, S.Bollaert, Y.Roelens, A. Cappy, T. Gonzalez,D.Pardo and J. Mateos, “Comparison Between the Noise Performance of Double-and Single-Gate AlInAs/InGaAs HEMTs”, IEEE Trans Electron Device vol.55, no.6, pp. 2815-2822, 2007.

[4] N. Wichmann, I. Duszynski, X. Wallart, “S. Bollaert, and A. Cappy,“InAlAs–InGaAs double-gate HEMTs on transferred substrate,” IEEE Electron Device Lett., vol. 25, no. 6, pp. 354–356, Jun. 2004.

[5] J.Jogi,S.Sen, M.Gupta and R.S Gupta, “Carrier-Concentratio n-Dependent Low –Field-Mobility For InAlAs/InGaAs/InP Lattice-Matched HEMT for Microwave Application,” Microwave Opt.Tech.Lett vol. 29., pp. 66-70, 2001.

[6] Silvaco Atlas 2-D Device Simulator 2010.