IEEE Standards for Design Automation: Their Impact on the Semiconductor Industry

Karen BartlesonSr. Director, Community Marketing, Synopsys, Inc.Vice Chair, IEEE-SA Design Automation Standards CommitteeMember, IEEE-SA Corporate Advisory Group

Global Standards at IEEE9 March 2010

Agenda

What is Electronic Design Automation?– IC Design Flow– EDA Standards Under IEEE

Benefits of EDA Standards– to EDA Tool Developers– to EDA Users

EDA Standards Collaboration with IndustryCase Studies in EDA Standards

EDA: Where Electronics Begins

Software “tools” for chip design– Architecture design– Functional design and verification– Physical design and verification– Various electrical analyses

Standards improve productivity– Tool interoperability– Data exchange, sharing, and consistency

Let’s Make a Lot of Money!Semiconductor chips are pervasiveSemiconductor industry is about $256.3B*EDA industry is about $4.6B*– Annual revenue:

Synopsys 1.37B* Cadence 863M* Mentor 830M* Magma 128M*

– Market share*: S – 30%, M – 18%, C – 19%Market drivers include:– Time-to-market– Global competition– Lower costs– Technology: smaller, faster, denser * 2009

Productivity increases 10X every 6 years!

Source: Wikipediahttp://en.wikipedia.org/wiki/File:SoCDesignFlow.svg

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Synopsys Example Design Flow Technology

Process

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Gate-level netlist

Testbench

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Specification

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ScriptsInitial constraints

SystemAnalysis

System StudioSaber

SelectArchitecture

Module Compiler

Models / IPLibrary CompilerDesignWare IP

VERA

RTL VerificationVCS-MX

ATPGTetraMAX

SynthesisDesign Compiler Power CompilerDFT Compiler

Gate-levelverification

VCS-MXMagellanFormalityPrimeTime

Place & Route

IC CompilerPhysical Compiler

Links-to-LayoutDesign Planning

PrimeTimeNanoSimHSPICE

Post-Route Verification

Physical DataCreation

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GDSII

JupiterXT

ProteusPhysical Design

ChecksSTAR-RCXTHercules

RTL Gates

Design Constraints

Mask WriterCATS

EDA Standards Under IEEEIEEE Std # Description1076 VHDL1149 JTAG (Test)1364 Verilog HDL1450 Standard Test Interface Language (STIL)1481 Delay & Power Calculation System (DPCS)1497 Standard Delay Format (SDF)1647 Functional Verification Language ‘e’1666 System C LRM1685 IP-XACT1735 IP Encryption and Rights Management1800 System Verilog1801 Unified Power Format (UPF)1850 Property Specification Language (PSL)

Don’t have to address entire design flow– Too complex for small EDA companies

Focus on core strengths– Standards help partition the problem

Integrate tools in design team’s flow– Interoperability means new business

opportunitiesAbility to promote own technology for widespread usage as a standard

Benefits to EDA Tool Developers

Benefits to EDA Tool Users

Portability of design data across multiple toolsUsers’ in-house special-purpose tools integrate easily with commercial toolsReuse of design data – Among different projects– Among different design teams

Faster learning curveBuild customized design flow to suit specific requirementsBetter management over tool purchases

EDA Standards Collaboration with Industry

Availability of the standard is synchronized with many marketing/promotional activities– Several product rollouts– Launching of web site

(e.g., www.systemverilog.org)– Consultants doing tutorials– Seminar series by vendors– User groups– Papers, articles, blogs, …

Wide adoption by user community– When the standard solves REAL problems, it is quickly adopted– Marketing the standard helps to accelerate its adoption rate– Wider community adoption accelerates tool maturity, use models,

and entirely new methodologies– Leads to continued enhancement of the standard

EDA Standards Collaboration with Industry (cont.)

EDA standards-setting organizations bridge to IEEE– Accellera, SPIRIT, OSCI/SystemC– Incubate standards, then transfer to IEEE

EDA’s IEEE standards are sponsored by– Design Automation Standards Committee

(DASC)– Test Technology Council (TTC)

Case Study: SystemVerilog – A Success from Concept to Standard

Computer language for IC designAn industry-wide collaborative effort that started in 2001– Co-Design, Inc. “invented” Superlog, a

derivative/enhancement of Verilog HDL (IEEE 1364) – Company acquired by Synopsys in 2001– Superlog, with many other internal technologies,

proposed as extensions to Verilog for system-level modeling, design, and verification

– Called “SystemVerilog”, created by Accellera– Six technology donations and many enhancements– New entity-based IEEE WG (P1800) formed after

Accellera approved its SystemVerilog standard

SystemVerilog Journey

Ratified as IEEE Std. 1800-2005– Started with SystemVerilog 3.1a from Accellera– Less than one year from transfer to ratification– More than 200 products support the standard– Rapid adoption across design and verification

communityRatified as IEEE Std. 1800-2009– Verilog IEEE 1364 completely integrated– Large user community looking for design and

verification productivity improvementFree tutorial on IEEE Standards Education website

SystemVerilog Spawned an Entirely New Business Segment

Enabled/accelerated IP (design blocks) market segment– One language to write complex design blocks– Same language to verify design blocks– Make IP once, sell many times

Many IP providers for design and verification reuse– Networking, wireless, and consumer applications

Verification IPs as much in demand as design IPs – New methodologies invented

Assertion based verification, testbench automation– Clear inflection point in the industry to deal with large

System-on-Chips

Case Study: UPF – A Low-Power IC Standard

Ever-growing need for low-power ICs in mobile/portable devices and data centersIndustry recognized need for low-power IC standard– Common way for design and verification engineers to describe

IC’s low-power propertiesEDA users and vendors came together to develop a format and methodology– Effort started in 2006 under Accellera– Merged 6 technology donations for multi-faceted requirements– Unified Power Format (UPF) created in 6 months

Ratified as IEEE Std. 1801-2009– Less than 18 months under entity process

Conclusions

EDA users and vendors have embraced IEEE standards for three decadesLarge user community active in development of standards along with vendorsStandards help broaden infrastructure for the entire industry and academia

Thank You