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Integrated circuits operating inspace applications are susceptible to radiationeffects that can be permanent or transient.1

Various energetic particles in the space radia-tion environment can interact with silicon tocause undesirable effects. When a single heavy

ion strikes silicon, it loses its energy by creat-ing free electron-hole pairs, resulting in adense ionized track in the local region. Pro-tons and neutrons can cause nuclear interac-tions when passing through the material. Therecoil also produces ionization, which gener-ates a transient current pulse that can causean upset when interpreted as a signal in thecircuit. With technology scaling into deep-submicron dimensions, the effects of energeticparticle hits become a concern even at sealevel, where the major high-energy radiation

source is atmospheric neutrons and protons.A single particle can hit either the sequen-tial logic or the combinational logic in the sil-icon. When an energetic particle strikes one ofa memory cells sensitive sites, the effect canproduce an inversion in the stored valueinother words, a bit flip in the memory cell. Thisis called a single-event upset (SEU).2Whenan energetic particle hits a sensitive site in thecombinational logic block, it also generates atransient current pulse. This phenomenon iscalled a single-event transient (SET).3 For

combinational logic blocks with registeredoutputs, the SET can eventually appear at theinput of the flip-flops placed at the combina-tional logic outputs, unless the induced tran-sient pulse is either logically or electricallymasked by the logic inputs. If interpreted as a

valid signal in the register input, this SET cancause an incorrect value to be stored in theregister, provoking a soft error.

Continuous technology evolution andsmaller transistor features have made softerrors on devices more frequent. Detectingsoft errors in combinational and sequentiallogic is critical for avoiding errors in the cir-cuit application. However, this task is com-plex because the internal circuit signals aredecreasing to the same order of magnitude asthe transient currents generated by charged-

particle strikes.Researchers have proposed a built-in cur-rent sensor (BICS) connected to the powerlines for monitoring on-chip current variationsprovoked by permanent faults, such as stuck-at faults, and by soft errors in memory ele-ments.4,5 However, to the best of ourknowledge, no one has yet proposed a BICS-based method for detecting SETs in combina-tional logic, and this issue is gainingimportance in new technologies. We proposean approach for using BICS to detect transient

Egas Henes Neto

Ivandro RibeiroMichele Vieira

Gilson Wirth

Universidade Estadual do

Rio Grande do Sul

Fernanda Lima

Kastensmidt

Universidade Federal do

Rio Grande do Sul

CONNECTING A BUILT-IN CURRENT SENSOR IN THE DESIGN BULK OF A DIGITAL

SYSTEM INCREASES SENSITIVITY FOR DETECTING TRANSIENT UPSETS IN

COMBINATIONAL AND SEQUENTIAL LOGIC. SPICE SIMULATIONS VALIDATE THIS

APPROACH AND SHOW ONLY MINOR PENALTIES IN TERMS OF AREA,

PERFORMANCE, AND POWER CONSUMPTION.

USING

BULK

BUILT

-IN

CURRENT

SENSORS TO DETECT SOFT ERRORS

Published by the IEEE Computer Society 0272-1732/06/$20.00 2006 IEEE


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upsets in sequential andcombinational logic.The BICS connects to the transistors designbulkan arrangement we call bulk-BICSwhich increases the sensors sensitivity to detectany discrepancy in a circuits internal current

that might occur during a particle strike. Thisapproach helps in two ways: First, the BICScan distinguish SETs from internal logic sig-nals and consequently detect them, while theBICS connected to the power lines cannot.Second, bulk-BICS has a minor effect on per-formance and power dissipation, comparedwith a BICS connected to the power lines.

We used 100-nm CMOS technology todesign the bulk-BICS and the circuits in ourcase studies, and SPICE simulation validatedthe detection capability. Our results show that

bulk-BICS has high detection sensitivity toSEUs and SETs and a negligible effect onperformance.

The bulk-BICS approach An efficient SEU and SET detection

method is mandatory for evaluating an ICssensitivity and to guarantee its reliability.Researchers proposed BICS for monitoringon-chip SEUs because a BICS presents fewerpenalties than error correcting code, andexperiments have shown that asynchronous

BICS can detect SEUs in memories.4,5

Thisapproach places the BICS on a memoryspower lines.

The BICS cited by Vargas and Nicolaidis4

appears in Figure 1, where a memory cell isthe circuit under test. Without current in thevirtual power bus (VDD and Gnd), the volt-age level on the gate of transistor T3 is VDDand that on the gate of T6 is Gnd. A chargedparticle striking the silicon can cause two sit-uations, and in both cases the voltage level onthe BICS output increases, producing a pos-

itive output. The first case is when the upsetresults from a particle that charges the drain ofa PMOS device that is off, thereby chargingthe T6 gate to a voltage greater than Gnd. Thesecond case is when the upset results from aparticle that discharges the drain of an NMOSdevice that is off, thereby discharging the T3gate to a voltage smaller than VDD.

This is an efficient solution for sequentialcircuits, but it doesnt work for combination-al logic because BICS connected to the powerline cannot efficiently differentiate internal

signals propagating through the logic fromSETs (upsets). Detecting transient upsets inthe combinational logic is much more com-plex because it requires evaluation of theintensity of the pulse generated by thecharged-particle strike. Previous work pro-

posed logic duplication, time redundancy, andextra transistors for SET detection.6 Thesemethods require costly design modification.Our method uses BICS connected to the bulkof the transistors; this reduces area, perfor-mance, and power dissipation penalties whileincreasing the efficiency of detecting SEUsand SETs in integrated circuits.

Why connect the BICS to the bulk insteadof to the power lines? When a charged particlestrikes a sensitive site in a CMOS circuit, it gen-erates a current that flows between the transis-

tors drain and the bulk. The sensitive sitessurround the reverse-biased drain junctions ofa transistor biased in the off statefor example,the drain junction of the n-channel transistorin Figure 2. The transient current pulse IP flow-ing through the pn-junction of the struck tran-sistor arises from the discharge of nodecapacitance IC and from the current conduct-ed by the transistor in the on state (ID of the p-channel transistor in Figure 2). The currentsdirection depends on whether the particle isdischarging or charging the logic node.2 The

11SEPTEMBEROCTOBER 2006

Gnd

WL WL

Bit Bit

T1

T7

T3

T5

T6

T2

T4

Out

VDD

VDD

VDD

VDD

VDD

Figure 1. The standard built-in current sensor connected to the power lines

of a SRAM cell.


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peak current induced by an energetic particlestrike is more intense at the drain-bulk junc-

tion than at the connection to the power lines.During normal circuit operation, the cur-rent flowing between a reverse-biased drainjunction and the bulk is negligible comparedwith the current peak induced by an energeticparticle hit. Consequently, a BICS connectedto a circuits bulk instead of to its power lines ismore efficient. The bulk-BICS works just likethe one shown in Figure 1, except that now theBICS analyzes the current appearing at the bulkterminal. During normal operation, the cur-rent in the bulk is approximately zero. Only

the leakage current flows through the biasedjunction, and it is still very low compared withthe current generated by charged particles. Sowhen a charged particle generates a current inthe bulk, the bulk-BICS recognizes that a SET

has occurred. Figure 3 shows the connectionof the bulk-BICS to the body ties. The circuititself connects to the power lines at the transis-tor sources, like every standard CMOS circuit,but the body ties connect to the VDD (n-wellcase) or to the ground (p-well case) through thebulk-BICS.

Figures 4a and 4b show the bulk-BICS con-nected to a sequential and a combinationalcircuit, respectively. The bulk-BICS approachrequires a dedicated BICS in each type of well(n-well and p-well). Consequently, designers

can use one BICS design for PMOS transis-tors in the n-well and another BICS designfor NMOS transistors in the p-well. EachBICS uses less area than the standard BICSthat detects SEUs in memory cells (Figure 1).In addition, the possibility of distinguishingupsets that occur in the PMOS region (out-P)from those occurring in the NMOS region(out-N) can help to precisely map the faultyregion in the circuit design. In Figures 4a and4b, the P-BICS detects 0-to-1 transitions andN-BICS detects 1-to-0 transitions.

Designers can calibrate the bulk-BICS todetect only transient current pulses that cancause a logic transition at the struck node. Weassume a SET occurs if the voltage of the logicgate output node changes by more thanVDD/2.This bulk-BICS technique represents a conser-vative approach to SET detection; it detects allSETs that might cause a soft error. However, aSET can be masked logically, electrically, or bya latching window. For these cases, in whichSETs are masked out before they reach a mem-ory element, it is necessary to combine bulk-

BICS with other techniques. Alternatively, wecan assume that every time a SET occurs, evenif it is a false positive, the system must be restart-ed or an error correction procedure invoked.

The number of BICS needed for SET andSEU detection in a given circuit is related tothe amount of area to be protected. Circuitsensitivity (load capacitance and junctioncapacitance) and body-tie density (bulk resis-tance) determine the maximum detectioncapacity. We present area overhead as the ratioof the active area occupied by BICS transistors

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BUILT-IN CURRENTSENSOR

IEEE MICRO

PMOS

NMOS

VDD

Cnode

ID

IP

IC

In (Gnd) Out (VDD)

Figure 2. Circuit-level representation of the charge deposition mechanism.

The particle hit is modeled by transient current pulse IP flowing between the

reverse-biased drain-bulk pn-junction of the n-transistor in the off state. Part

of the transient current flow comes from node capacitance (IC); the otherpart comes from VDD through the p-transistor in the on state (ID). This illus-

tration depicts the case of a particle hit at the drain junction of the n-transis-

tor in the off state.

N+

N+

P+

+ - + -

- + - ++ - + -

- + - +

+ - + -

- + - +

P-well

Out(drain)

In(gate) Gnd

(source)

GndthroughBICS

Figure 3. The body ties connect to the VDD or to the ground

through the bulk-BICS.


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to the active area occupied by the transistorsof the circuit that the BICS protects. The dis-tance from the body tie to the transistor drainlocation affects the currents resistance andtherefore the magnitude of the current pulse.Hence, the bulk-BICS has a maximum bulkresistance that it can tolerate. Bulk resistance

varies widely among different technologies;therefore, the minimum body-tie contact den-sity also varies by technology. For this reason,in the simulations we describe, we consider theimpact of the bulk resistance on SET detec-tion, and we evaluate the maximum bulk resis-tance the bulk-BICS can tolerate.


Gnd

Gnd

WL WL

BL BL

Out-N

Out-P

XOR_out

B

B B

B

A

AA

A

Out-N

Out-P

N-BICS

P-BICS

(a)

(b)

VDD

VDDVDD

VDD

VDD

VDD

VDD

VDD

VDD

P-BICS

N-BICS

Figure 4. In the bulk-BICS approach, the proposed N-BICS and P-BICS connect to the bulk ofsequential and combinational logic circuits: BICS connected to the bulk of a memory cell (a)

and BICS connected to the bulk of an exclusive-OR logic gate (b).


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A bulk-BICS embedded in memory cellsTo model the effect of an SEU, as well as to

detect its effect on the circuit, we designed abulk-BICS connected to a memory cell (as inFigure 4a) as a case-study circuit in 100-nmCMOS technology. The SPICE model is fromthe University of California, Berkeley. For this

technology, supply voltage VDD is 1.2 V andminimum transistor channel width (Wmin) isone and a half times the minimum transistorchannel length (Lmin).

7 For the memory cell,the two PMOS transistors were dimensionedwith channel length equal to Lmin and transis-tor channel width equal to 2Wmin; and the fourNMOS transistors were dimensioned withtransistor channel width equal to Wmin.

We injected a set of transient current puls-es into the memory cells sensitive sites to sim-ulate an SEU able to provoke a bit flip. We

modeled this transient current pulse by intro-ducing a double exponential current source atthe struck node:8

IP(t) = I0 [exp(t/F) exp(t/R)] (1)

where IP is the transient current pulse, I0 is thecurrent peak, F is the decay time of the cur-rent pulse, and Ris the time constant for ini-tially establishing the ion track. During thesimulations, we kept the time parameters ofthe double exponential current source con-

stant while varying I0. The temporal shape ofthe transient current generated by thecharged-particle strike is a decisive factor forthe occurrence of the bit flip.8,9

Table 1 shows the minimum current peak(minimum I0) to induce a bit flip in a mem-ory cell and to provoke bit-flip detection by

the BICS. For the results appearing in Table1, we set Rto 1 picosecond (ps) and F to 15ps. The presence of an embedded BICS, con-nected to either the power lines or the bulk,has a minor effect on the memory cells sensi-tivity. The embedded bulk-BICS makes thecircuit slightly less sensitive to an SEU becausethe minimum current peak that can provokea bit flip in the memory cell increases with thepresence of the embedded bulk-BICS. Ana-lyzing the minimum I0 bit-flip detection, wefind that the minimum current detected by

the BICS is about 20 percent less than theactual minimum current that can provoke anSEU. This is a conservative approach, and theBICS works within a safe margin of detection.Results show that the embedded bulk-BICShas higher detection sensitivity than the stan-dard BICS connected to the power lines.

Table 2 compares standard BICS and bulk-BICS in terms of performance degradation.We analyzed propagation times from high tolow and low to high transitions (tPHL and tPLH,respectively) in the write and read cycle, and

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IEEE MICRO

Table 1. Minimum current peak to induce and detect bit flips in memory cells:

Standard BICS versus bulk-BICS.

Minimum I0 to induce Minimum I0 to provoke

a bit flip (A) a bit-flip detection (A)

Device type 1 to 0 0 to 1 1 to 0 0 to 1

Memory cell 335 361

Embedded standard BICS 319 347 252 (21%) 278 (28%)

Embedded bulk-BICS 345 365 257 (25%) 217 (40%)

Table 2. Performance degradation: Standard BICS versus bulk-BICS.

Write cycle rising and

Propagation times (ps) falling times (ps)

Device type Write tPLH Write tPHL Read tPLH Read tPHL Write trising Write tfalling

Memory cell 82.2 69.6 143 143 44.5 39.6

Embedded standard BICS 85.6 (4.1%) 63 (9.5%) 151.1 (5.7%) 151.1 (5.7%) 851.3 (1,813.7%) 32.4 (18.2%)Embedded bulk BICS 81.9 (0.3%) 69.6 (0%) 143.4 (0.27%) 143.3 (0.27%) 44.3 (0.44%) 39.8 (0.5%)

PLH: propagation, low-to-high; PHL: propagation, high-to-low


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the rising and falling time during the writecycle. The performance variations observedin the SPICE simulation for the bulk-BICSare within the simulations range for numeri-cal accuracy, meaning that we can expect noperformance degradation if the bulk-BICS is

embedded in a design. Using a standard BICS,however, results in performance penalties.Table 3 compares BICS and bulk-BICS in

terms of power dissipation. The results showthat power dissipation for the standard BICSis two orders of magnitude higher than for thebulk-BICS.

A pair of bulk-BICS (N-BICS and P-BICS)can monitor SEU and multiple-bit upsets(MBUs) in a set of SRAM cells. Simulationshowed that one N-BICS and one P-BICS candetect SEUs in 128 memory cells. This means

we could connect one pair of bulk-BICS to eachmemory row to determine whether bit flips haveoccurred in a 128-bit stored data item. This isan efficient way to detect MBUs in memorycells, avoiding the need for complex error cor-rection code such as Hamming code with dou-

ble-bit correction capability or higher detectioncodes, such as Reed-Solomon code.The ratio of active area occupied by the 6

BICS transistors to active area occupied by thememory cells 768 transistors is roughly 0.18,meaning that the bulk-BICS occupies 15 per-cent of the total active area, which is accept-able for fault-tolerant circuits.

Bulk-BICS embedded in combinational logicThe 4-bit multiplier in Figure 5 exemplifies

the ability of the bulk-BICS to detect SETs in


Table 3. Power dissipation by BICS: Standard versus bulk connection method.

BICS method Power dissipation for write operation (fW) Power dissipation for read operation (fW)

Embedded standard 0.54 0.73

Embedded bulk 0.0046 0.0024

fW: femtowatt

a3b3 a3b2 a2b3 a3b1 a2b2 a1b3 a3b0 a2b1 a1b2 a0b3 a2b0 a1b1 a0b2 a0b1 a1b0 a0b0

HAHAHAFA

FAFA

FAHA

FAFA

FAFA

HA

a b

S_out

C_outFA

a b

S_out

C_out C_in

FA: full-adder cellHA: half-adder cell

M7 M6 M5 M4 M3 M2 M1 M0

Figure 5. Bulk-BICS for detecting single-event transients in a combinational circuit 4-bit multiplier.


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combinational circuits. We placed the BICS toensure detection of all SETs in all the multi-pliers sensitive nodes. A set of transient pulses,modeled as double exponential current pulsesand injected by simulation into the multipli-ers sensitive nodes, simulated SETs that couldpropagate to the outputs. By SPICE simula-tion, we generated the set of current pulsesusing Equation 1, with R= 5 ps in all simula-

tions and parametersI

0 and

F varying. Ourgoal was to model the effect of different tran-sient current pulses in the multipliers sensitivenodes for all combinations of inputs and there-by analyze the bulk-BICS detection capability.

Table 4 shows the results for a set of inject-ed transient current pulses of various shapescapable of provoking transitions from 0 to 1and from 1 to 0 in the output node M3 (Fig-ure 5). The other 4-bit multiplier outputnodes showed similar results. ND in Table 4indicates cases in which the bulk-BICS could

detect a transient pulse, but the pulse couldnot provoke an error at the output. This hap-pens only when the combined I0 and F para-meters produce very low current pulseamplitudes (around 150 to 250 A) com-bined in some cases with a very fast decline inthe exponential curve. This type of transientpulse has a high likelihood of being electri-cally masked at a subsequent gate.

The SPICE simulations show that the bulk-BICS is very efficient for SET detection, oncethe bulk-BICS has detected all SETs that couldprovoke transitions at the multiplier outputs.Bulk-BICS detects a transition to 1 when anode reachesVDD/2 or more. Figures 6a and 6bshow example SPICE simulation resultsfor1-to-0 and 0-to-1 transitions, respectivelythat occurred at 1.5 ns into the simulation time.In both cases, the BICS were able to detect theSET. The logic voltage on the P-BICS output(out-P) is high when there is no particle hit and

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IEEE MICRO

Table 4. Evaluation of bulk-BICS SET detection in a 4-bit multiplier.

0-to-1 transition 1-to-0 transition

F (ps) F (ps)

I0 (A) 10 20 30 40 50 60 10 20 30 40 50 60

150 NN NN ND ND ND TD NN ND ND ND TD TD

250 NN ND TD TD TD TD NN ND TD TD TD TD

350 NN TD TD TD TD TD NN TD TD TD TD TD

450 NN TD TD TD TD TD ND TD TD TD TD TD

550 ND TD TD TD TD TD ND TD TD TD TD TD

650 TD TD TD TD TD TD TD TD TD TD TD TD

NN: no transition and no detection; ND: no transition but detection; TD: transition and detection

Out-P

Out-N

Multiplier node wherethe particle hit occurs

Multiplier node wherethe particle hit occurs

VDD

1

0

VDD

1

00 1 2 3

VDD

1

0

VDD

1

00 1 2 3

Voltage

(V)

Voltage

(V)

(a) (b)Time (ns) Time (ns)

Figure 6. SET detection simulation results: 1-to-0 transition and detection by N-BICS (a) and 0-to-1 transition

and detection by P-BICS (b).


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low when the BICS detects a particle hit. Thelogic voltage on the N-BICS output (out-N)is low when there is no particle hit and highwhen the BICS detects a particle hit.

To measure the effect of the embedded BICSon the multipliers performance and power con-

sumption, we stimulated the multipliers inputsexhaustively and evaluated the minimum, aver-age, and maximum propagation delay. Resultsshow that the embedded bulk-BICS does notcause performance degradation. In this casestudy, the power dissipated by the set of BICSis of the same order as the dynamic power ofthe multiplier, which increases the overallpower dissipation in the protected circuit.Although the dynamic power of the circuit tobe protected depends on the switching fre-quency, the power dissipated by the BICS is

mostly static. This drawback of the BICS is notrelated, however, to its connection either to thepower lines or the bulk. We are working toreduce the BICS static power consumption,thereby decreasing the impact on power dissi-pation in the protected circuit.

As for area overhead, the 504 transistors inthe multiplier require five P-BICS and two N-BICS. The active area occupied by 70 BICStransistors represents roughly 29 percent of thetotal active area of the entire protected circuit.We use two and a half times more P-BICS

than N-BICS because PMOS transistors areapproximately two and a half times wider thanNMOS transistors. Each BICS connects toroughly the same amount of node capacitance,and we avoided connecting more than oneBICS to the same basic logic cell.

We used different values for the bulk resis-tance in various simulations so that we couldevaluate its impact on SET detection to deter-mine the maximum bulk resistance that thebulk-BICS can tolerate. Bulk-BICS detectionworks properly for bulk resistance values up to200 kOhms. As Figure 7 shows, high values ofbulk resistance introduce a delay between par-ticle hit and SET detection by the bulk-BICS.

Bulk-BICS offers an attractive means ofenhancing high-level fault-tolerance meth-ods based on fault detection and correction. Itscosts are low in terms of both area and perfor-mance degradation, and it responds quickly tosoft error detection. It can be applied, forinstance, in microprocessors with recomput-ing and pipeline refreshing capabilities. In thiscase, once a soft error is detected, the proces-sor can reexecute the corrupted instruction.Our bulk-BICS method is easy to integrate intoa standard integrated circuit design flow; nomajor changes to the original circuit topologyare required to embed the bulk-BICS for soft


0 1 2 3

Voltage

(V)

(a)

(b)

1.2

0.6

0

0

Time (ns)

0 1 2 3

Voltage

(V)

1.2

0.6

Time (ns)

= 0 kOhms

= 50 kOhms

= 100 kOhms

= 200 kOhms

Bulk resistance

Figure 7. Impact of bulk resistance on SET detection by the bulk-BICS: 1-to-0 transition anddetection by N-BICS (a) and 0-to-1 transition and detection by P-BICS (b). In all cases, the

particle hit occurs at t= 1 ns. Increasing bulk resistance increases the delay between parti-

cle hit and SET detection.


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error detection in digital systems. Our furtherresearch plans include efficient techniques torecovery from soft errors, both at the circuitand system levels. MICRO

References1. G.R. Srinivasan, Modeling the Cosmic-Ray-

Induced Soft-Error Rate in Integrated Circuits:

An Overview, IBM J. Research and Devel-

opment, vol. 40, no. 1, 1996, pp. 77-90.

2. P.E. Dodd and L.W. Massengill, Basic

Mechanism and Modeling of Single-Event

Upset in Digital Microelectronics, IEEE

Trans. Nuclear Science, vol. 50, no. 3, part

3, June 2003, pp. 583-602.

3. P. Shivakumar et al., Modeling the Effect

of Technology Trends on the Soft Error Rate

of Combinational Logic, Proc. Intl Conf.Dependable Systems and Networks(DSN

02), IEEE CS Press, 2002, pp. 389-398.

4. F. Vargas and M. Nicolaidis, SEU-Tolerant

SRAM Design Based on Current Monitor-

ing, Proc. 24th Intl Symp. Fault-Tolerant

Computing(FTCS 94), IEEE CS Press, 1994,

pp. 106-115.

5. B. Gill et al., An Efficient BICS Design for

SEUs Detection and Correction in Semi-

conductor Memories, Proc. Design,

Automation and Test in Europe(DATE 05),

IEEE CS Press, 2005, pp. 592-597.6. L. Anghel, D. Alexandrescu, and M. Nico-

laidis, Evaluation of a Soft Error Tolerance

Technique Based on Time and/or Space

Redundancy, Proc. Symp. Integrated Cir-

cuits and System Design (SBCCI 13), IEEE

CS Press, 2000, pp. 237-242.

7. Device Group at UC Berkeley, Berkeley

Predictive Technology Model, 2004; http://

www-device.eecs.berkeley.edu/~ptm.

8. G. Wirth, M. Vieira, and F. Lima Kastensmidt,

Computer Efficient Modeling of SRAM Cell

Sensitivity to SEU, Proc. IEEE Latin Amer-ican Test Workshop, IEEE CS Press, 2005,

pp. 51-56.

9. G. Wirth et al., Single Event Transients in

Combinatorial Circuits, Proc. 18th Intl

Symp. Integrated Circuits and Systems

Design, ACM Press, 2005, pp. 121-126.

Egas Henes Neto is an undergraduate studentin digital systems engineering at the Univer-sidade Estadual do Rio Grande do Sul, Gua-ba, Brazil, where he is a member of the

research group in micro- and nanoelectron-ics. His research interests include fault mod-eling, fault tolerance techniques, and radiationeffects on digital circuits.

Ivandro Ribeiro is an undergraduate studentin digital systems engineering at the Univer-sidade Estadual do Rio Grande do Sul and amember of the research group in micro- andnanoelectronics. His research interests includefault modeling, fault tolerance techniques,and radiation effects on digital circuits.

Michele Vieirais an undergraduate student indigital systems engineering at the UniversidadeEstadual do Rio Grande do Sul, where she is amember of the research group in micro- and

nanoelectronics. Her research interests includefault modeling, fault tolerance techniques, andradiation effects on digital circuits.

Gilson Wirth is a professor in the ComputerEngineering Department at the UniversidadeEstadual do Rio Grande do Sul, and head of theresearch group in micro- and nanoelectronics.His research interests include low-frequencynoise, radiation effects on circuits and devices,and analog and mixed-signal circuit design. Hehas a BSEE and an MSc from the Federal Uni-

versity of Rio Grande do Sul and a Dr.-Ing. inelectrical engineering from the University ofDortmund, Dortmund, Germany. Wirth is amember of the IEEE, the IEEE ElectronDevices Society, and the IEEE Circuits and Sys-tems Society.

Fernanda Lima Kastensmidt is a professor inthe Computer Science Department at theUniversidade Federal do Rio Grande do Sul,Porto Alegre, Brazil. Her research interestsinclude VLSI testing and design, fault effects,

fault tolerance techniques, and programma-ble architectures. She has a BS in electricalengineering and an MS and a PhD in com-puter science and microelectronics from theFederal University of Rio Grande do Sul. Sheis a member of the IEEE.

Direct questions and comments about thisarticle to Fernanda Lima Kastensmidt, Univer-sidade Federal do Rio Grande do Sul, PPGC,Instituto de Informtica, Caixa Postal: 15064,Porto Alegre, RS, Brazil; [email protected].

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