A CMOS CURRENT-MIRROR AMPLIFIER WITH COMPACT SLEW RATE ENHANCEMENT CIRCUIT FOR

LARGE CAPACITIVE 'LOAD APPLICATIONS Hoi LEE and Philip K. T. MOK

Integrated Power Electronics Laboratory Department of Electrical and Electronic Engineering

The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong, China

Tel.: (852)2358-85 17, Fax: (852)2358-1485, Email: leehoi@ee.ust.hk, eemok@ee.ust.hk

ABSTRACT A new slew rate enhancement ( S E ) circuit incorporated into

a current-nlirror amplifier. which does not affect the small-signal ffequency response of the core amplifier. is presented. With the proposed enhancenient circuit. simulation results show that more than 38 times iniprovenients in both tlie slew rate and the settling time are achieved. Experimental results show that with 28OpW power consumption. 1.7V/ps slew rate and 61011s settling time at 470pF loading capacitor. were obtained.

1. INTRODUCTION

The settling behavior of an operational amplifier is very critical as it directly affects the perforniance of the circuits using the amplifier. The settling time can be divided into tlie slewing period and the quasi-linear period [ l . 21. In particular. tlie quasi-linear period depends on the small-signal behavior of the amplifier while the slewing period depends on the large-signal behavior. For the large capacitive applications (the loading capacitor CL 2 1 OOpF). the settling time of single-stage amplifiers is restricted by its slewing period as tlie niaxiiiiuiii available current I,, to charge up the loading capacitor is linlited for a given power consumption. hi fact. the slew rate SR is given by

In order to improve the slew rate. several methods have been proposed [3-71. In this paper. a current-nlirror amplifier with a new slew rate enhancement (SRE) circuit is presented. The proposed SRE circuit differs from tlie previous works in three ways. hi order to avoid wasting power dissipation in the core amplifier during fast signal transient and placing constraints on the device size of tlie core amplifier. tlie slew enhancing current is applied directly to the output of the amplifier instead of the core amplifier. Also. tlie proposed SRE circuit is separated from the core amplifier in order to improve the design flexibility such that the minimum quiescent current and the small chip area are attained. Furthermore. in order to avoid increasing the noise and the input capacitance of the core amplifier that can degrade the PSRR of tlie amplifier. the fast

signal transition is detected by tlie load devices instead of the input transistors of the core amplifier.

The operation principle and the design considerations of the proposed SRE circuit are discussed and analyzed in Section 2 and Section 3. respectively. Simulation and nieasuremenl results of tlie current-iiirror amplifier with tlie proposed SRI5 circuit are included in Section 4 to justify the improvement in slew rate. Finally. tlie sunmiary is given ui Section 5 .

2. OPERATION PRINCIPLE The current-mirror amplifier with the proposed SRE circuit is

s h o w in Figure 1. in which the small-signal behavior of the amplifier is detenilined by transistors Ml-Ml2 while the slewing' capability is provided by transistors Mdl-MdS. In the SRE circuit. Md3 and Mdl are used to detect tlie fast input step transition. Transistors Md5 and Md2 are current sources sourcing and s u h g the dc currents to transistor Md6 and from trmsistor Mdl. respectively. hi this design. Md5 and Md2 are biased such that if they operate 111 saturation region. their drain currerits equal to I , and 1,. respectively. At the same time. Md3 and M:dl are biased with the dc currents 1: and 13. respectively. As the drains of Md5 and Md6 are tied. together. during the nomial operalion. Md5 and Md6 are in fact biased with tlie same dc current I?. mliich is much smaller than I,. As a result. Md5 is forced to operate in the triode region and the drain voltage of Md5 is pulled up to tlie positive supply voltage. Then Md7 is in the cut-off region. Sinlilarly. transistors Mdl and Md2 are biased with dc current 13, which is much smaller than I4 so that Md2 is forced to operate in the triode region and the drain voltage of MdZ is pulled down 1.0 the negative supply voltage. Then MdS is in the cut-off region. Therefore. the SRE circuit does not affect the perforniance of the core current- mirror amplifier under nomial operation.

When the amplifier is connected in unity-gain feedback configuration and a positive step voltage is applied to tlie positive input of the amplifier. the increase in tlie drain current Im causes an fiicrease in gate-source voltage of Md3 and leads to an increase in I?. When I2 is larger than I l . the drain voltage of Md5 is decreased and causes Md7 to be heavily tumed on. As a result. a huge current is generated to charge up tlie loading capacitor at the output. Wien the output voltage reaches to the value close to tlie

0-7803-6685-9/01/$10.0002001 IEEE 1-220

I

Cascode Bias Circuit Current-Mirror Amplifier Slew Rate Enhancement Circuit

Figure 1: Circuit diagram of current-nlirror amplifier with proposed slew rate enhancement circuit

final value. the gate-source voltage of Md3 is decreased back to the original value. which causes I2 to be smaller than I, again and the

source voltage of Mdl. Then I3 will be larger than I., and MdS is

W W ( 7 M d 3 ( p 4 r l l

( 3 4 3 ( 3 4 4

andb2 = - bl =y w SRE circuit is shut down. Similarly. during the negative slewing.

the drain current IM4 increases and leads to an increase in the gate-

turned on so that large current is sunk fiom the output to discharge the output capacitor.

3. DESIGN CONSIDERATIONS As the slew rate enhancement circuit supplies the large current

to the output of the core amplifier to charge and discharge the loading capacitor. it does not put constraints on the design of core amplifier with high current handling capability. Therefore the core amplifier can be optiinized independently 011 its small-signal properties such as low-frequency open-loop gain, phase margin and gain-bandwidth product. The SRE circuit only serves as a plug-in feature to the core amplifier to improve the settling-time for large capacitive load applications.

In order to avoid the SRE circuit affecting the small-signal properties of the core amplifier. the turn-on voltage V,, of the SRE circuit should be larger than the offset voltage VoE of the core amplifier. In fact. neglecting all the second-order effects the tum- on voltage is given by

11 -1,

gn,Mlbl v =- (for positive slew-rate) (2) on

and

von =- ‘4 - ‘3 (for negative slew-rate) (3) g,,M 2 b2

(4)

However. the sensitivity of the SRE circuit will be degraded when tlie V,, is too large. To optimize the design. V,, should be set to about 10 times the VOE value. In our design. V,, is set to be around 20mV-40niV for the VoS in the order of milli-volt.

The proper choice of device ratios bl and b- is important as they affect the onset of the SRE circuit. If bl and b2 are too large. the quiescent current of the SRE circuit will be increased and extra power will be wasted during normal operation of tlie amplifier. However. if bl and b2 are too small such as the biasing current of less than 2yA of each biasing branch in tlie SRE circuit. the process variations in integrated circuit fabrication will make the SRE circuit unreliable.

As the detection of the turn-on voltage of the SRE circuit depends on the current nlirrors. the issue of current matching is very important. The channel length of tlie transistors in the current mirrors should be much longer than the minimum value in order to reduce the chmiel-length modulation effect and thus to improve the current matching. Finally. the current mirrors implemented by the simple current sources are compact in size and allows the SRE circuit to be suitable for use in low-voltage low-power applications.

4. RESULTS

where gdl = g- = g,,. which is tlie transconductance of the input transistors of core amplifier M1 and M2: bl and b2 are transistor ratios given by Table 1 shows the performance parameters of the overall

amplifier obtained from the HSPICE simulations. The values are

4.1 Simulation Results

1-22 1

w/o SRE I wSRE Change

1 226yW I 259pW 1 14.6% Power Dissipation

Supply Voltage

0.017/0.017 0.6W0.72 ( CL=lnF) ( CL=lnF) 38x/42x

3 v 3 v -

I I I I

PM (CL=30pF)

I I I I

85.2" 84.9" 0.3'

4.2 Experimental Results

The proposed slew rate eidianced current-mirror amplifier was fabricated using AMs 0.6pni CMOS process with Vtn = IVtp( = 0.85V. Figure 2 shows the micrograph of the overall amplifier. The area of the overall amplifier is 0.027nmi'.

Figure 2 . Micrograph of current-mirror amplitier with the proposed s l w rate enhanceiiieiit circuit

The measureinent results of small-signal perfo"ance of the overall amplifier such as the low fiequency gain and the gain- bandwidth product GBW are almost the same as the simulated results. They verify that the proposed SRE circuit does not affect the small-signal performance of the current-mirror amplifier under normal operation condition.

Figures 3 and 4 show the transient response measurements of the overall amplifier in unity-gain feedback configuration with 1V step input. The measurement results of the transient response are summarized in Table 2. The measurement results are close to simulated results. Also both figures show that the output voltage does not exhibit overshoot in the quasi-linear region of the transient response.

Figure 3: The transient performance of overall amplifier with 1V input step and 470pF capacitive loading

I

Figure 4: The transient performance of overall amplifier with 1V input step and 1nF capacitive loading

To provide a clear picture on the improvements by the proposed slew rate eilhancement circuit. a table for the current- mirror amplifier using different slew rate enhancement circuits is shown in Table 2 for comparison. The large-signal figure of merit FOML [8] is defuied for large-signal performance.

SR.CL F O M L =-

power ( 5 )

1-222

The unit of FOM is V/ps.pFlmW. An average slew rate SR. defined as the slope between 10% and 90% of the output voltage step level, is used in the calculation. A larger figure of merit implies a better slew rate enhancement circuit. In our proposed SRE circuit, FOML above 2500 V.pF/ps.mW can be achieved for both 470pF and 1nF loading capacitors. which is an improvement to that obtained in the previous work.

0.63

0.027

5. SUMMARY

96/128 0.2W0.3 1921256

7471747 0.2 810.26 56/56 (CLZl5pF): (CLSl5pF): (CLzl5pF): -

(CL=100pF) (CL=lOOpF) (CL=lOOpF)

1.511.73 0.7910.6 1 251712903

1.4411.09 250012893 (C~=470pF): (CL=470pF): (CL=470pF):

l7P 0.710.81 (C,=lnF) (C,=lnF) (C,=lnF)

A new slew rate enhancement circuit which is targeted for single-stage amplifiers driving large capacitive loads has been presented in this paper. Operation principle and design considerations of the proposed SRE circuit are discussed. Both simulation results and experiniental results justify a significant improvenient in the slew rate and 1% settling time by using the proposed SRE circuit. Compared with other published SRE circuits. the proposed SRE circuit shows better large-signal performance with no overshoot in the transient response.

REFERENCES [ l ] B. Y. Kaniath. R. G. Meyer. and P. R. Gray. “Relationship

between Frequency Response and Settling time of Operational Amplifier.“ IEEE Joirrnal Solid-State Circuits. Vol. SC-9. pp. 347-352. Dec. 1974.

[2] C. T. Chang, “Analysis of the Settling Behavior of an Operational Amplifier,” ZEEE Journal Solid-state Circuits, Vol. SC-17, pp. 74-80, Feb. 1982.

[3]. M. G. Degrauwe, J. Rijmenants. E. A. Vittoz. and J. J. D. Man. “Adaptive Biasing CMOS Amplifiers,” ZEEE Joirrnal of Solid-state Circuits. Vol. SC-17, pp. 522-528, June 1982.

[4] R. Minke. B. J. Hosticka, and H. J. Pfleiderer. “A Very-High- Slew-Rate CMOS Operational Amplifier.” ZEEE Journal of Solid-state Circuits. Vol. 24. pp. 744-746. June 1989.

[ 5 ] K. Nagaraj, “CMOS Amplifiers Incorporating a Novel Slew Rate Enhancement Technique.“ Proceedings of the ZEEE 1990 Cirstont Integrated Circuits Conference. pp. 11.6.1- 11.6.5. 1990.

[6] B. W. Lee. and B. J. Sheu. ‘ A High-speed CMOS Amplifier with Dynamic Frequency Compensation.” Proceedings of the IEEE I990 Cirstoni Integrated Circuits Conference, pp. 8.4.1 - 8.4.4. 1990.

[7] J. Ramuez-Angulo, “ A Novel Slew-Rate Enhancement Technique for One-Stage Operational Amplifier.“ Proceedings of the 39’’’ Midwest .$tmposiirni on Circuits and $atenu. IEEE Part Vol. 1, pp. 7-10. 1996.

[SI K. N. Leung. P. K. T. Mok. W. H. Ki. and J. K. 0. Sin. ”Three-Stage Large Capacitive Load Amplifier with Damping-Factor-Control Frequency Compensation.” IEEE Joirrnal Solid-State Circuits. Vol. 35. pp. 22 1-230, Feb. 2000.

Table 2: Perfomiance summary and coniparison of different amplifiers

I I I

I I 0.88 83 O

Our Work

Results) (Measuremait I 81 1 1 (C,=30pF) (CL=30pF)

Power (niW@Vdd)

0.325@5 (Quiescent)

1 .5@5 (Trausient)

7.5

0.28@3

0.25 78 0’075 I 3’68n1 I (CL=470pF) 1 - I (CL=470pF)

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