Circuit-Aware Device Reliability Criteria MethodologyJ.T. Ryan1, L. Wei2, J.P. Campbell1, R.G. Southwick1, K.P. Cheung1*, A.S. Oates3, H.-S.P. Wong4 and J. Suehle1

1Semiconductor Electronics Division, NIST

Gaithersburg, MD USA *Kin.Cheung@nist.gov

2Microsystems Technology Laboratories, MIT Cambridge, MA USA

3TSMC Ltd. Hsin-Chu, Taiwan 300-77, R.O.C.

4Dept. of Electrical Engineering, Stanford University Stanford, CA USA

Abstract— Meeting reliability requirements is an increasingly more difficult challenge with each generation of CMOS technology. The disconnection between conventional one-size-fits-all reliability specifications and the wide range of circuit applications might be a huge waste of resources. By taking into consideration circuit-level figures of merit, a novel methodology to establish device reliability criteria that reflects real-world operation of devices in circuits is proposed and demonstrated. This “circuit-aware” methodology makes a real step toward realizing the goal of application-aware reliability standards which do not require additional measurements. The beauty is its simplicity – a simple transformation to solve an important problem. The simplicity makes it attractive as a standard methodology.

I. INTRODUCTION A critical aspect of qualifying VLSI technology for full

scale production is satisfying reliability criteria. As CMOS technology continues to advance, it is becoming increasingly more difficult for a new technology to meet all of its reliability specifications. Additionally, many of the reliability qualification specifications are based on seemingly arbitrary device parametric shifts and do not necessarily correlate with real world circuit behavior; product reliability in the field often shows no correlation with the qualification criteria. The current standard of a single device-level reliability specification, which is used to qualify all circuit applications for a particular technology, is illogical, wasteful, and painful. It makes little sense to universally trade performance for reliability or vice-versa regardless of the circuit application. Thus, there is a real and urgent need to develop reliability criteria that can reflect a particular circuit’s actual application and usage in the field [1-6].

Recently, a new circuit-aware methodology to evaluate emerging device performance in circuits was developed and demonstrated [7]. In this work, we leverage that methodology to explore a novel approach to develop a circuit-aware device reliability criteria methodology. That is, we evaluate reliability criteria for a device in terms of its real-world intended circuit functions (considering critical circuit parameters such as energy per switch and timing delay). Since the methodology does not require any additional measurements or fabrication of special test circuits, it can easily and conveniently be universally adapted across a wide range of product applications. We use one particular

reliability specification, namely hot-carrier lifetime [8], as an example to demonstrate the proposed methodology.

II. EXPERIMENTAL The devices used in this study are production quality 10

µm x 0.04 µm SiON nMOSFETs. Hot carrier stresses were performed at five different stress voltages (VStress = VD = VG) and were interrupted periodically to obtain drain current vs. gate voltage (ID-VG) curves at various values of drain bias (VD). Each ID-VG measurement was performed “forward” and “reverse” (swapping source and drain during measurement only). In all cases, the stress voltage was applied to the drain side. Hot carrier stresses degrade the drain end of the device. Thus, the “reverse” measurement is more sensitive to the degradation and is often used to monitor “worst-case” hot carrier degradation. These measurements allow hot carrier reliability analysis using the “conventional hot carrier lifetime approach” (section III) as well our new “circuit-aware reliability criteria methodology” (section IV). Please note that the pre- and post- stress ID-VG curves are the only inputs into the circuit simulation.

III. CONVENTIONAL HOT CARRIER LIFETIME ANALYSIS Fig. 1 shows a representative example of pre- and post-

stress (VD = VG = 1.45 V) ID-VG measurements illustrating the effect of hot carrier degradation. While the most commonly used hot carrier lifetime criterion is defined as a 10% saturated drain current (IDsat) (forward) degradation, this is not universal. Thus, we also examine a few other lifetime criteria that are often found in the literature including linear drain current (IDlin), threshold voltage shift (ΔVT) and maximum transconductance (Gm). Fig. 2 illustrates degradation vs. hot carrier stress time for a stress voltage of 1.35V. Shown are IDsat (2a), IDlin (2b), ΔVT (2c), and maximum Gm (2d) for forward and reverse measurements. The dashed horizontal lines denote lifetime criteria.

Figure 1: Representative ID-VG curves pre- and post-stress illustrating drain current degradation due to hot carrier damage.

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Combining this data with the results over a range of stress voltages, fig. 3 shows the voltage acceleration for all four device metrics. For a targeted operation voltage of VDD = 1 V, the extracted lifetimes are summarized in fig. 4a and 4b.

Figure 2: Device metric degradation vs. stress time for VStress=1.35 V. (a)IDsat, (b) IDlin, (c) ΔVt, and (d) max Gm. Horizontal lines denote reliability criteria.

Figure 3: Lifetime vs. 1/VStress for the four device metrics forward (a) and reverse (b). The horizontal dashed line represents a 10 year lifetime.

This exercise demonstrates how seemingly arbitrary reliability qualification can be. The above conventional hot carrier lifetime analysis indicates that the technology satisfies the 10% IDsat (forward) degradation criterion with some room to spare. What it does not show is the difference in margin for different circuit applications (i.e. in some applications this criterion is too conservative but for others it is too aggressive). The devices tested here could be used in a high performance circuit where the gates are switched frequently and the signal has to pass a long path in a restricted period of

time or in some non-critical circuit where the requirement on latency is much more relaxed. Thus, a reliability criteria methodology must be developed to reflect the way the device will be used in the final product.

Figure 4: Extracted lifetimes for the four device metric criteria forward (a)

and reverse (b) assuming an operation voltage of 1 V.

IV. NEW CIRCUIT-AWARE RELIABILITY CRITERIA METHODOLOGY

The proposed new circuit-aware reliability criteria methodology uses “standard” digital circuits to examine the effect of any mode of reliability degradation (demonstrated here with hot carrier stress) on two critical circuit parameters, namely energy per switch and timing delay (calculated following Eq. (1)-(4) in [7]). To be realistic, noise margin, parasitic capacitances, and VDD/VT variability are included in the calculation. The primary inputs are the pre- and post-stress ID-VG curves. Circuit information is extracted by activity factor, logic depth, and average fan-out which represents how frequently the device switches, how many stages the signal has to propagate in one clock cycle, and how heavy the average self-load is, respectively.

Figure 5: ΔEnergy per switch vs. additional delay for VDD = 1.0 V (a) and 0.9V (b) at various values of VStress. Clearly, energy per switch decreases and

delay increases for increasing stress voltage/time. Since energy per switch is decreasing, additional delay is the critical parameter.

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For this particular case (hot carrier in short channel nMOS), the energy per switch decreases and circuit timing delay increases with increasing stress time and voltage (Fig. 5). Thus, additional timing delay is the only parameter of concern. Fig. 6 more clearly illustrates the effect of hot carrier stress on timing delay by comparing additional timing delay (Δ Delay) vs. stress time for two different operation voltages (VDD = 1.0 V and 0.9 V). Normalizing the Δ Delay values of fig. 6 to their respective initial delay values results in the logic depth independent plot of fig. 7. These normalized Δ Delay vs. stress time plots can then be used to extract lifetimes for pre-defined percentage changes (fig. 8) or arbitrary percentage changes (fig. 9) in timing delay. Please note that this circuit-aware reliability methodology is based solely on the circuit delay (timing) budget instead of a singular parametric shift.

Figure 6: Additional delay vs. stress time for the different stress voltages. Shown are VDD = 1.0V (a) and 0.9V (b).

Focusing on the 1 V (blue triangle) result of fig. 9a, we see that the 10 year lifetime is right at 10% timing degradation. In other words, if a circuit’s critical timing budget can tolerate 10% degradation (a 10% increase in additional delay), it will have 10 years or longer hot carrier lifetime. For circuits with tighter critical timing budgets, the technology will not meet 10 years lifetime. In other words, technologies targeted for different performance or applications can now have different reliability criteria allowing designers to intelligently trade performance for reliability or vice versa.

Fig. 7: ΔDelay from fig. 6 normalized to initial delay vs. stress time for the different stress voltages. Shown are VDD = 1.0 V (a) and 0.9 V (b).

Figure 8: Lifetime vs. 1/Vstress with timing degradation (ΔDelay/Initial Delay) as the reliability criteria for VDD of 1.0 V (a) and 0.9 V (b). For circuits with different timing degradation allowances, the lifetimes can be very different.

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Figure 9: Hot carrier lifetime vs. timing degradation (ΔDelay/Initial Delay) for two values of VDD. Different circuit applications will have different

lifetimes depending on their timing degradation allowances.

V. DISCUSSION Since only pre- and post-stress ID-VG curves (plus a few

other common parameters that are technology specific) are used, no additional measurements are required for the simulation. This circuit-aware reliability methodology can be used for any degradation mode; the basic acceleration model of each mode of stress is unchanged. What is changed is the way failure criterion is extracted. No longer is the technology bounded by a single, seemingly arbitrary, reliability lifetime criterion. The reliability qualification can now become application specific avoiding all the pitfalls associated with the conventional approaches. While timing degradation is demonstrated here as a failure criterion for hot carrier stress, change in energy per switch can also be used if it is a concern. Again, the failure criteria can easily be application specific. In some cases, the combination of energy and delay may be used. Furthermore, the simulation also supports re-optimization of the circuit to buy more reliability margin if VDD and/or VT are allowed to be adjusted [1].

A key question for this “circuit-aware” approach is what constitutes a standard circuit? It is conceivable that this can be agreed upon by a standards body. Additionally, more than one standard circuit is also possible, making the methodology even more realistic and universal. In the extreme case, the circuit(s) can be customer specified to more accurately portray the final product.

VI. CONCLUSIONS In summary, we demonstrated, using hot carrier

degradation as an example, a novel methodology to transform traditional device reliability criteria to one that reflects the real world operation of devices in circuits. The methodology allows for adjustments based on actual circuit applications. Since it does not require any additional measurements or fabrication of special test circuits, it can easily and conveniently be universally adapted across a broad range of products. Additionally, it does not require any change in stress methodology or acceleration model. Rather, it passes the pre- and post-stress data through a realistic circuit simulator to extract the degradation of the critical parameters

most important to a particular circuit’s operation. The methodology can lead to greater reliability criteria flexibility based on a circuit design’s intended real-world function.

ACKNOWLEDGMENTS

J.T.R. and R.G.S. acknowledge funding support by the National Research Council. L.W. is partially supported by the MSD Focus Center of the Focus Center Research Program (FCRP).

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