Photonics - Electronics Integration on CMOS

Laurent Fulbert, Jean-Marc Fedeli CEA, LETI, MINATEC Campus, Grenoble, France

laurent.fulbert@cea.fr

Abstract— Silicon photonics has generated an outstanding interest for optical communications and for inter and intra-chip interconnects in electronic systems. High performance generic building blocks that can be used for a broad range of applications have already been demonstrated such as waveguides, I/O couplers, laser sources by III-V/Si heterogeneous integration, fast silicon modulators and germanium photodetectors. The paper will also review the different scenarios for integrating photonic functions with an electronic circuit, as well as the associated design, test and packaging challenges.

I. INTRODUCTION For more than 30 years, the optical interconnects solutions

were gradually implemented from very long to shorter distances. It began with long distance telecommunications networks (>10km) and then progressed to metro access networks (>1km) and enterprise LAN backbones (>100m). This transition towards optical interconnects solutions at short distances results from the difficulty to make electrical conductors cope with problems such as signal attenuation, dispersion and crosstalk which grow both with data rate and reach. Compared to electrical interconnects solutions for high-speed links, the optical solutions offer several demonstrated advantages such as lower signal attenuation, longer reach, higher bandwidth, and lower media cost. Another significant advantage of optical solutions is the immunity of the signals transmission to electromagnetic interference which makes them very well suited to mobile systems. However, optical links still cost much more than electrical links, and very short reach applications require very high volume production capability and low cost of the links.

Hence, silicon photonics generates an increasing interest for optical telecommunications and for optical interconnects in microelectronics circuits. Indeed this approach offers a solution to manufacture affordable optical links using Complementary Metal Oxide Semiconductor (CMOS) fabrication lines [1][2]. By co-integrating optics and electronics on the same chip, high-functionality, high-performance and high integrated devices can be fabricated using a well-mastered microelectronics fabrication process. Thus it will allow manufacturers to build optical components using the same semiconductor equipments and methods they use for microelectronics integrated circuits. The ultimate goal is to monolithically integrate optical transceivers or circuits

into silicon integrated circuits (IC) chips. Recent developments have already shown the integration of several elementary optical functions into nanophotonic silicon circuits such as laser emission, detection, modulation, multiplexing, demultiplexing, fiber coupling [3].

Silicon Photonics holds the promise of being the technology platform that enables cost-effective, automated volume manufacturing of a large variety of photonic components, circuits and systems. In order to be able to reuse the high yield, high volume microelectronics tools and fabs, a complete value chain is under construction. It concerns:

• A design methodology and flow for the integration of photonics on CMOS, including modeling tools for photonic devices and circuits compatible with EDA abstraction levels and libraries of photonic function models.

• The development of standardized, high performance building blocks: laser sources by III-V/Si heterogeneous integration, fast modulators and detectors, passive circuits and I/O couplers

• The process flow for photonic-electronic integration, developed to be compatible with commercial fabs and tools.

• Packaging solutions to address new challenges related to electrical, RF, optical and thermal issues.

II. PHOTONIC BUILDING BLOCKS

A. Laser source The integration of lasers with silicon photonic-electronic

circuits is considered as one of the major challenge. The complexity lies in the fact that silicon is a poor light-emitting material due to its indirect energy bandgap. In addition, the direct growth of standard III-V materials on Si substrates is still a major obstacle because of the mismatch in lattice constants and in thermal expansion coefficients [4]. A different approach consists in combining III-V hetero-structures to silicon waveguides. It is based on die to wafer bonding of III-V material on top of a patterned Si-on-Insulator (SOI) substrate [5].Then, hybrid Si/III-V lasers are realized following a collective fabrication procedure, enabling complex photonic integrated systems onto the silicon

978-1-4577-0704-9/10/$26.00 ©2011 IEEE 13

platform. Using this technology, Fabry–Perot [6][7], racetrack [8] and distributed feedback lasers [9] were demonstrated.

The hybrid cavity consists of a III-V heterostructure used only as gain material while the cavity lies in the silicon region. The III-V heterostructure (InP stack) is placed only at specific locations on the wafer by die-to-wafer bonding. The strong point is that it reduces the cost of the integration process since expensive III-V stacks can be bonded only where they are needed (Fig. 1).

Figure 1. Image of an InP die on silicon photonics circuit with SiO2 molecular bonding

After molecular bonding, mechanical grinding and InP chemical etching are performed in order to leave the thin heterostructure on the waveguide layer with a controlled SiO2 separation layer. Decontamination steps of the rear side of the wafers are required before the introduction of the wafers in a microlectronics fab at the back-end level. With DUV lithography, fine patterns can be defined with high alignment accuracy with respect to the waveguide layer. Then etching of InP in 200mm format is performed using reactive ion etching (RIE) with CH4/H2 gases as the thin thickness of the heterostructure requires low etching speed. The InP structures are then cladded with a thick silica layer and the wafers are chemically polished in order to leave a thin layer of silica on top the laser diodes. By opening the silica layers, contact with all the semiconductor layers and the last metallizations layers of the electronic circuit can be performed. CMOS compatible contacts on InP (Ti/TiN/AlCu) were used as gold is forbidden is 200mm microelectronics clean room (Fig. 2). The same metallization is provided to take the contacts on the implanted area for modulators and on doped area for the Germanium PIN photodiodes.

Figure 2. (a) Cross-sectional SEM image of a hybrid structure before

metallization. (b) Top-view optical microscope image of a final fabricated Si/III-V laser

We have reported the use of direct bonding with high quality transfer for the fabrication of a hybrid Si/III-V laser based on the supermode control of a two coupled waveguides system [8]. The proposed architecture, presented in Fig. 3, allows a larger tolerance on the bonding layer thickness (that can be > 100nm), relaxing the integration process..

Figure 3. Top and side view schematic representation of the hybrid Si/III-

V laser

Fig.4 shows the measured laser peak power intensity as a function of injected current and temperature. The lasing wavelength is around 1570 nm with a side-mode suppression ratio as high as 20dB. Under direct modulation, the measured bandwidth is around 8GHz.

P-contact

N-contact

III-V/Si active region Si waveguide

Gain region

Surface-grating couplerDBR

Mode transformer

Feed-back

Side view

Top view

To fiberInP

Si waveguide

R>90% R~50%

14

0 100 200 300 400 500 6000

1

2

3

4

5

6

7

80 1 2 3 4 5 6 7 8 9 10

0

1

2

3

4

5

6

7

8

J(kA.cm-2)

20°C 30°C 40°C 50°C

Lou

t-Fi

ber(

mW

)

I (mA)

Figure 4. Laser output power

B. Modulators During the last decade, silicon optical modulators based

upon free carrier manipulation have emerged as an attractive means for high data rate transmission and have undergone a period of rapid development. Until 2004, devices generally reported bandwidths limited to the MHz regime, due to the relatively large device dimensions and the use of carrier injection to electrically control the effective index of the propagating optical mode. Many silicon based optical modulators reported recently use techniques which are not limited by minority carrier lifetimes (carrier depletion or carrier accumulation) and have demonstrated performances which are compatible with data transmission rates of 10Gbit/s [10] and 40Gbit/s [11].

The modulator comprises a phase shifter (or phase modulator) inserted in a Mach-Zehnder interferometer. Different designs have been evaluated, such as thick modulators (ie. using 400nm thick SOI) [12] or thin modulators (ie. using 220nm thick SOI). A diagram of the phase shifter cross-section is shown in Fig.5.

Figure 5. PN modulator in 220nm SOI

Recently, silicon based devices of lengths of 3.5mm and 1mm operating at 40Gbit/s have been demonstrated with extinction ratios of up to 10dB and 3.5dB respectively. The efficiency and optical loss of the phase shifter is 2.7V.cm and

4dB/mm (or 4.5dB/mm including waveguide loss) respectively [13].

C. Photodetectors Integrated photodetector is one of the main building blocks

for silicon photonic applications for either monitoring or high speed detection. The heterogeneous integration of InGaAs layers on silicon has been one of the integration scheme followed for fabricating photodiodes [14]. Monolithic integration through germanium epitaxial growth on SOI has reached a high level of maturity [15].

For this purpose, germanium (Ge) is exploited thanks to its strong absorption coefficient in the near infrared. Fig. 6 shows a vertical pin Ge photodetector integrated in submicron SOI rib waveguide. Since butt coupling configuration is considered, the detector length to totally absorb incident light at the wavelength of 1.55 µm, is reduced down to 15 µm. Such a waveguide detector uses a process fully compatible with CMOS technology. Responsivity as high as 1 A/W under -4V and dark current density as low as 60 mA/cm² have been obtained, as well as an open eye diagram at 40 Gb/s under -4V bias.

Figure 6. Schematic view of vertical pin Ge-on-Si diode integrated in rib

waveguide

D. Passive waveguides The propagation of the light in a silicon circuit can be done

using either rib (partial etching of the silicon film) or strip (full etching of the silicon film down to the buried oxide film) waveguides. The latter allows achieving the highest compactness of the optical mode but propagation losses are higher than those obtained with rib structures. Numerous studies have been done on both kinds of waveguides. Most of the strip waveguides studied in the literature have a height of about 220 nm and a width lower than 500 nm to have single mode propagation [16][17]. Most of the key functions required for making complex circuits have been demonstrated: splitters, junctions, ring resonators, wavelength multiplexers and demultiplexers such as Arrayed Waveguide Gratings (AWG).

III. ON CMOS PHOTONIC LAYER INTEGRATION The ultimate goal of silicon photonics is to monolithically

integrate a photonic layer with optical functions onto silicon IC chips [18].

Several full integration schemes are considered, and two are, described in Fig. 7: (i) back-end integration, i.e. 3D

15

integration of photonic layer in between metallic interconnects layers, (ii) combined front-end fabrication, i.e. integration of photonic function at the transistor level.

Figure 7. Photonic layer integration on CMOS.

The combined front-end approach has already been demonstrated [19]: both the photonics fabrication and the transistors fabrication are combined at the front end level. Photonics and electronics structures share the chip footprint leading to moderate integration density. The thermal budget then rules the process steps and is compatible with rather high temperature process such as Germanium epitaxy in order to implement high speed photodetectors. The back-end process is common to electronics and photonics. In this approach, an external laser source is flip-chip bonded.

As shown in Fig. 8, 3D integration process where the photonic layers are embedded into the last levels of metallization above the IC layer is very versatile.

transistormetal

FC Modulator AWG Ge PDInP sou rce PAD

CMOSwafer

Figure 8. Illustration of a photonic layer integration at the last levels of metallization above the IC layer.

One of the main advantages of this integration scheme is the ability to integrate all the photonic circuits on a CMOS/BiCMOS wafer using 3D integration techniques, not depending on the specific node used to produce the electronic wafer and using only standard CMOS/BiCMOS processes. Hence standard libraries and processes are used for the fabrication of the electronic IC.

IV. I/O COUPLING AND PACKAGING Silicon nanophotonic circuits exhibit a very high level of

functional integration due to the very small cross sections of

the silicon waveguides with less than 1µm mode field diameter (MFD). However, to be implemented in data optical transmission networks, such circuits still must be interfaced with optical fibers having much larger dimensions with about 10µm MFD. Due to this mismatch in size, a specific coupling structure is required in order to minimize the coupling losses between a wide fiber mode and a narrow silicon wire mode. Another issue is the polarization management: in their topology, silicon waveguides are generally highly birefringent, and in the other hand polarization in fiber-based networks is unpredictable and varies randomly with time. However, in order to be compatible with telecoms and datacoms applications, the coupling structure must be broadband and non sensitive to polarization

The insertion loss between an optical fiber and a nanophotonic circuit is key parameter that impacts directly the link performances such as reach or signaling rate. Finally, beyond the performance, the selection of the coupling structure is also related to the manufacturing cost by considering wafer-level testing capability, fibers assembly and thermal management. Experimentally, two main solutions have already been implemented, each one having some significant advantages but also significant drawbacks: edge fiber coupler with adiabatic inverse tapers and surface fiber coupler with gratings.

The most efficient edge fiber coupler today is a spot-size converter that gradually transforms a highly confined mode into a wider mode supported by a low-index-contrast waveguide such as an optical fiber. The mode size converter reported in [20] is constructed from SOI wafers with a two-dimensional tapered Si wire and an overlaid high-index silicon-rich oxide (SiOx) waveguide. As shown in Fig. 9, the coupling efficiency remains high in a broad spectral range: the bandwidth at 1dB is around 100nm (> 300nm at 3dB) for both TE/TM polarization states. We can also notice that less than 1dB coupling losses were measured at 1550nm.

Figure 9. Coupling efficiency measured as a function of the wavelength.

Grating couplers lead to a vertical or quasi-vertical optical coupling of the light between a fiber and a nanophotonic circuit. In this way, they can be located anywhere over the chip and not only at the edge. So, compared with edge coupling structures, such surface couplers allow light coupling

Option 2 Combined front -end

fabrication

Option 1 Photonic layer at the last levels of metallizations withback -end fabrication

16

without the need for dicing and polishing the chip edge, which also makes wafer-scale testing of nanophotonic circuits possible. That is the reason why grating couplers may appear to be one of the most relevant fiber coupling structures for silicon photonics devices today. However, the high sensitivity of those structures to the operating wavelength and to the polarization state may limit their practical use.

Using typical photonic SOI wafers with 220nm thick silicon layer state of the art of 1D grating couplers exhibit between 40% to 50% fiber coupling efficiency [21]. For these optimized designs, the Buried Oxide (BOX) layer thickness is optimized in order to generate constructive reflection from the silicon substrate of the transmitted beam through the grating. This contribution may also be enhanced by increasing the reflection ratio using a bottom mirror such as a single metallic layer or a multilayer Bragg mirror [22].

Pros and cons of these two main architectures are summarized in the Table 1.

TABLE I. COMPARISON OF SURFACE AND EDGE COUPLING ARCHITECTURES (FROM [23])

Lateral (inverted taper)

Vertical (Grating coupler)

Coupling loss to Single Mode Fiber (SMF) (flat cleaved fiber, butt coupled)

-7dB (single stage) -1.5 dB (double stage)

-4.5 dB (standard grating) -1 dB (optimized grating)

Coupling loss to SMF (lensed fiber)

-1 dB (best) -3 dB (typical)

1dB tolerance (radial offset)

+/- 0.3 µm (single stage)

+/- 2µm

3 dB bandwidth Broadband 60 nm Polarization dependance

Weak Strong

Suitable for multiple I/O

In array on the edges In matrix on the surface

CONCLUSION Photonic electronics integration has been sketched and

some of the key processes highlighted. Most of the elementary photonic building blocks, such as laser source, modulator, photodetector, passive waveguide and I/O coupling structures are now available, with performances meeting the applications requirements. Already 40G modulator and 40G Ge photodetector have been achieved. Moreover InP on Si laser fabrication with 200mm processing in microelectronics clean room have been achieved for applications with embedded laser either for off-chip or for on-chip connections.

The complete technology platform, including design flow, process integration, tests and assembly is under construction. It will enable a cost-effective, volume manufacturing of silicon photonic integrated circuits for a wide range of applications.

ACKNOWLEDGMENT This work received funding from the European

Community's Seventh Framework Program (FP7/2007-2013) under grant agreements n° 224312 HELIOS and WADIMOS.

All the teams working on these projects are acknowledged for their active contribution.

REFERENCES [1] J.M. Fedeli, R. Orobtchouk, C. Seassal, L. Vivien, "Integration issues

of a photonic layer on top of a CMOS circuit", Proceedings of SPIE 6125, (2006)

[2] R. Baets, P. Dumon, W. Bogaerts, G. Roelkens, D. Taillaert, B. Luyssaert, G. Priem, G. Morthier, P. Bienstman, D. Van-Thourhout, "Silicon-on-insulator based nano-photonics : Why, How, What for?", 2nd IEEE International Conference on Group IV 05EX1053, 168-170 (2005)

[3] J.M. Fedeli, M. Migette, L. Di Cioccio, L. El Melhaoui, R. Orobtchouk, C. Seassal, P. RojoRomeo, F. Mandorlo, D. Marris-Morini, L. Vivien, "Incorporation of a Photonic Layer at the Metallizations Levels of a CMOS Circuit", 3rd IEEE International Conference on Group IV Photonics, 200-202 (2006)

[4] H. Kromer, T.-Y. Liu, and P. M. Petroff, J. Cryst. Growth, 95, 96 (1989).

[5] M. Kostrzewa, L. Di Cioccio, M. Zussy, J.C. Roussin, J.M. Fedeli, N. Kernevez, P. Regreny, C. Lagahe-Blanchard, B. Aspar, Sens. Act. A, 125, 411 (2006)

[6] A. W. Fang, H. Park, O. Cohen, R. Jones, M. J. Paniccia, and J. E. Bowers, Opt. Express, 14, 9203 (2006).

[7] X. Sun, A. Zadok, M. J. Shearn, K.A. Diest, A. Ghaffari, H.A. Atwater, A. Scherer, and A. Yariv, Opt. Lett., 34(9), 1345 (2009).

[8] A. W. Fang, R. Jones, H. Park, O. Cohen, O. Raday, M. J. Paniccia, and J. E. Bowers, Opt. Express, 15, 2315 (2007).

[9] A. W. Fang, E. Lively, Y.-H. Kuo, D. Liang, and J. E.Bowers, Opt. Express, 16, 4413 (2008).

[10] F. Y. Gardes, A. Brimont, P. Sanchis, G. Rasigade, D. Marris-Morini, L. O'Faolain, F. Dong, J-M. Fedeli, P. Dumon, L. Vivien, T. F. Krauss, G. T. Reed and J. Martí “High-speed modulation of a compact silicon ring resonator based on a reverse-biased pn diode,” Opt. Express, 17(24), 21986-21991, (2009).

[11] L. Liao, A. Liu, D. Rubin, J. Basak, Y. Chetrit, H. Nguyen, R. Cohen, N. Izhaky and M. Paniccia et al. “40 Gbit/s silicon optical modulator for high speed applications” Electronics Letters, 43(22), 1196-7, (2007).

[12] G. Rasigade, D. Marris-Morini, M. Ziebell, E. Cassan, and L. Vivien, "Analytical model for depletion-based silicon modulator simulation," Opt. Express 19, 3919-3924 (2011)

[13] D. J. Thomson, F. Y. Gardes, Y. Hu, G. Mashanovich, M. Fournier, P. Grosse, J-M. Fedeli, and G. T. Reed, "High contrast 40Gbit/s optical modulation in silicon," Opt. Express 19, 11507-11516 (2011)

[14] Van Thourhout, D.; Spuesens, T.; Selvaraja, S.K.; Liu Liu; Roelkens, G.; Kumar, R.; Morthier, G.; Rojo-Romeo, P.; Mandorlo, F.; Regreny, P.; Raz, O.; Kopp, C.; Grenouillet, L.; , "Nanophotonic Devices for Optical Interconnect," Selected Topics in Quantum Electronics, IEEE Journal of , vol.16, no.5, pp.1363-1375, Sept.-Oct. 2010

[15] L. Vivien, J Osmond, J-M Fédéli, D Marris-Morini, P Crozat, J-F Damlencourt, E Cassan, Y.Lecunff, S Laval, 42 GHz p.i.n Germanium photodetector integrated in a silicon-on-insulator waveguide, Optics Express 17 (2009).

[16] Yurii A. Vlasov and Sharee J. McNab, Optics Express 12, 1622-1631 (2004).

[17] W. Bogaerts, D. Taillaert, B. Luyssaert, P. Dumon, J. Van Campenhout, P. Bienstman, D. Van Thourhout and R. Baets, V. Wiaux, S. Beckx, Optics Express 12, 1583-1591 (2004).

[18] Fedeli-J-M, “Si and InP integration in the HELIOS project”, 2009-35th-European-Conference-on-Optical-Communication-ECOC. 2009: 3 pp, (2009)

[19] Pinguet-T et al, “Monolithically integrated high-speed CMOS photonic transceivers”, 5th-IEEE-International-Conference-on-Group-IV-Photonics-GFP, p362-4, (2008).

[20] B. Ben Bakir, A. de Gyves, R. Orobtchouk, P. Lyan, C. Porzier, A. Roman, J-M. Fedeli, “ Low-Loss ( < 1 dB) and Polarization-Insensitive

17

Edge Fiber Couplers Fabricated on 200-mm Silicon-on-Insulator Wafers” Photonics Technology Letters, IEEE, Volume: 22 , Issue: 11, 739 – 741 (2010)

[21] Taillaert D. et al., “Grating Couplers for Coupling between Optical Fibres and Nanophotonic Waveguides”, Japanese Journal of Applied Physics, Vol. 45, No. 8A, 6071–6077, 2006

[22] F. Van Laere, G. Roelkens, J. Schrauwen, D. Taillaert, P. Dumon, W. Bogaerts, D. Van Thourhout, R. Baets, “Compact grating couplers

between optical fibers and Silicon-on-Insulator photonic wire waveguides with 69% coupling efficiency”,OFC 2006, United States, p.PDP15 (2006)

[23] Kopp, C.; Bernabé, S.; Bakir, B. B.; Fedeli, J.-M.; Orobtchouk, R.; Schrank, F.; Porte, H.; Zimmermann, L.; Tekin, T.; , "Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging," Selected Topics in Quantum Electronics, IEEE Journal of , vol.17, no.3, pp.498-509, May-June 2011

18