A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter

S.M.Kashmiri, S.Xia, and K.A.A.Makinwa Electronic Instrumentation Laboratory / DIMES

Delft University of Technology Delft, The Netherlands

E-mail: S.M.Kashmiri@TUDelft.NL

Abstract— The design of a CMOS temperature-to-digital converter (TDC) is presented. It operates by measuring the phase shift of an electrothermal filter (ETF), which is a function of the temperature-dependent thermal diffusivity of bulk silicon. Compared to previous work, this TDC employs an improved ETF, whose layout has been optimized to minimize the phase spread caused by lithographic inaccuracy. Furthermore, the TDC’s front-end consists of a gain-boosted transconductor, whose wide bandwidth minimizes electrical phase spread. The resulting current is then digitized by a phase-domain ΣΔ modulator. The phase-subtracting node of the modulator is realized by a chopper demodulator, whose switching action, however, will give rise to a residual offset current. This is minimized by locating the demodulator at the virtual grounds of the transconductor’s gain boosting amplifiers. Any residual offset is then eliminated by chopping the entire front-end. Measurements on 16 samples show that the TDC has an untrimmed inaccuracy of less than ±0.4ºC (3σ) over the military range (-55°C to 125°C).

I. INTRODUCTION In earlier work [1, 2], it has been shown that absolute

temperature can be accurately determined by measuring the phase shift of an integrated electrothermal filter (ETF). Using this approach, a temperature-to-digital converter (TDC) with an untrimmed inaccuracy of ±0.5ºC has been realized [3]. This compares very favorably with the inaccuracy of untrimmed, band-gap temperature sensors, which is in the order of ±3ºC.

An integrated ETF consists of a heater and a (relative) temperature sensor realized in close proximity on the same silicon substrate. AC power dissipation in the heater causes local temperature variations, which the sensor then converts back into electrical AC signals. Since the rate at which heat diffuses through the substrate is finite, the sensor’s output will be phase shifted with respect to the heater’s power dissipation. This phase shift is a function of the filter’s geometry and of the temperature-dependent thermal diffusivity of the silicon substrate [4]. Since the thermal diffusivity of the substrate is insensitive to process spread [2, 5], the spread in an ETF’s phase shift will be mainly determined by lithographic

inaccuracy, which can be minimized by optimizing its layout [6] and by making its critical dimensions sufficiently large.

In an ETF-based TDC, another important source of error is the electrical phase spread introduced by its front-end. In principle, this can be minimized by maximizing the front-end’s nominal bandwidth. However, this must be done in a power efficient fashion, in order not to incur significant self-heating errors.

In this work, a new TDC front-end is described. It consists of a wide-band gain-boosted transconductor, which converts the ETF’s output voltage into a current. The phase-shift of the resulting current is then digitized by a phase-domain ΣΔ modulator [3]. Compared to the multi-stage preamplifier used in previous work, this front end provides significantly higher bandwidth (115MHz vs. 25MHz) at roughly the same current consumption. To exploit the expected improvement in TDC accuracy, the new front-end has been combined with an improved ETF, whose layout has been optimized to minimize phase spread due to lithographic inaccuracy [6].

In the next section, the optimized ETF is described. Section III provides an overview of the implemented TDC. The circuit design is described in section IV, while the measurement results are presented in section V. The paper ends with conclusions.

II. OPTIMIZED ELECTRO THERMAL FILTER The layout of the optimized ETF is shown in Fig. 1. Like a

previous ETF [3], it consists of an n+ diffusion heater, which is surrounded by a thermopile made of p+ diffusion/Aluminum thermocouples. However, its layout has been optimized to maximize the SNR at the thermopile’s output, to maintain the same phase-shift at 100 kHz, and to minimize the sensitivity of this phase-shift to lithographic errors [6].

For the same power dissipation, reduced heater area will result in higher temperatures, and so, a folded heater was used. In addition, the thermopile’s “hot” junctions were located on a roughly circular, constant phase-shift contour. This maximizes

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the thermopile’s output amplitude, since this is proportional to the sum of the phase-shifted temperature variations at these junctions. Finally, the length of each arm, and hence its thermal noise contribution, was chosen to maximize the SNR at the thermopile’s output. Compared to the ETF of [3], these considerations allowed the number of thermocouples, and hence the ETF’s signal output, to be increased from 20 to 24.

Figure 1. Layout of the optimized ETF

Simulations show that at a driving frequency of 100 kHz and for the same lithographic inaccuracy, the optimized ETF exhibits 20% less phase spread than the ETF of [3]. In addition, its output SNR is 50% higher.

III. SYSTEM DESIGN A block diagram of the implemented TDC is shown in Fig.

2. Here, the optimized ETF is driven at a constant frequency fdrive by a square-wave derived from a crystal oscillator. Its output is then a small (sub-millivolt) AC signal, which is phase-shifted with respect to the square-wave. This signal is then converted into a current by the wide-band transconductor gm, and then digitized by a phase-domain ΣΔ modulator.

The phase-domain ΣΔ modulator consists of a chopper demodulator, an integrator (Cint), a quantizer and a single-bit phase DAC. Depending on the output of the quantizer, the chopper demodulator will be driven by one of the two digitally phase-shifted versions of fdrive, fdrive(φ0) and fdrive(φ1), output by the phase DAC. The chopper demodulator acts as the modulator’s summing node, and outputs a current whose DC

component is proportional to the difference in phase between the transconductor’s output current and the output of the phase DAC. This DC component is then integrated by the capacitor Cint, which acts as the modulator’s loop filter. The capacitor also filters out the harmonics of fdrive that are present at the output of the chopper demodulator. The voltage across the capacitor is then boosted by a differential-to-single-ended amplifier, which drives a digital latch in an off-chip FPGA. The latch thus serves as the modulator’s quantizer.

Due to the charge injection mismatch of the demodulator’s CMOS switches, and to the fact that a net DC current is required to establish a switching waveform across the parasitic capacitances at its input, there will be a significant DC offset current at the output of the demodulator. As in [3], this source of error can be eliminated by chopping the entire front-end (including the ETF) at a frequency fch (20Hz), which is much lower than fdrive (85 kHz).

Since the modulator is of 1st order, the bitstream was decimated by a 1st-order sinc filter, with a length of N/fch, where N is an integer, so that its notches perfectly eliminate the ripple caused by the low-frequency chopping. The decimation filter also sets the system bandwidth, and thus filters out most of the thermopile’s wide-band noise.

The ETF’s phase-shift is a near-linear function of temperature [3], and so achieving a resolution of 0.1ºC (in line with the expected accuracy) over the military temperature range means that the phase-domain ΣΔ modulator must have a resolution of at least 12-bits. Since the modulator’s over-sampling ratio can be made quite large, its resolution will be mainly limited by the leakage of its passive integrator, which, in turn, is determined by the finite output impedance of the transconductor. To achieve sufficient resolution, the transconductor’s output impedance was increased by the use of gain boosting. As will be discussed in the following section, the CMOS switches of the demodulator can then be advantageously located at the virtual grounds established by the gain-boosting amplifiers. This significantly reduces the magnitude of the DC offset current at the output of the demodulator.

Figure 2. System overview

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IV. CIRCUIT DESIGN As discussed above, the input transconductor should be

designed to have wide bandwidth and high output impedance. To achieve this, the transconductor was implemented as a gain-boosted folded-cascode amplifier, with a PMOS input pair, and an embedded chopper demodulator (Fig 3). In order to compare the performance of the old ETF with that of the optimized ETF, two PMOS input pairs were connected in parallel. By multiplexing their tail currents, one of the two ETFs can be selected. The transconductance of each input pair is 300μS, which ensures that its noise contribution is negligible compared to the noise associated with the thermopile’s resistance (20kΩ).

Figure 3. The wide band transconductor

Simulations show that over temperature and process, the amplifier has a unity-gain BW greater than 115MHz and a corresponding phase-shift spread of less than 0.05 degrees at fdrive = 85kHz. Although this corresponds to a temperature-sensing inaccuracy of only 0.2°C, it should be noted that the phase spread within a batch should be significantly smaller. Furthermore, the amplifier’s simulated DC gain is greater than 140dB, which corresponds to an output impedance of more than 33GΩ. With Cint = 70pF, a 2Hz signal bandwidth, and a 2.67 kHz sampling frequency, this means that the dead bands associated with integrator leakage are no wider than 0.02ºC.

The demodulated DC current applied to Cint will be in the order of a few tens of nano-Amperes. This means that any DC error currents must be reduced to the pico-Ampere level. The chopper demodulator is itself a major contributor of such error currents. This is because any DC voltage across its output (e.g. due to the offset of the cascode transistors) will, because of its switching action, periodically charge and discharge the parasitic capacitance Cpar (e.g. associated with the current sources and the PMOS input stage) at its input nodes. The resulting currents are then rectified by the chopper itself and cause a net DC offset current Ioff at its output [8]. For an output voltage Voff and a chopping frequency fch:

Ιoff = 4fchCparVoff (1)

To minimize Ioff, the parasitic capacitances at the high impedance input nodes of the chopper demodulator should be shielded from the DC voltage across its outputs. As shown in Fig. 4, a suitable location for the chopper is between the source terminals of the cascode transistors and the input terminals of the booster amplifiers. This way, the booster amplifiers will establish a virtual ground at the high impedance, high capacitance, folding nodes of the main amplifier. The output of the boosters must then also be chopped in order to maintain the correct feedback polarity. This technique has two advantages. Firstly, fixing the chopper’s input nodes at virtual ground reduces the magnitude of Ioff by three orders of magnitude (from simulations), compared to the situation when the choppers are located outside the gain-boosting loop. Secondly, chopping the booster’s output means that the contribution of its offset (and 1/f noise) to the amplifier’s output current is also chopped. As discussed previously, any remaining residual offset current is then cancelled by chopping the entire front end [9].

Figure 4. Chopping at virtual ground nodes of the booster

Since the signal across Cint is too small to drive an off-chip latch, it is buffered by a differential to single-ended amplifier with a gain of 40dB. The output of this amplifier is a rail-to-rail signal, which drives an off-chip FPGA latch (Fig. 2). As described in [2], heater drive inversion (HDI) is used to minimize the effect of capacitive cross talk in the ETF.

V. MEASUREMENT RESULTS The optimized ETF, the old ETF used in [3], and the

TDC’s analog front-end were realized in a standard 0.7μm CMOS technology. The chip has an area of 2.3mm2 (fig. 5). The selected ETF and the temperature-to-digital converter each consume 2.5mW from a 5V supply. The timing signals were generated in an FPGA and derived from a 16MHz crystal oscillator. The ETF was driven at a frequency of 85 KHz, and the difference between the two reference phases φ0 and φ1, was chosen to be 90 degrees, which is large enough to cover the expected variation in the ETF’s phase shift over the

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military temperature range. The sampling rate of the phase-domain ΣΔ modulator was 2.67 KHz, and the low frequency chopper was driven at 20Hz. A 14-bit counter was used as a 1st-order sinc filter, which limits the system bandwidth to 0.16Hz.

Figure 5. Chip photo

Figure 6. Measured phase response of optimized and old ETF’s

Figure 7. Measured temperature error of 16 chips (new ETF). Bold line: 3σ spread for the new ETF, Dotted line: 3σ spread for the old ETF

As described in section IV, due to the implementation of an input multiplexer, both the old and the new ETF could be characterized. The measured phase shift of both filters (16 devices) is shown in Fig. 6 as a function of temperature. As a result of their different geometries, the two filters have significantly different phase characteristics. As shown in Fig. 7, the optimized ETF achieves an untrimmed inaccuracy of ±0.4°C (3σ) over the military range (-55°C to 125°C), while the old ETF only achieves an inaccuracy of ±0.54°C (3σ). These results are in line with the predicted 20% improvement in the phase spread sensitivity of the optimized ETF to lithographic inaccuracy.

VI. CONCLUSIONS A CMOS temperature-to-digital converter (TDC) based on

thermal diffusivity sensing has been implemented. It consists of a phase-domain ΣΔ modulator, which measures the temperature-dependent phase shift of an electrothermal filter (ETF). By optimizing the layout of the filter, its sensitivity to lithographic errors was decreased by 20% and its SNR was increased by 50%. To minimize the phase error introduced by the interface electronics, a wide-band, gain-boosted, single-stage transconductor was used instead of the multi-stage pre-amplifiers used in previous work. In addition, the residual offset current introduced by the chopper demodulator of the phase-domain ΣΔ modulator was minimized by locating it at virtual ground nodes. Using these techniques, an untrimmed temperature-sensing inaccuracy of ±0.4°C (3σ) over the military range (-55°C to 125°C) was achieved (16 samples).

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