Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop

C. Zhang and K.A.A. Makinwa Electronic Instrumentation Laboratory

Delft University of Technology Delft, The Netherlands

Email: C.Zhang@tudelft.nl

Abstract—A new architecture for a CMOS electrothermal frequency-locked-loop (FLL) is presented. Unlike previous work, it does not require the use of off-chip capacitors. The FLL’s output frequency is determined by the well-defined thermal diffusivity of bulk silicon. Measurements show that the spread in the FLL’s output frequency corresponds to an untrimmed inaccuracy of less than ±0.7°C (3σ) over the temperature range from -40°C to 100°C.

I. INTRODUCTION Today, most integrated temperature sensors are based on

bipolar transistors, and make use of the temperature dependence of their base-emitter voltages [1][2]. However, due to the process-dependent spread in the saturation current of bipolar transistors, the inaccuracy of such sensors is typically limited to about ±2°C. By calibrating and trimming individual sensors, the inaccuracy can be reduced to less than ±0.1°C (3σ) over the military temperature range [2]. However, this is at the expense of significantly increased manufacturing costs.

An alternative way of realizing an integrated temperature sensor is by making use of the temperature-dependent thermal diffusivity of bulk silicon [3][4][5]. In such a sensor, temperature is determined by measuring the temperature-dependent phase-shift of an electrothermal filter (ETF), which consists of a heater and a temperature sensor implemented in close proximity in the substrate. Due to the thermal inertia of the substrate, such a filter has a low-pass characteristic, and as a result, the output of the sensor will be delayed (phase-shifted) with respect to the power dissipated in the heater. This phase-shift is determined by the filter’s geometry and by the well-defined temperature-dependent thermal diffusivity of bulk silicon.

An electrothermal frequency-locked loop (FLL) can then be established, whose frequency is determined by the phase-shift of an ETF, and is therefore a well-defined function of temperature [4][5]. Unlike traditional temperature sensors based on bipolar transistors, such a sensor should not require trimming, because the thermal diffusivity of the low-doped bulk silicon is essentially process independent [6].

Figure 1. System diagram of an electrothermal FLL [5]

The system diagram of the electrothermal FLL presented in [5] is shown in Fig. 1. It consists of an ETF, a preamplifier, a synchronous demodulator (transconductance gm, chopper and integrating capacitor Cint) and a VCO. The VCO drives the ETF with a square-wave and the resulting phase-shifted output is amplified and then synchronously demodulated. The output of the demodulator is used to tune the VCO. Due to the integrating action of Cint, the VCO’s frequency fVCO will stabilize when the chopper’s DC output is zero, which corresponds to a phase-shift of 90° in the ETF. With this FLL, a temperature sensing inaccuracy of less than ±0.5°C (3σ) has been demonstrated [5].

However, in the electrothermal FLL of [5], some critical components were not integrated on-chip, such as the VCO and two large external capacitors: Cint (1µF) and Cdc (100nF, used in a DC-servo loop to reduce the preamplifier’s offset). Although the VCO can be integrated relatively easily, the two external capacitors cannot. Also, the preamplifier’s power dissipation dominates the power dissipation (2.5mW) of the interface electronics.

This paper presents an implementation of an electrothermal FLL that can be fully integrated. The realized interface electronics does not employ a preamplifier, and so dissipates less power than the circuitry presented in [5]. In the next section, the principles of an electrothermal FLL are described in more detail. Then, in section III, the implementation of the interface electronics is presented. The measurement results are given in section IV. Finally, the paper ends with some conclusions.

Sponsored by National Semiconductor

1-4244-1125-4/07/$25.00 ©2007 IEEE. 292

s

Vtp

heater

n-well

thermopile

Figure 2. Schematic layout of an electrothermal filter

II. PRINCIPLES OF THE ELECTROTHERMAL FLL The heart of an electrothermal FLL is an electrothermal

filter (ETF), which consists of a heater and a thermopile realized in the substrate of a CMOS chip (Fig. 2). As in [5], the heater is an n+-diffusion resistor and the thermopile consists of 20 thermocouples, which are made from p+-diffusion resistors and aluminum connections. Also, as in [5], the distance s between the heater and the hot junctions of the thermopile is 20µm.

In the thermal domain, this ETF behaves like a low-pass filter, whose phase-shift can be expressed as [5]:

/ 2Dφ ω∝ (1)

where ω is the frequency of the heater’s output power and D is the temperature-dependent thermal diffusivity of the substrate. When incorporated in an electrothermal FLL, the phase-shift in the ETF will be fixed at 90°, and so from (1), the VCO’s frequency fVCO can be expressed as:

VCOf D∝ (2)

The temperature dependence of D can be well modeled by a power-law function of absolute temperature [5][6], and so fVCO can be expressed as:

1VCO nf

T∝ (3)

where T is absolute temperature and n is a constant (~ 1.8 over the industrial temperature range). Therefore, fVCO will be a well-defined function of absolute temperature.

III. INTERFACE ELECTRONICS The interface electronics should be designed such that

the FLL’s output frequency is solely determined by the ETF’s phase-shift. Referring to Fig. 1, this means that the bandwidth of any circuitry located before the chopper should be large enough to minimize its electrical phase-shift at fVCO, as this would, otherwise be indistinguishable from

the phase-shift of the ETF. Furthermore, the circuitry that processes the output of the chopper should be offset-free, since any offset will be indistinguishable from the DC output of the chopper. Finally, since the FLL is basically a negative feedback loop, its loop gain should be large enough to ensure that process-dependent gain variations do not become a significant source of error.

A block diagram of the proposed FLL architecture is shown in Fig. 3. It is functionally identical with the FLL shown in Fig. 1, the main differences being that the passive integrator has been replaced by an opamp integrator, and that the preamp has been eliminated. The use of an opamp integrator ensures that the loop gain is sufficiently high, while the elimination of the preamp significantly reduces the power dissipation of the interface electronics, and makes it easier to achieve a low electrical phase-shift. Furthermore, it means that the off-chip capacitor Cdc is no longer required.

Since the ETF output is at the sub-millivolt level, the noise bandwidth of the FLL must be made as narrow as possible. Since the synchronous demodulator acts like a narrow-band filter centered on fVCO, the noise bandwidth BW of the loop may be expressed as:

intmBW g C∝ (4)

where gm is the effective transconductance of the input stage and Cint is the integrating capacitor. In [5], a noise bandwidth of about 0.5Hz was obtained by using a large off-chip capacitor (Cint=1µF). In this work, this capacitor is replaced by two, much smaller (25pF), on-chip capacitors. For the same bandwidth, gm must then be proportionally smaller. However, a smaller gm means that the DC output of the chopper will be proportionally lower, which means that integrator’s offset must be lower for the same accuracy. As a trade-off between signal level and the noise bandwidth, gm was chosen to be 100µS, which corresponds to a noise bandwidth of about 30Hz.

The phase-shift introduced by the input transconductor is process-dependent, and so its phase-spread should be much less than 90°. The transconductor was implemented as a telescopic OTA, and its bandwidth was maximized by minimizing the parasitic capacitances at its output. Corner simulations show that the OTA’s phase-spread is less than 0.2° over the temperature range from −40°C to 100°C, which corresponds to a temperature error of less than ±0.5°C. This is significantly less than the 0.8° phase-spread introduced by the front-end of [5]. However, it should be noted that within one batch, the phase-spread from device-to-device will be much smaller.

The finite steady-state gain of the loop will also give rise to an error in the steady-state value of fVCO. Due to the sub-millivolt signal level at the ETF’s output, the steady-state gain of the synchronous demodulator must be larger than 130dB in order to make the corresponding temperature error less than ±0.5°C. For this reason, the integrator’s opamp was implemented using a folded-cascode topology with a typical

293

Figure 3. The block diagram of the proposed electrothermal FLL

Figure 4. The timing diagram of the S/H

DC gain of 96dB. The rest of the required loop gain is provided by the OTA.

Due to the lower signal level, offset cancellation in the interface electronics becomes more important. At the input of the integrator, the chopper’s charge-injection mismatch will result in a residual offset current that is proportional to fVCO [7]. As in [5], this problem has been solved by adding an extra chopper operating at a lower frequency fVCO/a (a=256) in the feedback network of the integrator (Fig. 3). As a result, the total charge injection will be reduced by a factor of a. To maintain the correct polarity of the integrated current, a digital chopper operating at the same frequency fVCO/a is used to invert the heater output.

The offset of the input OTA is modulated by the fVCO chopper and results in AC ripple at the integrator’s output (Fig. 4). Furthermore, the chopped offset of the opamp appears as a square-wave at the OTA’s output, and due to its finite output impedance, will give rise to a square-wave current. After demodulation by the fVCO chopper, this current will be converted into a residual offset current at the input of the integrator. However, this residual offset current will be chopped by the extra fVCO/a chopper, and will again

be converted into AC ripple at the integrator’s output, but at the lower frequency fVCO/a (Fig. 4).

Since the driving signals of the various choppers are all derived from fVCO, its duty cycle must be exactly 50% in order to achieve perfect offset cancellation. This means that the VCO’s input should be kept constant throughout one complete chopping cycle, i.e. one period of fVCO/a, i.e. that the integrator ripple must be filtered out. To remove the ripple, a sample-and-hold circuit (S/H) consisting of two capacitors and some switches is inserted between the integrator and the VCO [8]. The timing diagram of the S/H is shown in Fig. 4. The residual square-wave ripple is due to the opamp’s millivolt-level offset, which also appears at the output of the integrator.

Another source of error is crosstalk (via parasitic capacitances and the substrate) between the heater drive voltages and the thermopile output [5]. In this work, the two terminals of the heater are driven by fVCO and fVCO/a (Fig. 3). As a result, the polarity of the heater drive voltages are periodically inverted, which cancels the effect of crosstalk [5]. Furthermore, this heater driving strategy also implements the function of the digital chopper.

IV. MEASUREMENTS The ETF and the synchronous demodulator were

realized in a standard 0.7µm CMOS process (Fig. 5). The entire chip has an area of 2.3mm2. For flexibility, the S/H, the VCO and the digital logic were implemented off-chip. However, the inputs of the VCO and the switches of the S/H exhibited significant leakage currents at high temperatures (2µA). To minimize the resulting discharge of the sampling capacitors, large values were used (10µF). By integrating the VCO and the switches on-chip, such leakage currents can be eliminated, and the capacitors can be made small enough (a few picofarads) to be integrated on-chip.

294

Figure 5. The chip photo of the electrothermal FLL

Figure 6. Measured frequency vs. temperature characteristic of 16 samples from one batch.

Figure 7. Measured temperature error of 16 samples from one batch, with 3σ limits (bold lines).

The on-chip electronics (excluding the heater) dissipates 0.9mW from a 5V supply, while the heater in the ETF dissipates 5mW. Measurements, on 16 samples from one batch, show that fVCO has the 1/Tn dependency predicted by (3), where T is the absolute temperature in Kelvin and

1.8n ≈ (Fig. 6). Based on this model, fVCO at 300K is 103KHz, which is in good agreement with [5]. The spread in fVCO is less than ±0.45% (3σ) over the temperature range −40°C to 100°C. This corresponds to a temperature inaccuracy of less than ±0.7°C (3σ) (Fig. 7). The FLL’s output jitter corresponds to a temperature error 0.1°C (rms).

V. CONCLUSIONS A temperature sensor realized by an electrothermal FLL

has been presented. The electrothermal FLL makes use of the temperature-dependent thermal diffusivity of the bulk silicon. Due to the high purity of the bulk silicon, an untrimmed inaccuracy of less than ±0.7°C (3σ) is achieved over the temperature range from −40°C to 100°C. Compared to the prior art on electrothermal FLLs [5], the interface electronics dissipates three times less power. Furthermore, it does not require large off-chip capacitors, and so can be fully integrated in standard CMOS technology.

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