1996 IEEE TENCON - Digital Signal Processin,s Applications

Low Power, High Performance Switched-Capacitor Sigma-Delta Modulator Suitable for Battery operated Audio Signal Processing Applications.

Ho Yoon San & S.M. Rezaul Hasan School Of Electrical & Electronic Engineering, Universiti Sains Malaysia

Per& Branch Campus, Bandar Sri Iskandar 31750 Tronoh,Perak

Malaysia

ABSTRACT: A high performance, low ~ O M W

second order sigmn delta modirlator is proposed. The proposed corivertel- cati De integrnted cilotig

with other rligitnl cii.ix~itries to form n cotnplete moriolithic digital signal processor for DSP applications. The convertet- is tiot setisitiw to wat-ds co vipo ti pi i t 111 ismo tc h nil d ti o I 1 irle (7 I it ies of the process technology. Sirniil(1tioti t m i i It show ,s tlmt the proposed cotivet'ter rrcllieved iGrtiiolly 13.9 Dit resolutioii ut snmplitig f r - eq icen~y o f 5.12 MHz for (in iriput sigtial of 20 kHz bnndwirltli. I t opeiutes (it +i- 2.5V siipply voltrrge with (1 single polrrriry rcferetice voltage atid (1issi)nttJs otdy 4inw.

1. INTRODUCTION

The most robust sigma-delta modulntor reported so far is the second order sigma-delta modulator with two integr:itors and a two level single threshold quantizer placed in two feedback loops [1][3-1. Singor & Snelgrove[3] reported a switched- capacitor sigma-delta modulator which dissipated 60mW for a i SV power supply.

In this paper, we describe a low power second order sigma-delta modulator which dissipates 4mW for a k 2.5 V supply voltage. This modulator uses simple two stage op-amps as integrators and :I volliige to charge converter as the 1 bit D/A.

2. ARCHI'I'ECTURE OF THE SIGMA-

DELTA (CA)MOI)ULATOR

The schematic di:igr:im of the modulator is shown in figure 1. Here switches S 1 4 4 , C 1 . U and OP1 forin a stray insensitive non-inverting switched capacitor integmtor[4]. All switches in the modulator are implemented by CMOS tr:insmission g;ite in order to reduce the et't'ect of clock fecdthrough and also 10 allow fu l l rail input signal.

Switches SS-SX. C3, C4 nnd OP2 form the second integrator. OP3 fonns the single threshold. two level quantizer. Switches S1 I-SZO :ind CS

form the 1 bit D/A while S21-S30, C6 form another D/A that feed to the second integrator. The reference voltage used has only single pohi ty . The operation of the modulator is controlled by R

two phase non-overlapping clock which regulate the bit rate at the output, so that, the average output is equal to the average input.

During phase one, P1, switches S1, S4 are closed and S2, S3 are opened and the input is sampled into C1. Also SS, S8 are closed and S 6 , S7 are opened which cause the output of the first integrator to be sampled into C3. At the same time, the output of the second integrator is sampled into C7 and is compared with ground at OP?. The output of the comparxor is stored into C8.

During clock phase two, P2, switches Sl,S4,SS,SS are opned while S2,S3,SG,S7 are closed. Then all the chrirge in the capacitor C1 is transferred to C2. Also all charge in C3 is transferred to C4. At the same time switch S10 is closed and c;iuses the output of the comparator to 1% fed into the D/A and causing the D/A circuit to pump out either +CVref or - CVTef charge into the non-inverting terminal of the op-amp. The transfer function of the integr;;!or can be written in z- domain as.

v, = ( Cl/C2) ( fl/( 1 - z-l ) ) (V, - Vref) (1)

where Cl/C2 is the integrator's gain. As a result . the circuit implements the subtraction of input and the output (fcedback) and integriilion at the snme time.

In this paper, a two stage CMOS op-amp with differential input and single ended output is employed. The two stag? op-amp has demonstrated high open-loop gain that reduces the impact of finite op-amp gain towards the performance of a switched-capacitor integrator. In addition. the output swing of a two stage op-amp is larger. Therefore the use of ;I two stage op-;imp is justified. The simulated perform;iiice of the op- amp is shown i n t:iliIe I .

728 0-7803-3679-8/96/$5.00 0 1996 IEEE

P2 COlll I I

Hysterisis Slew rate

Figure 1 : Second Order Sigma-Delta Modulator Architecture

2mV 1 OO.%V/ps

The 1 bit A/D is implemented by an op-amp similar to the one used in the integrator .The performonce of the compxator is summarized in table 2. The 1 hit D/A is a voltage to charge converter where the output of the compxator will determine the polarity of the chxge that is injected into the non-inverting terminal of the op-amp.

3. SIMULATION RESULT

Extensive SPICE sitntilahn was carried out on the modulator using 211 CMOS parameters from MOSIS. Fourier an:tlysis was then performed at the oulput of rhe modtil:ilor. A sinusoidal sign:il of

2OWz was fed to the modulator and the sampling frequency was set at 5.12 MHz colresponding to an oversampling ratio of 128. A dynamic range of X3.4dB was achieved which corresponds to 13.9 bits resolution for a Nyquist rate converter. The proposed convcrter operates with a power supply k 2.SV and dissipates only 4 mW . The low power consumption of the converter is particularly attractive for low power applications especially audio signal processing in battery operated consumer electronic product. Figure 2 shows the output spectrum of the modulator when a 20kHz sinusoidal signal is applied to the modulator.

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Figure 2: Output Spectrum of the modulator

4. CONCLUSION [3] Singor F.W. and Snelgrove, “Switched-

In this paper. we have prescrited a second order sigtm-delta modulator that employed three simple two stage transconductance operation amplifiers 3s

the integrators and the coniparator. Simulation result shows that the modulator achieves 13.9 bit resolution at sampling frequency of 5.12 MHz for a baseband signal of 20Wz while only dissipating 41nW.

The absolute accuracy of the capncitors used within the modulator will not impair the overall performance of the system because the gain of the integrator solely depends upon the cap:icitance ratio rather than the nhsolute individual capacitance, and therefore i t is tolerant to device in isina tc h.

The resolution of the converter can be increased by employing higher sampling frequency or higher oversampling ratio. However, the architecture of the modulator irself is designed to suppress in-band quantization noise. The therm:il noise and l/f flicker noise would still present he i n the system and this will impair the performance of the modulator somewhat.

5 . REFERENCES

[ 11 Candy J.C., “A Use Of Double Integration In Sigma-Dcltn Modulation,” IEEE Jourii:il 0 1 1 Coin munication.s,Vol.33, pp. 249-258.. Mac. 1985. Roser B. E. and B.A.Wooley. “The Design of Signin-Delta Modulation Analog-to- Digital Converters,” IEEE Journal of Solid- State Circuits. Vol. 23. pp.1298-1308, Dec. 1988.

[2]

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capacitor bandpass _Delta-Sigma A/D Modulation at 10.7 MHz ,” IEEE Journal of Solid-state Circuits, Vol. 30, pp.184-192 , Mac. 1995.

Gregorian R. and Teines G.C., 1986, Analog MOS Integrated Circuits for signal processing (New York: John Wiley series on filters)

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