Proceedings of 1990 International Symposium on Power Semiconductor Devices & ICs, Tokyo, pp. 289-294 6.3.5

A NOVEL 8 KV LIGHT-TRIGGERED THYRISTOR WITH OVERVOLTAGE SELF PROTECTION

H. Mitlehner, F. Pfirsch, H.J. Schulze

Siemens AG, Central Research and Development, Otto-Hahn-Ring 6

8000 Munich 83, Germany, Phone:

ABSTRACT

We have fabricated a novel 8 kV light-triggered power thyristor with integrated overvoltage self-protec- tion. The light-sensitivity was im- proved by a special groove struc- ture. Four amplifying gate-stages together with an integrated current- limiting resistor guarantee a safe and homogeneous turn-on behavior. An improvement of the dynamic and static power losses could be ob- tained by a local lifetime reduction and by a decrease of the penetration depths of the blocking pn-junctions.

1. INTRODUCTION

Current developments in thyristor switches for high-voltage power sys- tems are aiming at reducing the com- plexity of control units in the thyristor valve and consequently at improving their reliability and costs [l]. One approach is to re- place the triggering and protective units at different levels of high potential by direct integration of light triggering and overvoltage self-protection into the thyristor. Another possibility is to increase the blocking voltage per thyristor in order to reduce the number' of thyristors per valve. This approach, however, has to face constraints put forward by system power loss consid- erations becoming .more and more im- portant at blocking voltages exceed- ing 5 kV.

The principle goal of this work was to develop an 8 kV light-triggered, self-protected thyristor (LTT) with- out any electrical gate-circuit ca- pable to replace electrically trig-

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gered thyristors in KVDC-installa- tions. The successful development of such an HVDC-thyristor is hampered by several problems concerning

(1) the trade-off between the static and dynamic power losses compared with a 5.5 kV thyristor;

(2) a high dv/dt-capability without degrading the light sensitivity;

( 3 ) the turn-on at high voltage with high di/dt-capability triggered with relatively small light-induced cur- rent ;

(4) the optical transmission loss over long distances from the light source to the thyristor surface.

Fig. 1: a) cross-section of the encapsula-

tion for a light-triggered thyristor (LTT)

b) gate-structure of an 8 kV LTT

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For this purpose a new powerful light-source (Xenon flash-lamp) had to be developed, which is able to trigger up to 100 thyristors in a valve synchronously. Additionally it was necessary to construct a novel encapsulation allowing to guide a light-pipe to the center of the presspack-housing even for in series connected thyristors (Fig. 1).

Earlier investigations dealing with a discrete pilot thyristor [2] in the gate-circuit of an electrically triggered main thyristor have shown that the demands (2) and ( 3 ) could only be satisfied by a special light-sensitive gate-geometry and an additional resistor between the am- plifying gate stages. Aiming at an improved reliability of the thyris- tors, device simulations and experi- ments have been performed to show possibilities for the integration of a break-over diode (BOD) function which can be controlled by the de- sign of the p-base (Sec. 2).

Since the power loss increases with the blocking voltage, it is neces- sary to look for new concepts in the case of thyristors with blocking voltages exceeding 8 kV as e.g. the realization of a “Tandem thyristor“ [ 3 ] or the introduction of new tech- nologies presented here (Sec. 3 ) .

2. DESIGN CONSIDERATIONS

The central region of the thyristor contains four amplifying gates. (Fig. 1). An additional circular- shaped resistor between the amplify- ing gate stages has to limit the current flow and to reduce the duty- cycle of the first stage. This de- sign guarantees a safe and homoge- neous turn-on behavior under real load conditions up to the full blocking voltage. There is an obvi- ous negative aspect of the inte- grated resistor because of the in- creased gate impedance. But this has only to be considered, if this con- cept of overvoltage protection should be transplanted into an elec- trically triggered thyristor. At very small anode voltages the cur- rent-limiting resistor can also hold down the current of the next stages below the trigger current, determin- ing the maximum resistor value for a minimum required anode voltage. Fi- nally, the thermal load on the re- sistor during turn-on has to be

carefully calculated to prevent thermal failure in the resistor re- gion. The following considerations concerning the lay-out are taken into account:

f) In order to avoid problems with isolation during turn-on at high voltage an essentially rotational symmetric geometry is chosen. There- fore grooves need not be able .to withstand high potential differ- ences.

ii) A good compromise between light sensitivity and dv/dt-capability is provided by a structure consisting of etched grooves around the light sensitive area. Light sensitivity is influenced by the depth of the grooves [ 2 ] .

iii) The amplifying gates are tuned with respect to increasing dv/dt-ca- pability going from the center to the main cathode and with respect to trigger current in order to guaran- tee high di/dt-capability. Trigger current does not differ by a factor greater than 3 between subsequent stages outside the current limiting resistor. ’

iv) Shape and area of the integrated resistor ( 5 0 a ) are dimensioned as to ensure that the energy dissipated during turn-on does not lead to burnout. Under worst conditions (turn-on at maximum voltage, dissi- pated energy ca. 100 mJ) the maximum rise of temperature is calculated to be 170 K.

v) Overvoltage protection is achieved using a curved pn-junction with reduced breakdown voltage. Cal- culations carried through with a modified version of the PISCES I1 B- computer program are shown in Fig. 2 for the breakdown voltage in the two- and three-dimensional rotation- ally symmetric case, respectively. We chose a rotationally symmetric structure.

3 . DEVICE TECHNOLOGY

We have performed device simulations demonstrating that there are two possible ways of achieving an im- provement in the trade-off between the stat,ic and dynamic power losses. One is the generation of localized narrow regions of short carrier lifetime near the blocking p/n-junc-

290

tions ana the other is the reduction of the device thickness by smaller penetration depths of the p/n-junc- tions. The influence of these meth- ods on the trade-off between the on- state voltage VT and the reverse re- covery charge Q== is demonstrated in Fig. 3 .

6.5 4 \ I 0.0 50.0 100.0 150.0 203.0 250.0 3m.o G.0 m.0

D l p m )

Fig. 2: Break-over voltage vs. diameter of the BOD-structure. Diffusion depth: 90 pm (a,b); 50 pm (c,d). Curves arc are for rotationally symmetric structures, curves b,d for dimensional structures.

two-

1 n+-P+ I I , , . . I . , /

V,/V

I , . , . 72Wr ' ' 1.8 20 2.5 3.0 L

Fig. 3: QIT/VT trade-off calculated for 50 pm (1) and 90 pm (2) deep blocking p/n-junctions.

For experimental verification of those potential improvements we have fabricated 8 kV thyristors with ho- mogeneous or local lifetime reduc- tion and with different penetration depths of the p/n-junctions, requir- ing also different total device thicknesses to obtain the same blocking voltage. The essential technological parameters such as wafer thickness, doping profile and carrier lifetime were chosen as sug- gested by device simulation and pre- dicted by process simulation.

The minimization of the process-in- duced defect density in the silicon wafers and an accurate control of the doping profiles were important aspects of device processing. The n- -layer ( 9 = 470 Qcm) of the float zone 3"-silicon wafers was fabri- cated by neutron transmutation dop- ing. In order to obtain a high car- rier lifetime by low diffusion tem- peratures and short diffusion times, the blocking p/n-junctions were re- alized by an A 1 vacuum pre-deposi- tion [ 4 ] followed by a drive-in step. This diffusion results in very homogeneous sheet resistances which is a very important condition to thyristor optimization. The n+-emit- ter was produced by a POCls-diffu- sion yielding a good gettering effi- ciency for heavy metal impurities. To obtain a good p+-emitter, a shal- low boron doping profile was super- imposed to the A 1 doping profile by a boron implantation into the anode side of the device and a subsequent annealing procedure. The connection of the Si-wafer with the Mo-sub- strate was provided by a low-temper- ature joining technique [ 5 1 . The re- duction of the carrier lifetime in two small layers according to Fig. 3 was realized by proton irradiation whereas the homogeneous lifetime re- duction was achieved by electron ir- radiation.

The doping profiles were controlled by spreading resistance measurements and 4-point resistivity mapping. The analyses concerning the process-in- duced defect density in the wafer are described elsewhere [ 6 ] .

291

As the junction depth of the p-lay- ers was reduced to 50 pm, it was necessary to apply a novel termina- tion for the p/n-junction blocking in the forward mode. In order to ob- tain a good blocking capability, a 3 mm wide planar junction termina- tion with a variation of the lateral doping concentration [7] combined with a depletion etch was used. The essential fabrication steps of this junction termination are illustrated in Fig. 4. The blocking capability in the reverse blocking mode was provided by a positive angle. The structure of the A1 doping profile in the middle of the device (Sec. 2) leading to a BOD-function, was ob- tained by the masked etching of the p-doped layer after the Al-prede- positon. A p/n-decorated cross sec- tion of this device region is shown in Fig. 5.

I n-

- I n I

Fig. 4: Fabrication process for planar, high-voltage junction terminations. a) Wafer cross-section after Al-pre-

b) after masked etching; c) after drive-in; d) after depletion etch

deposition;

Fig. 5: Decorated cross-section of the BOD- region; the darker area corresponds to the p-type base layer.

4. EXPERIMENTAL RESULTS

The experimental Q,,/VT data of thyristors fabricated with different penetration depths of the p/n-junc- tions and with homogeneous or local lifetime reduction are in good agreement with the device simula- tions. It could be demonstrated that the application of proton irradia- tion instead of electron irradiation results in a Q,,-reduction of 15 % for a fixed VT whereas the transi- tion from 90 pm to 50 pm deep block- ing p/n-junctions causes a Q,,-re- duction of 30 %.

Electrical data of LTT's (50 pm pen- etration depth of the blocking p/n- junctions) without BOD-protection are listed in Table I. Current-volt- age characteristics in the forward and reverse blocking mode at 25OC are shown in Fig. 6.

The depth of the etched grooves d has been varied between 22 pm and 31 pm. Accordingly, the light-sensi- tivity of the thyristor changed from llmW (d = 22 pm) to 8mW (d = 31 pm) applying a forward blocking voltage of 800 V.

Turn-on at high voltages (7.5 kV) showed a soft switching behavior. The dechargement of the installation capacitance (4 nF) with subsequent di/dt = 100 A/ps could be handled properly due to the current limiting resistor. IR-recombination measure- ments proove the turn-on at the desired amplifying gate stage (Fig. 7).

292

-?

\ E 5 0 -

c: G . w -

33-

20

10

U0

I -

-

U n , U a / k V

Fig. 6: Current-voltage characteristics in the forward (U,) and reverse (UR) blocking mode at 25OC.

-?

\ E 5 0 -

c: G . w -

33-

20

10

Fig. 7: Turn-on behavior at 7.5 kV. a) IR recombination radiation in the

time interval t, (b) during turn- on

b) time-dependence of thyristor cur- rent and voltage after triggering by a light pulse 4.

U0

I -

-

U0 / k V

Fig. 8: Current-voltage-characteristics in the forward blocking mode of a BOD- protected thyristor at different temperatures.

U T \ w j I .cuuunl L>

Q,,(pAsec); 2000A, 2 A/wsec dU / d. auf Un=7kV

,; 25°C I T T I . 7nnnn

R(kV); 25OC

tlkV/usec): 90°C

Table I

In case of an integrated overvoltage self-protection the blocking voltage could be reduced to 7.8 kV at 25°C and 8 . 3 kV at 120OC. The current voltage characteristics in the for- ward blocking mode of such a thyristor are shown in Fig. 8 for different temperatures.

CONCLUSIONS

An 8 kV light-triggered power thyristor with a safe turn-on behav- ior and an integrated overvoltage self-protection was fabricated. A reduction of the power losses could be realized by consequent applica- tion of new fabrication technologies backed up by numeric simulation.

293

ACKNOWLEDGEMENTS

The authors would like to thank J. Sack and P. Vop for many helpful discussions. Moreover, we are grate- ful to B. Blocher, R. Bommersbach, R. Kuhnert, H. Schwarzbauer, and W. Zlabinger for their support in preparation and measurement of the samples.

REFERENCES

H. Mitlehner, H.J. Schulze, "Thyristors for HVDC-Transmis- sion" , Phys . Technol. , 19 , 227 , 1988 H. Mitlehner, "Light Activated Auxiliary Thyristor for High- Voltage Applications" , Siemens Forsch.u.Entwick1.Berichte 14, 50 , 1985 H. Mitlehner, J. Sack, H.J. Schulze, "High Voltage Thristor for HVDC Transmission and Static Var Compensators" , PESC 88 Record, 934, 1988 W. Rosnowski, "Al-Diffusion into Silicon in an Open Tube High Vacuum System", J. Electrochem. Soc. U.5, 957, 1978 H. Schwarzbauer, R. Kuhnert, "Novel Large Area Joining Technique for Improved Power Device Performance" , IEEE/IAS Conference Record, 1348, 1989 H.J. Schulze, "Reduction of Process-Induced Defects in Power Devices", Mat. Science and Eng. , B4, 377, 1989 H.J. Schulze, R. Kuhnert, Re a 1 i z at i on of a High -Vo 1 t age Planar Junction Termination" , Sol.State Electr.,32, 175, 1989

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