A web EDA tool for the automatic generation ofsynthesizable VHDL architectures for a rapid design

space exploration

Minas DasygenisDepartment of Informatics and Telecommunications Engineering

University of Western Macedonia, Kozani, 50100, Greece, Email: mdasyg@ieee.org

Abstract—Design space exploration of new circuit method-ologies require the creation of models in hardware descriptionlanguages to evaluate the characteristics for different parameters,a time consuming process. To alleviate the burden of HDLconstruction, we present a compact netlist format and a web toolthat creates syntactically correct VHDL files. The designer canuse our tool, together with an easy to create netlist generator, toquickly create multiple VHDL files and skeleton test benches, toevaluate his model. Our parametrized netlist generators illustratethe efficiency of our EDA tool.

I. INTRODUCTION

During the recent years, the complexity of designing in-tegrated circuits has increased by many orders of magnitude,especially due to the assembly of multiple functional units onthe same System-On-Chip (SoC). Most of the SoC are customhardware architectures, that cause their development even moredifficult to plan, implement, evaluate and test on time.

Fortunately, this barrier is mostly removed with the aid ofthe electronic design automation tools (EDA). Even though,EDA tools cover all aspects of design, we have found thatDSE support is limited. Up to now, the designer who wouldlike to evaluate his circuit methodology, he had either tocreate many HDL models or he had to write a parametrizedgenerator to output a netlist format, like EDIF, a thorny taskeven for experienced engineers. Both approaches are very timeconsuming.

We present a compact and efficient netlist format and aunique web based tool that can play a crucial role in a fastdesign space exploration1. The input to the tool is a newnetlist format, and the outputs are a full set of VHDL filesfor the circuit, the components used, and the block levelschematic. We have named the new netlist format abstractedHDL (α-HDL) and has been designed with some specificgoals:(1) convey only the necessary information for the struc-tural connectivity of the components, (2) remove redundancyin the representation, (3) be as compact as possible, in orderto minimize errors during its automatic generation, (4) bedynamic, (5) be specialized for the structural connections, and(6) be easy to construct by a prototype generator. To thebest of our knowledge, there is no free web tool that canaccept a compact netlist and output syntactically correct andsynthesizable VHDL files and schematics.

1The tool is available at http://arch.icte.uowm.gr/hdl

Our key contributions are the following: (i) We present apublic web accessible tool that can create very fast syntacti-cally correct register-transfer-level VHDL description of thegiven netlist format. (ii) We present a new type of a compactnetlist format that differs from every other netlist becauseit does not carry redundant information, in which only theinput vectors are defined. (iii) Our netlist format has beendesigned with the focus to be constructed automatic by an α-HDL generator, and not by human. Because it is compact andeasy to generate, designers can create generators to validate thebehavior of their circuits for different requirements. (iv) Weprovide from the tool’s web page, a number of hdl generators,than can be used to create α-HDL netlists for specific designparameters and download the generated VHDL codes, alongwith their testbenches. (v) we demonstrate the usefulness ofusing a high level language (python) in the rapid design spaceexploration.

II. DISCUSSION AND RELATED WORK

Generating HDL code from a higher level language is notnew. For the past 15 years many researchers have workedon automating the HDL generation, but with not very usefulresults (at least for the whole EDA community) [6]. As theauthors of [6] conclude, there is a serious problem with the lackof EDA automation. We noted this problem, and we decidedto challenge it.

Steps towards EDA automation are performed from allmajor EDA companies (Altera, Xilinx, Mathworks, etc.). Thesecompanies support customized IP blocks for various functions.Xilinx provides the “Core Generator”, while Altera providesthe “MegaWizard Generator”. All these generators create spe-cific modules, and they do not support the creation of othertypes of modules. Our tool can assist in this field, becauseit is a very flexible tool. Furthermore, automating VHDLgeneration for various design modules has been a topic underresearch for more than a decade. Daveau et al [4] presented anapproach to allow the generation of VHDL from SDL models.The work was limited only on the specification and no EDAtool was ever created. Daitx et al [3] presented a tool to createVHDL description of FIR filters according to a coefficientspecification file. Their tool is not available online, in contrastwith our tool. All these efforts target specific circuits and theyare not as flexible or generic as our tool.

On the other hand, automating High level HDL generationis the focus of multiple research projects. All these generators

2014 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

978-1-4799-4972-4/14/$31.00 ©2014 IEEE

!

accept a high level description of the code, usually in C, andcreate an HDL description of it. The major drawback of highlevel synthesis, is that input code should adhere to a lot of re-quirements, like regular memory access, perfectly nested loops,in some cases absence of pointers and so on, while all the toolshave a limited application domain. The ROCCC project [1]supports mainly streaming applications. The Streams-C project[5] also supports a very limited application domain.

III. THE α-HDL NETLIST

Our web tool requires a compact netlist input called α-HDL, which is formulated either by three different datastructures, or concatenated into a single data structure in theformat of the JSON [2]. The back-end of the tool is based onthe python programming language.

Our tool accepts as input three data structures that areusually created by an α-HDL generator. This netlist format hasbeen created bearing in mind that the structures will always becreated by a program and not by a human, because creatingthem by hand would be error prone. On the other hand, creatingthem by a program is much easier.

The first data structure, named components can be visual-ized as a hypercube with three dimensions [x][y][z]. In each(x, y, z) location, an unsigned number exists. This number isa component id number, and is correlated with the second datastructure.

The second data structure, named componentlist is alookup table that relates the component’s id to the componentnames. The component names are either the exact names ofcomponents found in the tool’s library, or they adhere to aspecific syntax that defines a new component. The standardcomponents do not provide only the RTL description, but alsothe quadruple (i, o, io, b) with i the number of input ports,o the number of output ports, io the number of input-outputports, and b the number of buffer ports. This quadruple isvery useful during the VHDL generation phase, because ithelps to detect whether there is an unconnected port, or thedirection and type of the port. The lookup table of compo-nentlist is specified in python syntax using {} brackets, suchas componentlist = {“10” : “fa1bit”}.

The third data structure, named interconnections is amultidimensional array that carries all the input connec-tions of every component. For every component (x, y, z)the interconnections[x][y][z] carries a number of vectorsthat describe the connections of the input ports only. Theinterconnections[x][y][z][0] is the vector that correspondsto the first input port of the component, while the vectorinterconnections[x][y][z][w] corresponds to the w − 1 inputport. The term input port is used both for the in and inout portsand our tool can understand the type of port according to thequadruple (i, o, io, b). Note that in α-HDL only the input portsare specified, with the only exception of the special outputnodes, that carry also output information.

IV. APPLICATIONS & EXPERIMENTAL RESULTS

To illustrate the usefulness of our tool and evaluate it, wehave constructed three α-HDL generators, available on thesame web page, that create input files for our tool according

to user parameters, which are fed as inputs to HDL generator.The first α-HDL generator, is a ripple carry adder, that consistsonly of 16 lines of python code.

The second α-HDL generator is an unsigned binary mul-tiplier. This derived circuit consist of AND gates, full addersand half adders. In the first step the partial products are createdusing the AND gates, and in the second a CSA is utilizedto sum all the partial bits, while in the third step a ripplecarry adder is used for the final result. This is a complicatedcircuit that cannot be parametrized in a VHDL file using theGENERIC clause. The α-HDL generator for this circuit andconsists of 120 lines of python code.

The third α-HDL generator is a CSA adder for unlimitednumber of input vectors and bits, and consists of 100 lines ofpython code. The parameters to this generator are the usageof pipeline flip flops, and the input vectors, formulated in antwo dimensional array, with every row corresponding to eachvector. In this complex model a testbench creator was alsoadded that creates random test vectors to verify its correctoperation.

All these generators were thoroughly tested, synthesizedand simulated without any error or warning, using XilinxVivado 2013.2, Altera Quartus II 12.0 sp2, and ghdl. Further-more, all α-HDL generators as well as the VHDL generatorare available on the web, and accessible for use with everybrowser. Every designer, can use the tools to create VHDLcodes that can download for local compilation and simulation.

V. CONCLUSIONS

We present a novel web EDA tool to assist the designersin the rapid generation of correct and synthesizable VHDLdescription of their circuits, using a new, compact and efficientnetlist format, called α-HDL. The tool outputs a full set ofVHDL files (circuit and components description, testbenchskeleton) and a detailed block schematic. Our simple andcompact netlist format, enables the creation of parametrizedα-HDL generators for a quick design space exploration. Ourtool exhibits some very useful characteristics: it is one of thefirst EDA tools that is available on the web and accessed usinga web browser, it is free, and it is accompanied by a numberof parametrized circuit generators.

REFERENCES

[1] J. Computing, “ROCCC 2.0 (riverside optimizing compiler for config-urable computing), C to HDL,” (On-line) http://www.jacquardcomputing.com/roccc/, 2014.

[2] D. Crockford, “The application/json media type for javascript objectnotation (json),” Internet RFC 4627, July 2006. [Online]. Available:http://www.ietf.org/rfc/rfc4627.txt

[3] F. Daitx, V. Rosa, E. Costa, P. Flores, and S. Bampi, “VHDL generationof optimized FIR filters,” in Signals, Circuits and Systems, 2008. SCS2008. 2nd International Conference on, 2008, pp. 1–5.

[4] J.-M. Daveau, G. F. Marchioro, C. A. Valderrama, and A. A. Jerraya,“VHDL generation from SDL specifications,” 1996.

[5] M. Gokhale, J. Stone, J. Arnold, and M. Kalinowski, “Stream-orientedFPGA computing in the Streams-C high level language,” in Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on,2000, pp. 49–56.

[6] Y. Yankova, K. Bertels, S. Vassiliadis, R. Meeuws, and A. Virginia,“Automated HDL generation: Comparative evaluation.” in ISCAS.IEEE, 2007, pp. 2750–2753. [Online]. Available: http://dblp.uni-trier.de/db/conf/iscas/iscas2007.html#YankovaBVMV07

!

!