Brain Inspired High Performance Electronics on Flexible Silicon

Galo Andres Torres Sevilla, Jhonathan Prieto Rojas and Muhammad Mustafa Hussain Computer, Electrical and Mathematical Engineering Division. King Abdullah University of Science and Technology.

Thuwal, Mekkah, Saudi Arabia Email: MuhammadMustafa.Hussain@kaust.edu.sa

Abstract— Brain’s stunning speed, energy efficiency and massive parallelism makes it the role model for upcoming high performance computation systems. Although human brain components are a million times slower than state of the art silicon industry components [1], they can perform 1016 operations per second while consuming less power than an electrical light bulb. In order to perform the same amount of computation with today’s most advanced computers, the output of an entire power station would be needed. In that sense, to obtain brain like computation, ultra-fast devices with ultra-low power consumption will have to be integrated in extremely reduced areas, achievable only if brain folded structure is mimicked. Therefore, to allow brain-inspired computation, flexible and transparent platform will be needed to achieve foldable structures and their integration on asymmetric surfaces. In this work, we show a new method to fabricate 3D and planar FET architectures in flexible and semitransparent silicon fabric without comprising performance and maintaining cost/yield advantage offered by silicon-based electronics.

Keywords—flexible electronics; mono-crystallline silicon; 3D flexible electronics; field effect tranisistor.

I. INTRODUCTION Today’s flexible electronics research is mainly based on the

fabrication of solid-state devices on organic substrates, which show extreme flexibility and transparency [2-5]. However, the low temperature requirements to processes organic substrates and their inherited low electron mobility hinder their potential for truly high performance flexible electronics. Some other approaches have been investigated recently involving transfer of monocrystalline silicon on polymers [6-11]. Although these techniques exhibit high yield and feature definition, they are incompatible with very critical state of the art processes such as mask alignment. Also thinning techniques have been used to produce mechanically flexible silicon chips [12,13]. However, their major drawback consists in the use of extremely abrasive processes that may damage the on-hip devices. To mitigate all these weaknesses, in the recent past we have demonstrated transformational electronics where we transform the traditional silicon electronics into flexible and transparent one with already fabricated devices retaining their status-quo performance, efficiency, ultra-large-scale-integration density, thermal budget and finally cost.

Using this low-cost generic batch process, we make trenches in the unused areas of a silicon circuitry, followed by vertical sidewall protection layer (spacer) formation and finally carrying out an isotropic etching at the bottom of the deep trenches to form 20 mm caves in the silicon substrate to release an ultra-thin (>5 mm), fully flexible (5 mm bending radius) and semi-transparent (12% transmittance) silicon fabric with pre-fabricated devices. After the removal of the top layer of whole wafers in this way, we perform chemical mechanical polishing to planarize the remaining bottom substrates to recycle it and then fabricate next set of devices on it followed by the repetition of the same process to form up to 6 layers of silicon fabric with devices from a standard 0.5 mm thick silicon wafer. Following a similar process, here we demonstrate, semiconductor industry’s most advanced architecture FinFET and planar MOSFETs with the most advanced material set: high-k/metal gate stacks.

FinFET is a new generation device architecture which has been adopted by semiconductor giant Intel Corporation from 2011 in their microprocessors. FinFET a member of multi-gate FET family offers non-planar 3D topology where the channels are vertically aligned in arrays of ultra-thin silicon fins bordered by multiple gates (in our case it is two gates) to ensure higher electrostatic control so the short channel effects can be mitigated as well as performance can be enhanced. In addition to the advanced topology, we have also integrated semiconductor industries’ most advanced high-k/metal gate stacks to make our device fully state-of-the-art.

II. FABRICATION PROCESS

A. Flexible FinFETs [14] Figure 1 shows the basic steps to release FinFETs from the

carrier substrate and transfer them to a polymer substrate. Each of the fabricated wafers was diced into 2.5 cm x 3 cm pieces in order to process each die separately. It is to be noted that although complete wafer release can be easily performed, die processing was chosen in order to perform different etching conditions on each die. At this point, dies were processed with research level lithography to create the etch hole patterns in the inactive areas of the fabricated devices (Fig. 1b). The distance between the holes depends on the selectivity of the isotropic etchant between silicon and buried oxide (BOX) (>1000:1) and the thickness of the bottom oxide layer. The next step consists in removing the interlayer dielectric (ILD) from the holes to

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allow access for xenon di-fluoride (XeF2) isotropic etchant. Next, while keeping the photoresist, the dies were placed in XeF2 chamber to isotropically remove the silicon from the bottom of the BOX and create caves (Fig. 1c), once these caves meet with each other, the SOI and the BOX, is completely released from the bulk substrate allowing us to peel-off the devices (Fig. 1d) and transfer them to a flexible polyimide carrier substrate (Kapton) with a thin uncured PDMS spin coated film to enhance adhesion between the peeled devices and the carrier substrate (Fig. 1e). Finally the PDMS layer is cured. It is to be noted that the holes did not represent any constraint in the design of the fabricated devices due to high selectivity between thermal oxide and silicon under XeF2 etching conditions.

Fig. 1. Flexible FinFET fabrication flow.

B. Planar MOSFETs [15] Figure 2 shows the fabrication process for planar

MOSFETs on flexible silicon. The fabrication begins with standard 4” silicon wafers (100). All the devices are built using research grade lithography and industry compatible etching and deposition processes. First the active definition is done using one lithographic step and one etch step to remove the silicon dioxide (SiO2) from the area where the transistor is built. Next, the gate is deposited (TaN + Al2O3) and patterned using regular lithography and reactive ion etching. Finally the devices are implanted in the source and drain regions and contacted using aluminum contacts. At this point, the fabrication of the transistors is completed and we can proceed to the release of each individual die. The dies are taken for a final lithography and patterned with the etch holes which are done with deep RIE. Finally, spacers are deposited in the walls of the deep trenches and the dies are taken into XeF2 chamber in order to isotropically etch the bottom silicon and release the devices from the bulk substrate.

Fig. 2. Flexible planar MOSFETs fabrication flow.

III. RESULTS In order to have a complete understanding of the electrical

behavior of released and unreleased devices, the same transistor were characterized before and after release process. The obtained results are described below and show very low changes in the main parameters of the devices.

A. Flexible FinFETs [14] Electrical results are summarized in figure 3 while the

fabrication results can be found in figure 3. To study the behavior of the FinFETs, we first started measuring the I-V characteristics. Figure 3 (a – f) shows a comparison for the same PMOS and NMOS devices before and after peel-off processing. The measured NMOS and PMOS devices have gate length (L) 250 nm and channel width (W) 3.6 mm. The current at saturation with VGS = 1.5V for NMOS and VGS = -1.5V for PMOS at VDS = 1V and -1V respectively are 549 mA/mm for NMOS and 110 mA/mm for PMOS, and 58.48 mA/mm and 7.73 mA/mm at VDS = 50mV and -50mV for NMOS and PMOS respectively. In the case of NMOS, Ion/Ioff ratio is 4.6 decades and for PMOS is 4.78 decades. Ion/Ioff ratio was calculated using Intel Corporation’s method, which states that Ioff should be calculated at Vth minus one third of VDS for non-optimized gate stacks. Gate leakage was also found to be 3.6 A/cm2 for NMOS and 1.18 A/cm2 for PMOS at VGS = 1.5V and VGS = -1.5V respectively. It is to be noted, there is a small current reduction of 7% for NMOS and 12% for PMOS in the saturation region of the transistors.

Vthsat for released and unreleased NMOS was 0.325V and

0.345V respectively and Vthsat for released and unreleased

PMOS was 0.66V and 0.713V respectively. The difference in Vth

sat does not represent a significant change (only 6% for NMOS and 8% for PMOS), therefore confirming the consistency of the process. The comparison between sub-threshold swing for released and unreleased samples also indicates an insignificant change of only 3.4% for NMOS and 2.8% for PMOS. In summary, apart from the 7% for NMOS and 12% for PMOS reduction in the on state current, the devices behave very similarly when comparing released NMOS and PMOS with unreleased NMOS and PMOS.

Fig. 3. Flexible FinFET electrical characteristics.

It is to be noted that PMOS devices were not optimized for Vth during the fabrication process. This causes a large shift of Vth towards the positive side of the gate voltage; however, the difference between released and unreleased PMOS devices differ in only 8% of the original threshold voltage value, showing the consistency of the release process.

B. Planar MOSFETs [15] In order to study the main characteristics of our MOSFETs

we measured the I-V characteristics in both the sub-threshold and linear regions. The results are shown in Figure 6 for a representative device. The current at saturation with VGS = -2 V is -4.4 µA/µm for VDS = -2 V and -0.3 µA/µm for VDS = -100 mV. Ion/Ioff ratio is 3.7 decades and the gate leakage is as small as 70 µA/cm2 at VGS = -1 V. The measured devices have a gate length (L) of 8 µm and a channel width (W) of 5 µm.

In order to have a better understanding of the implications associated with the release method and the related sub-processes, we have compared the electrical performance of a sample before and after release processing. Figure 4 compares the ID-VG transfer characteristics in the saturation and sub-threshold regime of the same transistor before and after release. As can be observed there is a small current reduction, around 2.6%, in the saturation region of the transistor (Figure 4a). In fact, due to the presence of strained oxide on top the silicon for insulation of devices, there is a small residual strain which can contribute to the reduction in current and other parameters, as will be discussed in the upcoming section. The increase in Ioff current, up to one decade, from ~30 pA/mm to ~300 pA/mm, can be related to the reduced substrate thickness, which makes the sample more susceptible to noise or thermal excitation allowing more off-state leakage. Gate leakage current for unreleased and released samples is shown in Figure 4c. We observed a small increase in leakage although it does not represent a significant difference. Additionally we have extracted the threshold voltage (Vth) and the sub-threshold swing (S) from both released and unreleased samples. The threshold voltage in the released sample showed a reduction around 7 %, most likely related to the current reduction, from -0.48 V in the unreleased sample to -0.45 V in the released one. The sub-threshold swing, on the other hand, showed an insignificant change, increasing from 75.24 mV dec-1 in the unreleased sample to 80.3 mV dec-1 in the released one, representing a 6.7 % increase.

Fig. 4. Planar MOSFETs elctrical characteristics.

In summary, besides the off-current, less than 10 % variation in main parameters results from the additional processing related to the release method. This can be attributed to the residual strain as a result of the oxide and other deposited layers on the fabric. On the other hand, even though the Ioff current, and therefore Ion/ Ioff ratio, are significantly affected, the values remain at an acceptable and competitive level.

IV. CONCLUSION State of the art FinFET and planar MOSFET devices have

been demonstrated on a flexible monocrystalline silicon platform starting from standard 8” silicon-on-insulator wafer and 4” bulk silicon wafer respectively. Using only industry standard processes, the flexibility shown is extremely high achieving a minimum-bending radius of 5mm. The results set a major step toward the integration of high performance devices on flexible platforms while keeping the performance and more important the cost yield advantage obtained with silicon based fabrication.

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