Network Security & Cryptographic Sciences NO PRJ

TITLE

ABSTRACT DOMAIN YOP

1

Theoretical

Modeling

of Elliptic

Curve

Scalar

Multiplier

on LUT-

Based

FPGAs for

Area and

Speed

This paper uses a theoretical model to approximate the delay of different characteristic two primitives used in an

elliptic curve scalar multiplier architecture (ECSMA) implemented on k input lookup table (LUT)-based field-

programmable gate arrays. Approximations are used to determine the delay of the critical paths in the ECSMA.

This is then used to theoretically estimate the optimal number of pipeline stages and the ideal placement of each

stage in the ECSMA. This paper illustrates suitable scheduling for performing point addition and doubling in a

pipelined data path of the ECSMA. Finally, detailed analyses, supported with experimental results, are provided

to design the fastest scalar multiplier over generic curves. Experimental results for GF(2163) show that, when

the ECSMA is suitably pipelined, the scalar multiplication can be performed in only 9.5 μs on a Xilinx Virtex V.

Notably the design has an area which is significantly smaller than other reported high-speed designs, which is

due to the better LUT utilization of the underlying field primitives.

Network

Security &

Cryptograph

ic Sciences

2013

2

Efficient

Implementa

tion of

Reconfigur

able

Warped

Digital

Filters With

Variable

Low-Pass,

High-Pass,

Bandpass,

and

Bandstop

Responses

In this brief, an efficient implementation of reconfigurable warped digital filter with variable low-pass, high-

pass, bandpass, and bandstop responses is presented. The warped filters, obtained by replacing each unit delay of

a digital filter with an all-pass filter, are widely used for various audio processing applications. However, warped

filters require first-order all-pass transformation to obtain variable low-pass or high-pass responses, and second-

order all-pass transformation to obtain variable bandpass or bandstop responses. To overcome this drawback, the

proposed method combines the warped filters with the coefficient decimation technique. The proposed

architecture provides variable low-pass or high-pass responses with fine control over cut-off frequency and

variable bandwidth bandpass or bandstop responses at an arbitrary center frequency without updating the filter

coefficients or filter structure. The design example shows that the proposed variable digital filter is simple to

design and offers substantial savings in gate counts and power consumption over other approaches.

Network

Security &

Cryptograph

ic Sciences

2013

3

Off-Chip

Memory

Encryption

and

Integrity

Protection

Based on

AES-GCM

in

Embedded

Systems

Increasing concerns related to off-chip memory security can be observed in nowadays embedded system designs

due to the requirement of high capacity storage of many sensitive and critical information. In this article we

propose a novel architecture for off-chip memory encryption and integrity protection based on Advanced

Encryption Standard - Galois/Counter Mode (AES-GCM). Our approach provides data confidentiality and

integrity authentication at the same time and can safeguard against a series of well-known attacks, including

replay attacks, spoofing attacks and relocation attacks. Besides the security enhancement, our approach also

features a much lower on-chip memory overhead with smaller performance overhead than hash tree based

approaches.

Network

Security &

Cryptograph

ic Sciences

2013

#56, II Floor, Pushpagiri Complex, 17th Cross 8th Main, Opp Water Tank,Vijaynagar,Bangalore-560040.

Website: www.citlprojects.com, Email ID: projects@citlindia.com,hr@citlindia.com

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VLSI PROJECTS – 2013

(Network-Security & Cryptographic Sciences, DSP, Arithematic Core & Digital Electronics, Digital

Communication & Information Theory, Digital Image Proccesing)

4

FPGA-

Based

40.9-

Gbits/s

Masked

AES With

Area

Optimizati

on for

Storage

Area

Network

In order to protect “data-at-rest” in storage area networks from the risk of differential power analysis attacks

without degrading performance, a high-throughput masked advanced encryption standard (AES) engine is

proposed. However, this engine usually adopts the unrolling technique which requires extremely large field

programmable gate array (FPGA) resources. In this brief, we aim to optimize the area for a masked AES with an

unrolled structure. We achieve this by mapping its operations from to as much as possible. We reduce the

number of mapping [ to ] and inverse mapping [ to ] operations of the masked SubBytes step from ten to one. In

order to be compatible, the masked MixColumns, masked AddRoundKey, and masked ShiftRows including the

redundant masking values are carried over . We also use FPGA block RAM (BRAM) to further reduce hardware

resources. Compared with a state-of-the-art design, our implementation reduces the overall area by 36.2%

(20.5% is contributed by the main method, and 15.7% is contributed by the BRAM optimization). It achieves

40.9-Gbits/s at 4.5-Mbits/s/slice on the Xilinx XC6VLX240T platform. We have attacked the iterative version of

this masked AES in hardware. Results show that none of the bytes can be guessed from the masked AES with

the collected 10 000 power traces, but 14 out of 16 bytes can be guessed from the unprotected AES with the

same number of traces.

Network

Security &

Cryptograph

ic Sciences

2013

5

High

performan

ce scalar

multiplicat

ion for

ECC

Wireless Sensor Networks (WSN's) are being widely used in various civilian and military applications. In certain

WSN applications, the data among the nodes and the Base Station (BS), needs to be exchanged in a secure

manner. The encryption and decryption operations over the data involve additional energy overhead. Hence, it is

required to use a security model, which offers security with less computational requirements, as WSN nodes

have resource constraints. Elliptic curve cryptography (ECC), a public key cryptographic system, has lesser key

size requirements in comparison with RSA algorithm. ECC has been gaining acceptance as another alternative to

RSA. In ECC, scalar multiplication accounts for about 80 % of the key calculation time [1]. This work presents

an optimized Sliding Window method with 1's complement technique for scalar multiplication. The same is also

compared with two other methods of scalar multiplication, Binary Method and Non-Adjacent Form (NAF)

method.

Network

Security &

Cryptograph

ic Sciences

2013

6

An efficient

FPGA

implementa

tion of the

Advanced

Encryption

Standard

algorithm

A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in

this paper. This implementation is compared with other works to show the efficiency. The design uses an

iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives

low complexity architecture and easily achieves low latency as well as high throughput. Simulation results,

performance results are presented and compared with previous reported designs.

Network

Security &

Cryptograph

ic Sciences

2012

7

A compact

32-Bit AES

design for

embedded

system

Recently, much research has been conducted for security of data transactions on embedded platforms. Advanced

Encryption Standard (AES) is considered as one of a candidate algorithm for data encryption/decryption. One

important application of this standard is cryptography on smart cards. In this paper we describe a 32-bits

architecture developed for Rijndael algorithm to accelerate execution on 32-bits platforms with reduced

memory. Using the FPGA device xc5vfx70t- 2ff1136-6, a very low-cost implementation of 375 occupied Slices

is obtained under 303.364 MHz frequency.

Network

Security &

Cryptograph

ic Sciences

2012

8

An

Implementa

tion of AES

Algorithm

Based on

FPGA

An implementation of high speed AES algorithm based on FPGA is presented in this paper in order to improve

the safety of data in transmission. The mathematic principle, encryption process and logic structure of AES

algorithm are introduced. So as to reach the porpose of improving the system computing speed, the pipelining

and papallel processing methods were used. The simulation results show that the high-speed AES encryption

algorithm implemented correctly. Using the method of AES encryption the data could be protected effectively.

Network

Security &

Cryptograph

ic Sciences

2012

9

Hardware

efficiency

comparison

Of AES

implementa

tions

The AES algorithm can be implemented in different styles at programming levels. The paper compares the

hardware efficiency of different AES implementations with respect to their area, speed and power performance

especially in two different styles – one using controller and the other one is iterative method. These designs were

described using Verilog HDL, simulated using Modelsim® and prototyped in Altera’s platform FPGA.

Network

Security &

Cryptograph

ic Sciences

2012

10

A Novel

Architectur

e for VLSI

Implementa

tion of RSA

Cryptosyste

m

The RSA system is widely employed in networking applications and achieves good performance and high

security. In this paper, we use Verilog to implement a 16- bit RSA block cipher system. The whole

implementation includes three parts: key generation, encryption and decryption process. The key generation

stage aims to generate a pair of public key and private key, and then the private key will be distributed to

receiver according to certain key distribution schemes. The memory usage and overhead associated with the key

generation is eliminated by the proposed system model. The cipher text can be decrypted at receiver side by

RSA secret key. These are simulated in Xilinx and hardware is synthesized using RTL Compiler. The existing

and proposed models are then analyzed for performance measures using Synopsis-Design Vision. Net list

generated from RTL Compiler will be used to generate IC layout.

Network

Security &

Cryptograph

ic Sciences

2012

11

A FPGA

Design of

AES Core

Architectur

e for

Portable

Hard Disk

This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the

data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power

consumption to comply with minimum speed of 5 Gbps (USB3.0). We proposed the 128 bits data path of two

different AES architectures design, Basic Iterative AES, which reuses the same hardware for all the ten iterations

and , One Stage Sub Pipelined AES, with one stage of outer pipelining in the data blocks that both of them are

purely 128 bits data path architecture that different from the previous public paper. The implementation result on

the targeted FPGA, the basic iterative AES encryption can offer the throughput of 3.85 Gbps at 300 MHz and

one stage sub pipelined AES can offer the throughput to increase the efficiency of 6.2 Gbps at 481 MHz clock

speed. Index Terms- AES, Encrypt/decrypt, USB3.0, FDE, ATM

Network

Security &

Cryptograph

ic Sciences

2012

12

A Novel

Stream

Cipher with

Hash

Function

for the

RFID

Device

In recently years, Radio Frequency Identification (RFID) system in low-cost communication applications is

growing rapidly and deploying widely. Regarding the low-cost RFID device, the design of easy and simplified

circuits must be concerned first; moreover, integrity and encryption issues also must be considered to avoid an

illegal tampering and to secure data between the reader and the tag. In general, the integrity check function

provided by the hash function circuit and the encryption function provided by the stream cipher circuit are

independent. In this paper, the novel stream cipher circuit with hash function in a RFID device is proposed for

integrating integrity and encryption functions, for simplifying the device circuits, and for reducing power

consumption. Besides, the FPGA hardware model is used to implement and to validate our proposed scheme.

Also, the performance of the proposed hardware circuit is given.

Network

Security &

Cryptograph

ic Sciences

2012