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DESCRIPTION
CITL Tech Varsity, a leading institute for assisting academicians M.Tech / MS/ B.Tech / BE (EC, EEE, ETC, CS, IS, DCN, Power Electronics, Communication)/ MCA and BCA students in various Domains & Technologies from past several years. DOMAINS WE ASSIST HARDWARE: Embedded, Robotics, Quadcopter (Flying Robot), Biomedical, Biometric, Automotive, VLSI, Wireless (GSM,GPS, GPRS, RFID, Bluetooth, Zigbee), Embedded Android. SOFTWARE Cloud Computing, Mobile Computing, Wireless Sensor Network, Network Security, Networking, Wireless Network, Data Mining, Web mining, Data Engineering, Cyber Crime, Android for application development. SIMULATION: Image Processing, Power Electronics, Power Systems, Communication, Biomedical, Geo Science & Remote Sensing, Digital Signal processing, Vanets, Wireless Sensor network, Mobile ad-hoc networks TECHNOLOGIES WE WORK: Embedded (8051, PIC, ARM7, ARM9, Embd C), VLSI (Verilog, VHDL, Xilinx), Embedded Android JAVA / J2EE, XML, PHP, SOA, Dotnet, Java Android. Matlab and NS2 TRAINING METHODOLOGY 1. Train you on the technology as per the project requirement 2. IEEE paper explanation, Flow of the project, System Design. 3. Algorithm implementation & Explanation. 4. Project Execution & Demo. 5. Provide Documentation & Presentation of the projectTRANSCRIPT
Bus Protocols And System On Chip
1
FPGA based
implementation
of a double
precision IEEE
floating-point
adder
Floating-Point addition imposes a great challenge during implementation of
complex algorithm in hard real-time due to the enormous computational burden
associated with repeated calculations with high precision numbers. Moreover, at the
hardware level, any basic addition or subtraction circuit has to incorporate the
alignment of the significands. This paper presents a novel technique to implement a
double precision IEEE floating-point adder that can complete the operation within
two clock cycles. The proposed technique has exhibited improvement in the latency
and also in the operational chip area management. The proposed double precision
IEEE floating-point adder has been implemented with XC2V6000 and XC3S1500
Xilinx© FPGA devices
Bus
Protocols
and System
on Chip
2012
2
Design and
Functional
Verification of
I2C Master Core
using OVM
This paper contrasts physical implementation aspects of the protocol through a
number of recent Xilinx’s FPGA families, showing up the protocol features are
responsible of substantial area overhead and power overhead. These help designers
to make careful and tightly tailored architecture decisions. These RTL coding is
carried out for the I2C protocol using the HDL code. The verification methodology
carries a important role in design of the VLSI, As the functional verification of the
I2C is covered using Open Verification Methodology (OVM) which does not
interfere with DUT. This verification method provides the I2C with fault free and
useable for modern day applications. The OVM is carried using Questasim10.0b.
Bus
Protocols
and System
on Chip
2012
#56, II Floor, Pushpagiri Complex, 17th Cross 8th Main, Opp Water Tank,Vijaynagar,Bangalore-560040.
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VLSI – 2013
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics, Digital
Communications and Information theory, Digital Image Processing, Bus Protocols and System on Chip