Analysis and Reduction of Noise in Fractional PLL

Govind Singh Patel ECED, Lingayas University

Faridabad, India Email:govindpatel99@rediffmail.com

Abstract: The aim of this paper is analysis and presenting a technique to reduce phase noise in fractional frequency synthesizer for pure signal synthesis. To reduce phase noise of synthesizer, first, we present a mathematical and accurate model of noise in Phase Locked Loop(PLL) based fractional frequency synthesizer with take into account noise of its component. Then we predict output phase noise in term of its parameters. Finally, we describe as effective technique for noise in fractional frequency synthesizer by CppSim simulator. The Behavioral Simulation results show the performance of the fractional frequency synthesizer. Keywords: PLL, Noise Reduction and Fractional Frequency Synthesis.

I. INTRODUCTION PLL fractional frequency synthesizers are widely used in telecommunication receiver and transmitters and radar system, as part of the frequency conversion block. Purity of output frequency spectrum affects on the quality of data transmission and bandwidth optimization in communication systems as well as sensitivity and range resolution in radar systems. Reduction of phase noise and spurs is one of challenges in PLL fractional frequency synthesizer design. Moreover, the PLL must comply with the frequency hopping requirement. This model is useful to determine the impact of various system noise sources on overall synthesizer behavior. The term phase noise is used to describe phase fluctuations due to the random frequency fluctuations of signal. One of the major issues facing synthesizer designers is the phase noise phenomenon. Phase noise is an undesirable entity that is present in all real world oscillators and signal generators. It can cause distortion or complete loss of incoming information in traditional receivers, and it introduces high bit error rates in modern phase modulated applications. It is, therefore, necessary to understand and quality phase noise so that its effects on the higher level product are minimized. Phase and frequency noise and its effect on the performance of synthesizer have been the subject of numerous studies. This paper first presents an exact analysis of noise contribution in fractional frequency synthesizer and then, based on presented analysis, proposes a new technique to reduce output phase noise. The technique exploits the feature of loop filter to reduce the noise on the input of voltage controlled oscillator (VCO) in the phase lock mode. The noise sources in all building blocks of a PLL contribute to the noise power spectral density of an output signal[1].

Sanjay Sharma ECED, Thapar, University,

Patiala, India Email: sanjay.sharma@thapar.edu

Noise sources in the circuit can be divided into two groups, namely device noise and interference. Thermal, shot and flicker noise are examples of the former, while substrate and supply noise are in the latter group. Noise sources in PLL are: Input reference noise, loop filter noise, charge-pump noise and VCO noise. Transfer characteristics of individual noise sources are explained and phase noise of the PLL system is analyzed. Since charge pump is a discrete-time system, as long as the dynamics of the loop are much slower than the signal, it can be considered continues system. Noise contribution in PLL based synthesizer, require having a model that we can analysis the effect of each noise source into output phase noise. In locked condition, the PLL acts similar to a LTI system and hence the superposition holds[2].

II. ARCHITECTURE A. Phase Locked Loop One popular misconception regarding fractional N PLLs is that they require different design equation and simulation techniques than are used for integer N PLLs. In actually, the exact same concepts and equations apply to fractional PLLs that apply to integer PLLs. The performance is different, due to the fact the N value is can be made smaller, which is a consequence of some fractions being allowed. The whole motivation of using a fractional N architecture is that it has a smaller N value, which theoretically means that it will have better phase noise performance. A Phase Locked Loop is a closed loop control system which is used for the purpose of synchronization of the frequency and phase of a locally generated signal with that of an incoming signal. It is basically a nonlinear (the phase detector is a nonlinear device) feedback loop, as shown in Fig. 1. The PLL consists of a voltage controlled oscillator (VCO), a phase detector, a variety of dividers, and a loop filter. The VCO is a device whose output frequency depends on the input control voltage. The relation is nonlinear but monotonic. However, when locked, the VCO can be assumed to be linear; it is both practical and convenient for analytical purposes.

Fig. 1 PLL block diagram.

2012 International Symposium on Computer, Consumer and Control

978-0-7695-4655-1/12 $26.00 © 2012 IEEE

DOI 10.1109/IS3C.2012.134

503

2012 International Symposium on Computer, Consumer and Control

978-0-7695-4655-1/12 $26.00 © 2012 IEEE

DOI 10.1109/IS3C.2012.134

507

Variation in the VCO control characteristics (i.e., this nonlinearity) affects the loop parameters, and loop linearization (or compensation) is used extensively. Generally, the VCO output waveform is given by

outA ( )[ ]νω,t = ( )ν,tA sin ( )[ ]ϕνω +t (1) Where A is the signal amplitude and ω is the angular frequency, both depending on time t , and control voltage v. As a first approximation, we assume that A has a constant envelope (does not depend on t or v) and that ω is a linear function of v. Therefore we can write eq. (1) as

outA ( )t = Α sin ( )[ ]ϕνω ν ++ tK0 (2) Here Kv is the VCO constant [rad/(Vs)]. Since we assume that the frequency is linearly dependent on v and is given by

( )νω = νω νK+0 (3) As mentioned, the linearization is justified and is assumed for the purpose of simpler analysis. In reality, when the loop is locked, frequency variations are tiny, and the constant-VCO assumption is correct as a piecewise linearization of the graph in fig. Since phase is the integral of the angular frequency, we can complete the approximation by writing that the VCO transfer function, given by

Vs)(0ϕ

= s

Kv (4)

As the Laplace transfer function of the VCO output phase. The phase detector produces an output voltage proportional to the difference in phase between its inputs and is always a nonlinear function. Typical phase detector output transfer functions are shown in fig. However, close to the locked position this function can be assumed to be linear (this is also justified since in the locked condition most frequency synthesizers operate with a very high signal-to-noise ratio and the phase detector therefore operates mainly at a fixed-phase position). Hence

dV = ( )0ϕϕ −idK V/rad (5) Where Vd is the phase detector output voltage. Now the loop transfer functions can be described as

dV = ( ) ( )[ ]ssK oid ϕϕ − V/rad (6) Let

cV = ( ) ( )sFsVd control voltage Where F(s) is the loop filter transfer function and Vc is the VCO control voltage. Solving these simple equations yields

( )s0ϕ = )()()(

sFKKssFKKs

dv

vdi

+ϕ

(7)

and the transfer function H(s)= φo(s)/ φi(s) is given by

( )sH =)(

)(sFKKs

sFKK

dv

vd

+ (8)

Also, following these equations will show that the error transfer function, defined as

( )sH e = )(

)()(s

ss

i

oi

ϕϕϕ −

(9)

is given by

( )sH e =)(sFKKs

s

vd+ (10)

Since we linearzed all components, given Kv and Kd, the feedback loop behavior depends mainly on F(s)[3]. B. Role of Charge pump in PLL A basic charge pump circuit is shown in Fig.2. That schematic illustrates that P0 is a p-type MOSFET, N0 is an n-type MOSFET, Ip and In are current sources which provide identical current I0. C is a large capacitor. INC and DEC are the control signals which are applied to the gates of P0 and N0, respectively. During INC at logic low, P0 is turned on, the capacitor C is charged in the current I0 through Ip and P0. During DEC at logic high, N0 is turned on, the capacitor C is discharged in the current I0 through In and N0. The voltage across the capacitor C, Vc, controls the oscillator frequency of VCO. When Vc increases, the VCO frequency increases. When Vc decreases, the VCO frequency decreases. The control signals, INC and DEC, are from the phase detector. When the phase detector needs to increase the VCO frequency, it increases the negative pulse width of INC and decreases the positive pulse width of DEC so that the P0 turn-on time increases and the N0 turn-on time decreases. Since the current sources Ip and In always provide constant current I0, the electrical charge amount and the electrical discharge amount are proportional to the P0 turn-on time and the N0 turn-on time respectively. The long P0 turn-on time and the short N0 turn-on time make the net electrical charge for a pair of INC and DEC to be pumped into the capacitor C to increase Vc. When the phase detector needs to decrease the VCO frequency, it decreases the negative pulse width of INC and increases the positive pulse width of DEC, so that the net electrical charge for a pair of INC and DEC is pumped out from the capacitor C to decrease Vc. When the PLL is locked, the negative pulse width of P0 and the positive pulse width of N0 are set to a small and identical value so that the net electrical charge is zero, Vc stays unchanged. Therefore, it is an essential requirement that the charge and discharge in a charge pump must be controlled by the INC and DEC pulse width.

Fig. 2. Charge pump schematic

C. Role of Sigma Delta Modulator (SDM)

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It is used to change the value of the frequency division at a high rate compared to the bandwidth of PLL so that, over time, the frequency is effectively divided by an average value that is fractional rather than integer. The resolution of these fractional values is determined by the length of the accumulators making up the SDM. To overcome the spurious signal generation problem, a fractional frequency synthesizer can exploit noise shaping in a MASH SDM in a similar way that analog to digital conversion utilizes this behavior. In a typical frequency synthesizer the low-pass filtering operation is carried out on the quantization noise by the loop filter. A third order MASH Σ−Modulator is used in this design that exhibits by a 3rd-order noise transfer function and a 5-bit output. The SDM provides density modulated high frequency representations of fractional numbers. These signals are desirable for frequency synthesis because high-frequency noise can be filtered out by the loop filter while low frequency noise has been suppressed by the noise transfer function in the SDM. The loop reaches locked states when the reference and divided output signals have the same frequency and phase. As long as the dynamics of the loop are much slower than the signal, the charge-pump can be treated as a continuous time integrator. Thus, by use of average value of discrete-time parameters, the PLL can be analyzed as a continues-time system. When the PLL is in lock state, it is possible to use the linear approximation. It is very useful for PLL stability and phase noise contribution analysis[4].

III. PHASE NOISE MODELING AND BEHAVIOR In this section we investigate the causes and behavior of phase noise and presents mathematical models in order to understand it. A. Accounting for the N Divider and Closed Loop Transfer Function- Phase Noise Floor The closed loop transfer function can be approximated by the N divider value, provided that the offset frequency is within the loop bandwidth. Since phase noise is caused by a noise voltage, the noise power would be proportional to N2, hence this implies that phase noise varies as 20*log(N). The phase noise floor is this constant value and is calculated below.

⎪⎩

⎪⎨⎧

+

+≈=

)(log*20

log*20)(

offsetCLFloorPhaseNoise

NFloorPhaseNoiseoffsetPLLnoiseflat

-------- (11) B. PLL Flat Noise Calculation In this case, the comparison frequency must change as well. This could be the case when one is using a fractional PLL and wanting to know the impact of changing the N counter, which corresponds to raising Fcomp. The phase noise in this case varies as 10*log(N).

⎪⎩

⎪⎨⎧

++

++≈=

)(log*20log*101

log*20log*101

offsetCLFcompHzPN

NFcompHzPNPLLnoiseflat

-------------------- (12) PN1Hz=1 Hz Normalized Phase Noise Floor, Fcomp=Comparison Frequency, CL=Closed Loop C. Accounting for the 1/f Noise in the PLL Noise Estimate In actually, it is more correct to say that the phase noise is flat past a certain offset, but for frequencies less than some offset, the 1/f noise needs to be taken into consideration. In general, this noise decreases by 10 dB/decade and a simple way to characterize this is to normalize it to 10 kHz offset frequency and a 1 GHz PLL out put frequency, PN10kHz. The 1/f noise and the flat noise can be added together after the appropriate transfer function is applied in order to determine the PLL noise contribution[5].

kHzoffset

GhzFoutkHzPNoffsetFoutPLLnoisef 10

log*101

log*2010),(/1 −+−

------------------------- (13)

Fig. 3. Sources of noise in PLL

Parameterize Noise Transfer Functions in Terms of G(f):

1) PFD- Referred Noise

)/1)(/()()2/(1)/()(

NjfKfHIjkKfHI

e vcp

vcp

n

o

παφ

+=

)(2)(1

)(2 fNGfA

fANαπ

απ =

+ (14)

2)VCO- referred noise

)/1)(/()()2(11

NjkKfHI vcpvn

o

παφ

φ+

=

= )(1)(1

)(1)(1

1 fGfA

fAfA

−=+

−=+

(15)

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3) Contribution of charge pump noise to overall output noise

esothersourcfSfDI

fScpmout I

cp

+= )()()2()1()( 222

απ

φ (16)

Table 1. Parameters of fractional SD frequency synthesizer:

Symbol Description Value Units Kv VCO gain 50 MHz/V Kd Phase detector gain 100 μA Kp Loop filter gain 2.8e12 - BW Loop Band Width 1 MHz Fz Loop filter zero 1.11 MHz Fp Loop filter pole 2.87 MHz F1 First parasitic pole 500 KHz F2 Second parasitic pole 1 MHz Rf Ref. Freq. 50 MHz

Output frequency: 3.6GHz. Noise: -151 dBc/Hz at 20 MHz offset(3.8 GHz carrier), Evaluate Noise Performance with 1 MHz PLL BW, G(f) Parameters: 1MHz BW, Type II, 2nd order rolloff, extra pole at 2.5 MHz, Output referred charge pump noise:-104dBc/Hz, VCO noise: 155dBc/Hz at 20 Mhz offset(3.6 Ghz carrier)[6].

Fig.4. Calculated Phase noise for classical fractional –N synthesizer

Fig. 5 Time Response of Closed Loop System

Fig 6. Output Phase Noise of Convention System

IV. PROPOSED TECHNIQUE TO REDUCE PHASE NOISE

Fractional-N frequency synthesis based on ∆∑ modulation offers wide bandwidth with narrow channel spacing and alleviates PLL, design constraints for phase noise and reference spur. However, the synthesizer phase noise performance is significantly affected by the high frequency out-of-band noise. Comparing the output bit patterns of the high order modulator and the MASH, the former can achieve more desirable noise shaping for frequency synthesis, but the latter offers a simpler high order solution with no stability problem. In general, multi-bit modulators have no linearity problem in the digital domain, but when they are combined with PLL, the nonlinearity of the phase detector is a concern. The MASH –type modulators generates wide spread high frequency bit patterns , and impose more stringent requirements on the phase detector design for linearity[7]. This work uses a 3b 3rd-order modulator that generates less high frequency noise

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and makes the system less sensitive to the phase detector nonlinearity.

Fig.7 Proposed Frequency Synthesizer

Fig. 8. Output Phase Noise of Proposed System

The "Accumulate Circuit+VCO+Divider" is the heart of PLL which return the average of input during the period of its clock, is shown in Fig. 7. As much as the period of clock is longer, the averaging interval is larger and so the variations of its input signal become more attenuated. Now suppose that the system start with unlocked condition and finally reach to locked condition. As a matter of fact we have to select a short clock period first and gradually selecting longer clock period. Thus, before the locking of the system, the period of clock must be short and then while the system getting into locked, this period should be long. For this reason we use a mechanism that with increasing the VCO input voltage, the period of clock of accumulates circuit being longer. The clock frequency of circuit gets from the input reference that trough the divider. As increasing the VCO input voltage the divider value increasing and so the period of clock is longer and therefore the variation on the VCO input voltage is smoothing. The Gain adjusts the rate of increasing of divider value relative to increasing VCO input voltage. The value of Gain should be sufficient. If its value is large, the clock period of circuit may be very long and system unstable. If the value of Gain is small, the clock period of circuit may be short and the phase noise reduction not satisfied. The optimum value of Gain depends on reference frequency and VCO input voltage. The resulting phase noise spectrum is shown in the Fig. 8. Comparison of Fig. 6. and Fig.8 shows that Accumulate

Circuit is much slower than the conventional structure as expected. This technique causes to reduce the output phase noise due to the VCO noise[8]. This result can be easily understood noting that the VCO acts as an ideal integrator. So, reduction of this noise causes to reduction of output phase noise in a particular frequency range that the effect of VCO noise is dominant.

V. CONCLUSION

The work addresses the phase noise of PLL based fractional frequency synthesizer. We presented noise contribution of a 3rd MASH frequency synthesizer for wireless communication system. Then the transfer function of each noise sources based on linear model of PLL in locked condition has been derived and the output phase noise due to individual noise source has been shown. Based on performed analysis, we have described a new architecture of phase locked loop for reduction of phase noise and verified of its operation with a behavioral model description in CppSim simulator. The results show a good performance on the reduction of output phase noise.

REFERENCES

[1]. Bar-Giora Goldberg, Digital Frequency Synthesis Demystified, 3rd edition, LLH Technology Publishing, 1999. [2]. Roland E. Best, Phase-Locked Loops: Design, Simulation & Applications, 4th Edition, McGraw-Hill Professional Engineering, 2003. [3]. A. Bonfanti, F. Amorosa, C. Samori, and A. L. Lacaita, “A DDS based PLL for 2.45 GHz Freq. Synthesis”, IEEE transactions on circuits and systems -ii: analog and digital signal processing, December 2003,vol. 50, no. 12. [4]. Woogeun Rhee, Bang-Sup Song, and Akbar Ali, “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order Modulator”, IEEE journal of solid-state circuits, October 2000, s vol. 35, no. 10. [5].D. Banerjee, PLL Performance, Simulation and Design, Handbook'. 2008. [6].Perrot M, “Fast and Accurate behavioral simulation of Fractional –N Freq. synthesizer and other PLL/DLL circuits”, Proceeding of the IEEE 39th Annual design automation conf. , pp. 498-503. [7]. Perrott, M.H., Trott, M.D., and Sodini, C.G., “A Modeling Approach for Sigma-Delta Fractional-N Frequency synthesizers Allowing Straightforward Noise Analysis”, IEEE J. Solid-State Circuits, Vol. 37, No. 8,2002, pp. 1028-1038. [8]. A. Telba, J. M. Noras, M. Abou El Ela and B.AIMashaq, “Simulation Technique for Noise and Timing Jitter in phase Locked Loop”, IEEE transactions on simulation technique, Aug. 2004,pp. 501-504.

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