A Simple Modulation Scheme for aThree-Phase Direct Matrix Converter

Marcelo A. Perez, Christian A. Rojas, Jose RodriguezUniversidad Tecnica Federico Santa Maria

Electronics Engineering Department

Valparaıso, Chile

Email: marcelo.perez@usm.cl

Haitham Abu-RubTexas A&M University at Qatar

Department of Electrical & Computer Engineering

Doha, Qatar

Email: haitham.abu-rub@qatar.tamu.edu

Abstract—The direct matrix converter (DMC) is an AC-to-AC direct power conversion topology based on controlled bi-directional switches that can generate variable output voltagesand sinusoidal source currents with controllable displacementpower factor at the input side. The topology is characterized byits reduced size and weight compared to Voltage Source Invertersbecause the lack of dc-link stage. However, its modulation israther complex due to the high number of switching states andthe fact that they are not constant.

In this work a new PWM strategy based on the translation of2L-PWM converter to the DMC is presented. The modulationscheme is developed using a simple logic functions. Resultsfrom open and closed loop tests are presented to validate thecorrectness of proposed modulation.

I. INTRODUCTION

Power electronics converters are used in cases where the

features of the source voltage do not satisfy the load require-

ments. Electrical speed drives and active filters are the most

common applications of power converters. The classical speed

drive is based on a two-stage conversion topology composed

by a rectifier, a dc-link stage and an inverter, where the dc-link

is a bulky capacitor or inductor. One alternative to reduce the

size of the drive is the Direct Matrix Converter (DMC), where

the two stage back-to-back connection system is replaced by

an array of bi-directional controlled power valves [1], [2].

The main advantage of this converter is reduced volume and

weight due to the absence of the dc-link stage; furthermore

the DMC can generate load waveforms of variable magnitude

and frequency during motoring and regeneration.

Since the first modulation technique proposed by Alesina

and Venturini, also called direct transfer function (DTF) mod-

ulation [1], several modulation methods have been proposed.

However, up to now, the Space Vector Modulation (SVM)

is the well-known and commonly used modulation method

[3], [4], due to its high performance and relative simplicity

compared with DTF modulation. Several optimizations of

SVM have been studied and implemented to increase the

output current quality and solve issues related to the input

current phase displacement, common-mode voltage reduction

and distorted power sources [5]–[9]. The design of the input

filter is another important issue in the operation of the DMC.

Design guidelines for the filter can be found in [10], [11].

Some industrial applications and modulation schemes used

in DMC are reported in [12]–[14], where a PWM switching

pattern is needed to set the commutation instants in a specific

switching period. These intervals are set according to the

instantaneous value of the detected input voltage. This is

the concept called fictitious source voltage, and it is used to

develop the proposed modulation strategy.

The main contribution of this paper proposing a simple

modulation method for DMC with possibility of controlling

the input current displacement, hence the input power factor.

The DMC firing pulses are generated using a logic circuit

that uses the input voltage and a 2L-PWM modulation of the

desired output voltage. The modulation scheme for the 2L-

PWM is based on the well known sinusoidal PWM with min-

max sequence injection [15].

The paper is organized as follows: Section II gives a brief

review of DMC power circuit and its system model. Section

III presents the proposed modulation strategy for the direct

matrix converter. Section IV shows a close loop control using

the proposed modulation, while the conclusions are given in

Section V.

Fig. 1. Three-phase Direct Matrix Converter power topology.

978-1-4673-0158-9/12/$31.00 ©2012 IEEE 105

Fig. 2. Proposed modulation strategy.

II. DIRECT MATRIX CONVERTER

The direct matrix converter (DMC) is a converter alternative

that replaces rectifier, inverter and energy storage stages with

a single-stage storage-less converter composed by an array of

m×n bidirectional controlled switches to connect, an m-phase

voltage source to an n-phase load [1]. The topology considered

in this paper is a three-phase to three-phase direct matrix

converter (3×3 DMC) shown in Fig. 1, where 9 bidirectional

switches are used to connect each output phase to any of the

input phases. The output voltage of the converter is given by

vo = M · S · vi, (1)

where

vo = [voa vob voc]T , (2)

vi = [viA viB viC ]T , (3)

M =1

3

⎡⎣ 2 −1 −1

−1 2 −1−1 −1 2

⎤⎦ , (4)

and the switching matrix is given by

S =

⎡⎣ SAa SAb SAc

SBa SBb SBc

SCa SCb SCc

⎤⎦ . (5)

Each switching state Sx is 1 if the switching is ON and 0

if the corresponding switching is OFF.

On the other hand the input current is given by

ii = ST · io, (6)

where

io = [ioa iob ioc]T , (7)

ii = [iiA iiB iiC ]T . (8)

The bi-directional switches commutation should be con-

trolled under two principles. The first one is avoiding an input

line-to-line short circuit and the second one is avoiding load

open circuits [1]. To satisfy these restrictions, a stepped com-

mutation strategy is needed (generally 4-step commutation)

[9], [12]. In this work ideal commutation and switches are

considered for simplicity.

An LC filter is usually required at the input of the DMC

to reduce the high frequency current harmonics due to the

commutation operation (2), (8). The converter dynamic model

TABLE IDMC SWITCHING STATES AND OUTPUT VOLTAGES

DMC state (SDMC) Switches ON voa, vob, voc

1 SAa SAb SAc viA, viA, viA2 SAa SAb SBc viA, viA, viB3 SAa SAb SCc viA, viA, viC4 SAa SBb SAc viA, viB , viA5 SAa SBb SBc viA, viB , viB6 SAa SBb SCc viA, viB , viC7 SAa SCb SAc viA, viC , viA8 SAa SCb SBc viA, viC , viB9 SAa SCb SCc viA, viC , viC10 SBa SAb SAc viB , viA, viA11 SBa SAb SBc viB , viA, viB12 SBa SAb SCc viB , viA, viC13 SBa SBb SAc viB , viB , viA14 SBa SBb SBc viB , viB , viB15 SBa SBb SCc viB , viB , viC16 SBa SCb SAc viB , viC , viA17 SBa SCb SBc viB , viC , viB18 SBa SCb SCc viB , viC , viC19 SCa SAb SAc viC , viA, viA20 SCa SAb SBc viC , viA, viB21 SCa SAb SCc viC , viA, viC22 SCa SBb SAc viC , viB , viA23 SCa SBb SBc viC , viB , viB24 SCa SBb SCc viC , viB , viC25 SCa SCb SAc viC , viC , viA26 SCa SCb SBc viC , viC , viB27 SCa SCb SCc viC , viC , viC

is given by the filter capacitor voltage vi and the source current

is it is defined as,

vs = Ld

dtis + vi, (9)

is = Cd

dtvi + ii, (10)

where

vs = [vsA vsB vsC ]T , (11)

is = [isA isB isC ]T . (12)

If the input filter is considered, a compensation method of

the displacement angle caused by the input filter is needed, to

achieve a source current in phase with the source voltage [5].

This work is focused in the development of a simple

modulation technique for the DMC, for this reason the input

side is considered ideal and the input filter is not considered

in the analysis.

III. MODULATION STRATEGY

The fundamental of any modulation method is to synthesize

the load voltage reference v∗o, defined as

v∗o = [v∗oa v∗ob v∗oc]

T , (13)

using the switching states of the converter.

The modulation proposed in this paper is based on a two-

level pulse width modulation (2L-PWM) translated to the

DMC feasible states, as illustrated in Fig. 2. The modulation

scheme requires a 2L three-phase carrier based PWM, which

106

Fig. 3. Block diagram of the 2L-PWM modulation.

generates a three-phase switching pattern (s2L) given an output

voltage reference (v∗o). On the other hand, a sector detection

block determined the input voltages which will be used to

synthesize the output voltages. This sector detection uses a

modified input voltage (v∗i ), created by the phase adjustment

block, in order to control the input current angle. Once the

sector Ns is detected, it is possible to determine which DMC

state (SDMC) better synthesizes the output voltage reference

using a translation of the 2L-PWM switching pattern. Finally,

the resulting state is converted to switching pulses (SXy) and

sent to the converter. Next sections will describe these blocks

in detail.

A. DMC Modulation

In order to avoid short circuits at the input side only one

switch per output phase can be ON, and to avoid open circuit

of the load only one switch per output phase must be ON.

These restrictions reduce to 27 the feasible DMC switching

states [1]. These states are shown in Table I, where the first

column shows the state number SDMC, the second column

shows the switches SXy turned ON and the third column

shows which input voltage is sink to the output voltage for

each corresponding DMC switching state.

B. Two-level three-phase PWM

A carrier-based modulation scheme is used to generate

the switching pattern. The modulator compares the reference

with the carrier signal vcarrier, generating the 2L-PWM state

so = [sA sB sC ]T . Each sX has two possible levels: 1 and

0. There are eight combinations of switching states and each

one is assigned to one value of s2L corresponding to its binary

representation as shown in Table II. The third column of the

table shows the output voltage of each state considering a

minimum and maximum voltage value of a fictitious DC link.

A min-max technique is used to increase the voltage gain

[15]. The output of the min-max block is given by

v∗o = v∗

o +max(v∗

o)−min(v∗o)

2. (14)

The complete algorithm is shown in Fig. 3.

C. Sector Detection

To determine which input voltages better synthesize the

required output reference, it is necessary to detect which is

the higher and lower input voltages. Creating a fictitious DC

link will be used by the 2L-PWM. According to Fig. 4, there

are six sectors in which the maximum and minimum voltages

change. The maximum and minimum voltage in each one of

these sectors are shown in Table III.

TABLE II2L-PWM SWITCHING STATES

2L-PWM state (s2L) sA sB sC voa vob voc

0 0 0 0 vmin vmin vmin

1 0 0 1 vmin vmin vmax

2 0 1 0 vmin vmax vmin

3 0 1 1 vmin vmax vmax

4 1 0 0 vmax vmin vmin

5 1 0 1 vmax vmin vmax

6 1 1 0 vmax vmax vmin

7 1 1 1 vmax vmax vmax

viA viB viC

ωt

vi

0

1 2 3 4 5 66 Ns

Fig. 4. Sector definition for an ideal three-phase input voltage.

TABLE IIISECTOR VOLTAGES

Sector (Ns) 1 2 3 4 5 6

vmax viA viA viB viB viC viCvmin viB viC viC viA viA viB

D. 2L-PWM to DMC modulation translation

In each sector defined by Table III the PWM states from

Table II can be synthesized using a combination of the

corresponding vmin and vmax. This combination corresponds,

in turn, to a one of the DMC switching states shown in Table

I.

For example, in sector Ns = 1, vmax = viA and vmin = viB .

To generate first 2L-PMW state s2L = 0 the output voltage

must be vo = [viB viB viB ] which corresponds to the DMC

state SDMC = 14. To generate the second 2L-PWM state

s2L = 1 the output voltage must be vo = [viB viB viA]which corresponds to the DMC state SDMC = 13.

Table IV shows the complete translation from the eight 2L-

PWM switching states to 21 of the 27 DMC switching states

in each one of the six sectors. Once the required DMC state is

known, the three switches that must be ON are obtained from

Table I.

It is interesting to note that six states of the DMC are not

in the translation table. These states correspond to the rotating

vectors which its output voltage is composed by a combination

of the three input voltages.

Fig. 5 shows the simulation results of the proposed mod-

ulation. The parameters of the simulation are given in Table

V. The simulation consists on a step change of output voltage

reference from 125[V]/35[Hz] to 250[V]/70[Hz] at 0.06[s].

The output current changes from 9.4 to 15[A]. The input

107

TABLE IV2L-PWM STATE TO DMC STATE TRANSLATION

Sector (Ns)

2L-PWM State (s2L) 1 2 3 4 5 6

0 14 27 27 1 1 141 13 25 26 2 3 152 11 21 24 4 7 173 10 19 23 5 9 184 5 9 18 10 19 235 4 7 17 11 21 246 2 3 15 13 25 267 1 1 14 14 27 27

current is always in phase with the input voltage and its

fundamental component change from 5.7 to 14[A].

E. Phase adjustment

The modulation calculates the switching states based on the

input voltage, therefore, the input current is always in phase

with it. However, it is possible to use a shifted version of the

input voltage to feed the sector detection block to produce a

change in the angle of the input current.

The shifted voltage is generated using the following shifting

matrix

vi =

⎡⎣ k1(φi) k2(φi) k3(φi)

k3(φi) k1(φi) k2(φi)k2(φi) k3(φi) k1(φi)

⎤⎦vi (15)

where the variables kn(φi) must be calculated to produce a

voltage with a given phase angle φi in respect to the input

voltage.

Considering ‖ vi ‖=‖ vi ‖, the variables kn(φi) can be

calculated using

k1(φi) =2 cos(φi) + 1

3, (16)

k2(φi) = −2 cos(φi + 2π/3) + 1

3, (17)

k3(φi) =2 cos(φi − 2π/3) + 1

3. (18)

Fig. 6 shows the implemented diagram of phase adjustment

strategy.

Fig. 7 shows the simulation results of the proposed mod-

ulation using the phase adjustment block. The simulation

parameters are the same of Fig. 5. The simulation consists of a

step change of input phase from 0 to +30◦ at 0.02[s] and then

to −30◦ at 0.06[s]. The output voltage reference is constant

during all the experiment. The input current is displaced from

the input voltage accordingly with the input current reference

as shown in Fig. 7 c). The output voltage and current do not

change.

F. Simplified Implementation

It is possible to further simplify the implementation defining

the following variables

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−500

0

500

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−20

0

20

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

0

−500

500

Fig. 5. Simulation results of the proposed modulation. a) Output voltage andreference. b) Output current. c) Input voltage and current.

TABLE VSYSTEM PARAMETERS

System Parameters Description Value

Vi Voltage source rms line to line 380[V]fvi Source frequency 50[Hz]fsw Carrier frequency 10[kHz]fo Output frequency 35-70[Hz]Ro Load resistance 10[Ω]Lo Load inductance 15[mH]

xab =

{1, if va ≥ vb0, if va < vb

(19)

xbc =

{1, if vb ≥ vc0, if vb < vc

(20)

xca =

{1, if vc ≥ va0, if vc < va

(21)

The combination of these variables can be used to define

each one of the sectors. For example xabxca will be 1 only in

sector 1, xbcxab will be 1 only in sector 2, and so on. Using

these variables and combining Tables I and IV it is possible

to obtain:

SAa = sAxabxca + sAxabxca, (22)

SAb = sAxbcxab + sAxbcxab, (23)

SAc = sAxcaxbc + sAxcaxbc, (24)

SBa = sBxabxca + sBxabxca, (25)

SBb = sBxbcxab + sBxbcxab, (26)

SBc = sBxcaxbc + sBxcaxbc, (27)

SCa = sCxabxca + sC xabxca, (28)

SCb = sCxbcxab + sC xbcxab, (29)

SCc = sCxcaxbc + sC xcaxbc. (30)

108

Fig. 6. Block diagram of phase adjustment strategy.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−500

0

500

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−20

−10

0

10

20

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−50

0

50

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

0

−500

500

Fig. 7. Simulation results of the proposed modulation using the phaseadjustment scheme. a) Output voltage and reference. b) Output current. c)Input voltage and current. d) Input phase φi.

Therefore, using this approach, the switching signals for the

DMC can be obtained directly from a logical function avoiding

the use of tables and greatly simplifying its implementation.

IV. CONTROL SCHEME

A closed-loop operation is tested using the proposed mod-

ulation. Fig. 8 shows the complete control system. The output

current is controlled in dq frame using PI control to generate

the output voltage reference [16]. The input reactive power is

controlled using a PI, an asin() function is used to obtain the

required phase angle. The input reactive power is calculated

using

qi = iiTJvi, (31)

with

J =1√3

⎡⎣ 0 1 −1

−1 0 11 −1 0

⎤⎦ . (32)

Fig. 8. Load current control and input reactive power control schemes usingthe proposed modulation.

0 0.05 0.1 0.15 0.2 0.25 0.3−1000

0

1000

2000

0 0.05 0.1 0.15 0.2 0.25 0.3−1000

0

1000

2000

0 0.05 0.1 0.15 0.2 0.25 0.3−20

0

20

Fig. 9. Load current and input reactive power control of DMC. a) Outputdirect and quadrature currents. b) Output active power. c) Input active andreactive power.

Due to the PWM nature of the input current the obtained

reactive power is filtered to obtain qi which is used for the

reactive power loop.

With the angle, the input voltage and output voltage refer-

ence the switching pattern is generated.

Fig. 9 shows the change of the output current i∗od from 5A

to 10A at 0.05 while i∗oq = 0 and then the change of the input

reactive power reference q∗i from 0 to 500[V Ar] at 0.1[s] and

to −500[V Ar] at 0.2[s]. The control of the output current has

a very fast dynamic, however the control of the input reactive

current is slow due to the used filter. It is possible to note that

109

both variables are decoupled in steady state and have only a

small disturbance when the step change takes place.

V. CONCLUSIONS

A simple modulation scheme for three-phase to three-

phase direct matrix converters is presented in this paper. The

modulation is based in the translation of a two-level three-

phase voltage source inverter switching states to direct matrix

converter switching states depending on the values of the

input voltage. A very simple implementation of the modulation

using only logical function is also presented. Additionally, an

angle compensation stage is developed to control the input

current displacement and, consequently, the input reactive

power. Simulation results show a good performance of the

proposed modulation in open and closed control loop.

ACKNOWLEDGMENT

The authors acknowledge the support of the Universidad

Tecnica Federico Santa Marıa, the Chilean National Fund

of Scientific and Technological Development FONDECYT

Project 11090253 and the Centro Cientıfico-Tecnologico de

Valparaıso (CCTVal) No FB021 and by an NPRP 4-077-2-028,

a grant from the Qatar National Research Fund (a member of

Qatar Foundation). The statements made herein are solely the

responsibility of the authors.

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