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2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO) The International Conference Centre Birmingham 20-23 August 20112, Birmingham, United Kingdom Si Nanowire Memory Ayman Rizk and Ammar Nayfeh, Member IEEE Abstract - A novel Si nanowire memory cell is demonstrated by Physics Based TCAD simulation. The device utilizes the metal gate work function and the applied gate voltage to create potential barriers that trigger a positive feedback effect. Remarkably low voltage memory operation -1 V is achieved with extremely long retention times ( 19.5s) . The device is based on current high-K metal gate technology and can be fabricated using standard CMOS process integration. Index Terms - Nanowire, Memory, Retention I. TRODUCTION As the dimensions of devices approach the 10nm regime the transition between traditional and nanotechnology has arrived. The marriage between nanotechnology and memory devices is vital for allowing the next generation of memory to keep up with the inevitable computing demand [1-3]. In this work, a novel Si nanowire based memory device is demonstrated by Physics Based TCAD simulation. The effect of nanowire width and high-K material used is studied. The nanowire memory device operates with remarkably low voltage and has an extremely long retention time. II. TCAD STRUCTURE MODEL Figure 1 shows the structure of the nanowire memory simulated using the SynopsysTM TCAD tools [4]. The structure has two separated gates on each side of the Si nanowire, which is surrounded by n+(source) and p+(drain) regions. The nanowire width and high-K material used are kept has variables. However, the initial results use a width of 10 nm and K =30. The nanowire length is fixed at 30 nm with a gate oxide thickness of 2 nm while the separation between the gates is 1 nm. By applying the appropriate gate bias and by engineering the work function of the metal gates, "n' and "p" regions can be created by charge carriers as opposed to doping as shown in figure 1 (b). This creates a thyristor like n-p-n-p device without doping that allows for a positive feedback effect. The positive feedback effect can be utilized as a memory with charges confined in the nanowire aſter programming. Manuscript received July 4, 2012. This work was supported by the Masdar Institute of Science and Technology A. Rizk is with Masdar Institute of Science and Technology, Abu Dhabi,United Arab Emirates A. Nayfeh is with Microsystems Engineering at Masdar Institute of Science and Technology Abu Dhabi,PO BOX 54224 United Arab Emirates; (phone: +97128109105; e-mail: [email protected]). lo Gate 1 Gate 2 + c 9' Gate 3 Gate 4 _TiN _Si _H, V Figure I: (a) Device Structure of Si Nanowire Memory (b) Formation of n and p regions by metal gate work function and voltage applied II. INITIAL STATE OF NANOWIRE In order to study the effect of the metal gate work functions and gate voltage applied on the initial state of the nanowire memory two cases are simulated (Table 1). Table 1: Details of case I and II simulations Case] Case J] work function VCaie work VCale function I Gate 1/3 4.1eV o and 1 V 4.1eV OV I Gate 2/4 4.1eV o and -1.5 V S.leV OV In case I, all four gates have a metal gate work function of 4.1eY. In case II, the metal gate work function of gates 113 is 4.1eY and gates 2/4 is S.leY. Figure 2 plots the band diagram in the center of nanowire from source to drain comparing case I and II. For case I only a barrier between nanowire body and drain is formed. In this case an additional gate voltage is needed to form the n-p-n-p structure. On the other hand, for case II a barrier is created from source to body to drain with no applied voltage only the work function difference. The barrier is created do to excess holes under gate 1 and excess electrons under gate 2. These excess carriers act like doping creating the n-p-n-p structure. This difference between case I (no voltage) and case II shows how the metal gate work function can affect the potential barriers inside the nanowire without doping.

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Page 1: [IEEE 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO) - Birmingham, United Kingdom (2012.08.20-2012.08.23)] 2012 12th IEEE International Conference on Nanotechnology

2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO)

The International Conference Centre Birmingham

20-23 August 20112, Birmingham, United Kingdom

Si Nanowire Memory

Ayman Rizk and Ammar Nayfeh, Member IEEE

Abstract - A novel Si nanowire memory cell is

demonstrated by Physics Based TCAD simulation. The device

utilizes the metal gate work function and the applied gate

voltage to create potential barriers that trigger a positive

feedback effect. Remarkably low voltage memory operation

-1 V is achieved with extremely long retention times (19.5s).

The device is based on current high-K metal gate technology

and can be fabricated using standard CMOS process

integration.

Index Terms - Nanowire, Memory, Retention

I. INTRODUCTION

As the dimensions of devices approach the 10nm regime

the transition between traditional and nanotechnology has

arrived. The marriage between nanotechnology and memory

devices is vital for allowing the next generation of memory

to keep up with the inevitable computing demand [1-3]. In

this work, a novel Si nanowire based memory device is

demonstrated by Physics Based TCAD simulation. The

effect of nan ow ire width and high-K material used is studied.

The nanowire memory device operates with remarkably low

voltage and has an extremely long retention time.

II. TCAD STRUCTURE AND MODEL

Figure 1 shows the structure of the nanowire memory

simulated using the SynopsysTM TCAD tools [4]. The

structure has two separated gates on each side of the Si

nanowire, which is surrounded by n+(source) and p+(drain)

regions. The nanowire width and high-K material used are

kept has variables. However, the initial results use a width

of 10 nm and K =30. The nanowire length is fixed at 30 nm

with a gate oxide thickness of 2 nm while the separation

between the gates is 1 nm.

By applying the appropriate gate bias and by engineering

the work function of the metal gates, "n' and "p" regions can

be created by charge carriers as opposed to doping as shown

in figure 1 (b). This creates a thyristor like n-p-n-p device

without doping that allows for a positive feedback effect.

The positive feedback effect can be utilized as a memory

with charges confined in the nanowire after programming.

Manuscript received July 4, 2012. This work was supported by the Masdar Institute of Science and Technology

A. Rizk is with Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates

A. Nayfeh is with Microsystems Engineering at Masdar Institute of Science and Technology Abu Dhabi, PO BOX 54224 United Arab Emirates; (phone: +97128109105; e-mail: [email protected]).

lorn Gate 1 rJ.., Gate 2

11 c � iil .l! 9'

Gate 3 Gate 4

_TiN _Si _HID,

V

Figure I: (a) Device Structure of Si Nanowire Memory (b) Formation of n and p regions by metal gate work function and voltage applied

II. INITIAL STATE OF NANOWIRE

In order to study the effect of the metal gate work

functions and gate voltage applied on the initial state of the

nanowire memory two cases are simulated (Table 1).

Table 1: Details of case I and II simulations

Case] Case J] work fu nction VCaie work VCale function

I Gate 1/3 4.1eV o and 1 V 4.1eV OV I Gate 2/4 4.1eV o and -1.5 V S.leV OV

In case I, all four gates have a metal gate work function of

4.1eY. In case II, the metal gate work function of gates 113

is 4.1eY and gates 2/4 is S.leY. Figure 2 plots the band

diagram in the center of nanowire from source to drain

comparing case I and II. For case I only a barrier between

nanowire body and drain is formed. In this case an additional

gate voltage is needed to form the n-p-n-p structure. On the

other hand, for case II a barrier is created from source to

body to drain with no applied voltage only the work function

difference. The barrier is created do to excess holes under

gate 1 and excess electrons under gate 2. These excess

carriers act like doping creating the n-p-n-p structure. This

difference between case I (no voltage) and case II shows

how the metal gate work function can affect the potential

barriers inside the nanowire without doping.

Page 2: [IEEE 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO) - Birmingham, United Kingdom (2012.08.20-2012.08.23)] 2012 12th IEEE International Conference on Nanotechnology

Ec (Case II

2.4

2.2

2

1.8

1.6

_1.4

--'Ev(Casell r--··

> .!!. 1.2

� 1 QI c: � 0.8 c: il: 0.6

0.4

0.2

o

-0.2

• • • Ec (Case III

-Ev(Caselil

/ .

/'-. . " .

" . """._. I . "

.. - .................. _ ... _-

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" " "

" I "

I �, __

.,'

/ , /

V G(I/2/3/41= 0 V

-10 -5 o 5 10 15 20 25 30 35 40 45 X(nm)

Figure 2: Effect of the metal gate work function on the band energy across the device for both case I (no applied voltage) and case II

In addition to the metal gate work function, the voltage applied to the gate can also control the barriers or amount of charge carriers in the undoped body of nanowire. Figure 3 shows the effect of gate voltage on the potential barriers for case I where the metal gate work function is 4.1eV for all four gates. By applying 1 V on gates 113 and -1.5 V on gates 2/4 a barrier is now created between the nanowire body and source/drain regions. The barriers are the result of excess electrons/holes in the channel thus creating the desired n-p­n-p structure.

Figure 4 plots the electron and hole concentrations through the center of the nanowire between the source and the drain comparing case I and II. The plot highlights the effect of metal gate work function on the excess carrier concentration in the nanowire. For case II electrons and holes fill the nanowire body creating the n-p-n-p structure. For case I with no bias, on the other hand, only electrons fill the nanowire body. Additional gate bias is needed to create the desired n-p-n-p body as discussed earlier.

3.4 .r,::==:==:=====::::::;--------------, 3.2 Ec (VG =0) -Ev(VG=O) --- Ec (VG1=VG3=1 VG2=VG4=-1.5) --- Ev(VG1=VG3=1 VG2=VG4=-1.5)

3 2.8 2.6 2.4 2.2 " ," ,._

-

....... ' .. , 2 , .\, /' � 1.8 " " ",I -;: 1.6 ,l '\ � 1.4 I '\ .n 1.2 � __ .-::,'�-:-;",.......--....::;::--�:--- / .-.._---1 � 1 " ............ '.......... "" ,/'

: �:: /" '\'"''

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X(nm)

20 25 30 35 40 45

Figure 3: Effect of the metal gate applied voltage on the band energy across the device for case I

10+-20

10t-18

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10+14

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, ,

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Figure 4: Effect of the metal gate work function on the electron and hole concentrations across the device; case I (no applied voltage) and case IJ

Figure 5 shows the effect of metal gate voltage on the electrons and hole concentrations for case I with and without gate bias. By applying the IV on gates 113 and -1.5V on gates 2/4 electrons and holes fill the nanowire body creating the n-p-n-p structure for case I.

f � C 0 '" � � � C 8

10+21 10+19 10+17 10+15 lO"'u

10+11 10+9 10+7 10+5 10+3 10+1 10-1

10-' 10-5 10-7 10-'

, \�--------, , , , , , , ... -.. , "

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----------

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-electron (VG =0)

-Hole (VG =0)

" , . , . , " , " , ,

--- Electron (VGl=VG3=1 VG2=VG4=-1.5)

--- Hole VGl=VG3=1 VG2=VG4:-1.5

, , , .-, , , , , , , , , , , , , " " I \.------

--

, . , , , .-

\.. ...,' .. ,----- ,

-15 -10 -5 0 10 15 20 25 30 35 40 45 X(nm)

Figure 5: Effect of the metal gate voltage applied on the electron and hole concentrations across the device for case I

III. HYSTERESIS MEMORY EFFECT

a. Hysteresis

In order to plot the Idrain-V drain curve to see a hysteresis memory effect, the undoped nanowire body must be created into n-p-n-p by applying the appropriate bias and engineering the metal gate work functions. This can be done for case I by applying VgJ=Vg3=l V and Vgz=Vg4=-1.5 V. For case II the work function difference alone can provide the n-p-n-p structure from figure 2. However in order to increase the barriers further, VgJ=Vg3=lV and Vgz=Vg4=-lV is applied. Once the n-p-n-p is set, the drain voltage is swept from OV to 2V and back to OV. Figure 6 plots the Idrain-V drain curve obtained for both case I and II. The plot shows a large hysteresis loop with low turn-on voltage. The transition from low to high current flow is extremely sharp indicative of a feedback-based device. The turn on voltage is around 1.l V for case II and 1.3V or case I. The hysteresis loop is larger for the case II due to the larger initial barriers obtained. The hysteresis loop indicates that a charge is stored inside

Page 3: [IEEE 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO) - Birmingham, United Kingdom (2012.08.20-2012.08.23)] 2012 12th IEEE International Conference on Nanotechnology

the nanowire during the drain voltage sweep. This confirms the memory operation of the device.

10-3

1O�

10-' 10-'

� 10-7

1: 10�

� 10-' " U 10-10 "

of! Q 10-11

10-12

10-13 10-14

10-15 10-16

0 0.2 0.4 0.6 0.8 1.2 1.4 Drain Voltage (VI

Figure 6: Id"in-V d"in showing large hysteresis and low turn on voltage.

To explain how the device operates, the electrostatic potential at eight points of the hysteresis loop is studied. The numbers in figure 6 represent the points taken while figure 7 plots the electrostatic potential along the center of the nanowire from source to drain at each one of the eight points. The eight points plotted are when V draln=O, 0.5, 1, 1.5, 0.5 and 0 V during the sweep.

At point 1, there is large barrier between the source and drain so the current through the nanowire is small. At point 2, as the drain voltage increases the barrier between p+ drain and undoped nanowire body decreases allowing holes to diffuse to the area under the gate 2. The holes will subsequently attract electrons from the area under gate 1 reducing the barrier on the source side. This is the basis of the positive feedback effect. At point 3 and 4, as more holes diffuse into the undoped nanowire body and as more electrons are attracted, the barriers are reduced on both sides and a larger current starts to flow. Between 4 and 5, the barrier is no completely reduced allowing a large current to flow and the device turns on. At points 6 and 7, as the drain voltage drops the barriers begin form again but the due to the excess carriers in the body from the large current that is flowing, the turn off is slow. This is the basis for the hysteresis effect of figure 6. Finally, at point 8, the excess carriers are completely out of the nanowire body and the nanowire is back to the initial state of point 1 with little current flow and large barriers.

1.3 r---===-===:--------------, 1.2 -1.1

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-0.4 -0.5 -0.6

2.7

1.8

:�:� I--��---�-�-�-����-----l w e W H W H � U

X(nm)

Figure 7: The electrostatic potential along the device during the hysteresis voltage sweep; numbers on curve correlate to the numbers on figure 6

b. Nanowire Width and High-I(

The effect to nanowire width is studied by simulating Id - -Vd . curve for widths of 10, 12, 15, 25, and 30nm. The Id,aln_Vd

rain curve for all widths is shown in figure 8. The rain rmn ......

smaller the width the larger the hysteresis window achieved. The best result obtained is for a length of 30 nm is a width of lOnm. This suggests that a W/L ratio <113 is needed achieve the largest hysteresis window. For large widths, the barrier between source/nanowire/drain is not large enough to achieve the desired hysteresis.

10-' r------------------:=====,

10-3 10�

10-s 10� Reducing Nanowire Width 5: 10.1

1:: 10-8 �

� 10-9 u .: 10-10

� 10-n 10-12 10-13 10-14 1==----:-:::7

W=12nm

10-15 �=�::::::::::=�==�----� 10-16 c:

o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Drain Voltage (V)

Figure 8: I"',in-V ""in showing for nanowire widths: 10, 12, 15,25 and 30nm

The effect to high-K material is studied by simulating Id,aln-Vdrain curve for K vales of 3.9, 12, 16, 20, 24 and 30 in figure 9. As K increases the hysteresis window increases due to the larger capacitive coupling between metal gates and nanowire body. This provides a larger initial barrier between the source-nanowire-drain. In addition, the gate has more capacity to store electrons and holes and the memory effect hysteresis window increases.

Page 4: [IEEE 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO) - Birmingham, United Kingdom (2012.08.20-2012.08.23)] 2012 12th IEEE International Conference on Nanotechnology

1�2�----------------------------------------,

10.3 •

10"

10-5 10"

_ 10-7 -.. ':" 10-8 C

� 10-9

� 10-10

� 10-n

10-n

10-13

10"14

K = 30

=24 Increasing the oxide K

10-15 �����§:;:==�===::::=--------.,.....---------l 10-16 e

o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Drain Voltage (V)

Figure 9: Id"i,-V d"i, showing for high-K dielectric constants 3.9, 12, 16,20, 24 and 30

IV. TRANSIENT RESPONSE

The transient response of the memory cell is studied using the voltage pulse in figure 10. The applied voltage vs. time on the drain and gates are used for writing and reading a one and zero. To write a 1 the drain voltage is ramped up to IV with gates 2/4 ramped down from IV to OV in and gates 113 from -1.5V to 1.5V. All ramps are 2ns consistent with DDR3 specifications. To write a 0, the drain voltage is kept at 0 with gates 2/4 ramped down from IV to OV and gates 113 from -1.5V to 1.5V. Figure 11 shows the corresponding the drain current vs. time. The pulse shows a working memory operation with 1/0 ratio of 105. As result, the one and zero states are easily distinguishable.

1.5

0.5 ?:

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WO

Rl I I RO

r----i.��----��----�I Ir-----���-

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·1 I I. ____ I

-- I I'

\ I I _ _ _ _ _ _ , ______ ,

o 5 ill 15 20 25 30 35 � 45 50 � Time (ns)

I 1 ______ ,

Figure 10: The applied voltage pluses on the drain and the gates for writing "One", reading "One", Writing "Zero" and Reading "Zero"

lO·2 lO·3 lO-4 lO·' lO" 10.7

"< lO'· i 10-9 � 10-10 a 10-11 .� 10-12 C 10-13

lO·14 10-15 10-16 lO·17 10-18 10-19

r � r

I�

L--- \� '--

o 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Time (ns)

Figure 11: Drain current vs. time during voltage pulse of figure 10

In addition to the transient response, the retention of the nanowire memory is studied. After a zero is written in the around 75ns into the pulse (figure 10), the pulse is stopped and the hold condition set. The gates are now set to their initial condition values that produced the n-p-n-p stucture. After that, the electron density under gate 2 in the center of the device is monitored as a function of time. There are two mechanisms that are responsible for the nanowire to change from a zero state back to the initial state. First is electron hole pair generation in the Si nanowire away from the interface (bulk). Second is electron hole pair generation due to interface defects (Djt) at the high-KlSi nanowire interface (Figure 12). A trap state can enhance electron hole pair generation by either emission or Trap Assisted Tunnelling to the conduction band. The traps are amphoteric in nature and thus the barrier for emission to the conduction band from trap states can be reduced by electric field via the Poole­Frenkel Effect. The barrier reduction is proportional to the square root of electrical field [5]. These models are included in the simulation. The Djt is modelled as Gaussian distribution across the bandgap. The peak Djt is taken at the

. I d (2 1010 -? 2 lOll -2 mid-gap with three values srmu ate x cm -, x cm , and 2x1012 cm-2)

Figure 13 plots the electrons density vs. time after writing a zero for the different Dlt values. The larger the Djt (worse quality interface) results in the smaller retention time due to an increase in the electron hole pair generation rate. For Djt of 2xlOIO/cm2 a retention time of 19.5 seconds is achieved.

. n

xxxx xxxx xxxx xxxxx

Interface Defects � xxxx xxxx xxxx xxxxx

Gate 3 Gate 4

p •

Figure 12: Interface defects (Dil) at the high-K lSi nanowire interfaces

Page 5: [IEEE 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO) - Birmingham, United Kingdom (2012.08.20-2012.08.23)] 2012 12th IEEE International Conference on Nanotechnology

1013 •

.-------------------------

.. 19.5 Sec.

I Initial St,

1010

Zero State 1�+--------------�----�----

10.7 10.5 10.5 10·' 10' Time (Sec)

Figure 13: Electron density vs. time after writing a zero for different Dil values

SUMMARY

In summary a novel Si nanowire memory device is demonstrated by TCAD simulation. The devices uses metal gate work function and voltage to modify the potential in the device and create a positive feedback effect. The device operates at an extremely low voltage (�l V) with a long retention time (�19.5s). Finally, this device is an attractive solution for future nanowire based memories.

ACKNOWLEDGMENT

We gratefully acknowledge financial support for this work provided by the Masdar Institute of Science and Technology.

REFERENCES

[I] T. Tsutsumi et ai, "Single electron memory characteristic of silicon nanodot nanowire transistor," IEEE Electronics Letters, voL 36, pp. 1322-1323, July 2000.

[2] H. Cha et ai, "Gallium nitride nanowire nonvolatile memory device," Nanoscale science and design, Journal of Applied Physics, voL 100, March 2006.

[3] S. Lee, Y. Jung and R. Agarwal, "Highly scalable non-volatile and ultra-low-power phase-change nanowire memory," Nature Nanotechnology 2, pp. 626-630, September 2007.

[4] Synopsys TCAD, http://www.Synopsys.ComlTcad [5] Ammar Nayfeh et ai, "A leakage current model for SOl based floating

body memory that includes the Poole-Frenkel effect" IEEE SOl Conference, 2008 Date: 6-9 Oct. 2008 pp 75-76

978·1·4673·2200·3/121$31.00 ©2012 IEEE