2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO) The International Conference Centre Birmingham 20-23 August 20112, Birmingham, United Kingdom

Low Power Nanoscale RF/Analog MOSFETs

Dipankar Ghoshi, Mukta Singh Parihari, G. Alastair Armstroni, and Abhinav Krantii lLow Power Nanoelectronics Research Group, Electrical Engineering, Indian Institute of Technology Indore, 452 017, India

2School of Electronics, Electrical Engineering and Computer Science, Queen's University Belfast, Belfast BT9 5AH, UK Email: akranti@iiti.ac.in

Abstract - The present work reports on the substantial

benefits of underlap SourcelDrain (SID) design in moderately

inverted nanoscale MOSFETs to significantly enhance key

analog/RF performance metrics. It is demonstrated that

underlap SID design alleviates the inherent trade-ofrs between

bandwidth, gain and linearity for low power RF CMOS

nanodevices. Optimal underlap region parameters are

identified and design trade-ofrs examined. The results are

significant for RFICs with nanoscale MOSFETs in emerging

technologies.

Index Terms - Low power, Ana/og/RF, Linearity, Double

Gate MOSFET.

I. INTRODUCTION

The evolution in CMOS technology, determined by Moore's Law, is motivated by decreasing price-per­performance for digital circuitry [1]. To ensure sufficient lifetime and to keep power consumption at an acceptable level, the dimension-shrink is accompanied by lowering of supply voltages. While this evolution in CMOS technology is very beneficial for digital, this is not so for analog circuits [1-2]. As a result, analog/RF devices have lagged behind their digital counterparts by at least two technology generations due to short channel effects and parasitics [1].

In the previous technology nodes (65 nm, 90 nm and 130 nm), asymmetric low-power MOSFETs have been proposed to alleviate the degradation of analog/RF metrics [2]. However, in the nanoscale regime it will be difficult to implement asymmetric channel topology in advanced devices due process complexity and variability. The crucial questions for low power moderately inverted analog/RF MOSFETs are:

(1) Is it possible to scale down MOSFETs without degrading analog/RF performance metrics? (2) What is optimum drive current for low power analog/RF devices? (3) Can improved linearity be maintained at low drive currents in nanoscale devices?

A feasible technological option for improving the analog/RF metrics is the use of under lap Source lDrain (SID) architecture [3]. In this work, we demonstrate the usefulness of underlap SID design to enhance analog/RF metrics without degrading linearity in moderately inverted (low power) MOSFETs.

IT. SIMULATION

Undoped Double Gate (DG) MOSFET (fig. la), a promising structure for scaling at the end of TTRS roadmap [1], with gate length (L,) of 20 nm was simulated using ATLAS simulator with Lombardi mobility model [4]. Underlap SID doping profile (along the channel) was defined by NsD(x) = No exp(-x2/cl), where No is the peak SID doping, CJ (= -V2sd/ln(10) ) is the lateral straggle parameter governing SID roll-off [3], s is the spacer width (15 and 21 nm) and d is the SID doping gradient (= 3 nm/dec) at the gate edge [3]. In underlap profile, SID doping at gate edge is lower than the peak SID doping. As shown in fig. 1 b, spacer width is defined as the distance from the gate edge to the starting of roll-off of SID profile.

I?pace� Gate .Space�1

Tox '-----i"'- ---'

n-type Tsi p-type n-type

(a)

1022r------:-------;-------, 14 GAT E �I ----

'? E (.) '-"'

1018 ---->< '-"'

0 1016 (/)

Z Na

1014+-.....,.-........ -.,...---.-....,...-....... .....,----1 o 8 16 24 32 40 48 56

(b) x (nm) Fig, I Schematic diagram of (a) Double Gate (DG) MOSFET and (b) Underlap sourceldrain (SID) doping profile. Notations: Gate length (Lg), Oxide thickness (T",), Silicon film thickness (T'i), Spacer width (s).

TIT. RESULTS

Fig. 2 shows a comparison of our simulation results (traditional abrupt SID design) with the experimental data [5] for 20 nm DG MOSFETs. The default models were calibrated against the available data for 20 nm DG SOT MOSFETs. Figure 3a-b shows the variation of the product of transconductance-to--current ratio (gmIJds) and cut-off frequency (fT) with drain current (Jds) for underlap and

abrupt SID devices. To capture both performance and DC power consumption of a MOS transistor in any region of operation and during optimization process, Murmann et al., [6] and Shameli et al. [7] independently proposed a new figure of merit, the product of (grr!ids) and (If) to optimize the ultra-low power RF circuits. Maximizing gm!rlids for a fixed bias current leads to the maximum achievable gain bandwidth product (GBW) [7]. The "sweet spot" observed in the gmiTlids characteristics correspond to the optimum balance between bandwidth and gain for moderately inverted MOSFETs [6-7]. As gmiTl ids represents a basic challenge of achieving a good balance between bandwidth and power efficiency, higher values of gm!rl ids (around the sweet spot) indicate improved.iT at the same grr!ids (or dc gain) or even improvement in both parameters.

104r-----------------------�

102

>-::!�--� Vds = 1.2 V

7-'"""---.... Vds = 0.05 V

-Simulated = = Experimental [5]

10.8+-----...,.....----...,....----...,....----"'"' -0.4 0.0 0.4 0.8

Vgs (V) 1.2

Fig. 2 Drain current (Id,) - gate voltage (V.,) characteristics of Double Gate (DG) MOSFET at low and high drain bias (Vd,). Parameters: Lg = 20 nm, Tox = 1.7 nm, T,i = 10 run, gate workfunction ( c:t\n) = 4.67 e V

Underlap SID channel design results in an impressive improvement (x2.8 for Tsi = 10 nm and x2.4 for 7 nm) in gmiTlids when compared with abrupt SID device. The improvement in gmiTl ids in underlap SID design is due to enhanced gate controllability and reduced parasItic capacitance [3]. Comparing fig. 3a with fig. 3b for abrupt SID junctions, a reduction in Ts/ Lg from 0.5 to 0.35 lowers ids values from 30 flA/flm to 12 flA/flm to achieve gmiTlids =

2000 GHz iV. The underlap SID design with Ts/Lg = 0.35 results in a further reduction in ids to 2 flA/flm for the same gmiTlids value. Underlap SID architecture with s = 21 nm (Ts/Lg = 0.35) achieves impressive hand gmlids values of 170 GHz and 30 V·l, respectively, at lds = 10 flA/flm. These values are substantially higher thaniT = 70 GHz and grr!ids = 24 V·l achieved by abrupt SID design at the same ids. Underlap SID design at low ids (� 10 flA/flm) achieves approximately 3 times higher gmiTlids values. When porting an analog function with a fixed bandwidth requirement to next technology generation, MOSFETs should be biased at lower ids to achieve the desiredfT,

As shown in Table 1, underlap SID devices (for both s

values) achieveh = 50 GHz at drive currents lower than the LTRS target [1]. The reduction in ids is impressive for wider spacers. Intrinsic gain (grr!gds) is another crucial parameter limiting the scaling of analog devices as it degrades with gate length reduction. Underlap SID achieve higher grr!gds

values at lower ids values (corresponding to fr = 50 GHz), without having to use longer gate lengths as suggested by LTRS. 20 nm underlap devices, designed with s = 21 nm, achieve nearly the same gmlgds as a 55 nm abrupt SID DG MOSFET.

,--... 10 ..,-----------_ "'0 8

� 6 I 4 (9 -- 2

Ts;=10nm

Underlap SID (s = 15 nm)

Underlap SID (s = 21 nm)

1000

(a) "';; 1 0 -'--

T-s

-;

-= -Y - n- m-------cUc-n--: d-er-c-la-p- S=-I=D­

>< --8

6 � 4

I (9 2 -­

en

(s = 21 nm)

� 0 'j=------,------,---_ ..t'

E 0)

1000

(b) Fig. 3 Dependence ofgn,jillJ, on lJ, for Double Gate (DG) SOl MOSFET for (a) T,i = 10 nm and (b) T,i = 7 nm. Parameters L, = 20 run, Tox = l.l run, Vd, = 0.95 V and <Pm = 4.67 eV

Device s Lg Tsi ids (fllVllm) @ grr!gds (run) (run) (run) fr = 50 GHz (dB)@

fr = 50 GHz

Abrupt - 20 7 7.2 26.41 20 10 8.4 20.51

Underlap 15 20 10 4.1 30.11 21 20 2.5 34.10

Abrupt - 55 10 9 35.45 (Vds = Vdd/2, VaQ = 0.2 V)

LTRS - 20 - 5 29.50 target (Vds = Vdd/2,

VaQ = 0.2 V) Table I Companson of current level (Id,) to achieve!] = 50 GHz and mtrmslC voltage gain (&,/gd,) values achieved by abrupt SID and underlap SID devices. Parameters: Lg = 20 nm, Tox = 1.1 run, Vd, = 0.95 V and and <Pm = 4.67 eV ITRS target for gn/gd, is extracted at a gate overdrive (V" - Vlh) of 200 mY, Vcb = Vdd/2 and gate length to be 5 x minimum digital gate length (L, =

5 L.nin.digitaJ).

The scaling of CMOS has resulted in a strong improvement in the RF performance of MOS devices [1]. Consequently, CMOS has become a viable option for analog RF applications and RF system-on-chip. Performance

metrics such as transconductance, cut-off frequency and maximum oscillation frequency have been studied widely [8-10]. However, trends in linearity, for nanoscale devices, are not well known. While biasing the device at peak­gm/'Tlids greatly helps in lowering power for applications that do not demand an extremely high bandwidth, it may come with a penalty in terms of linearity. The metric for linearity, ViP3, is defined as ViP, = �24(gmj / gm3 ) where gml =

8idJ8 Vgs and gm3 =83idJ8 V3 g; represents the extrapolated gate voltage amplitude at which the third-order harmonic becomes equal to the fundamental tone.

�

> '-"'

C') 0.... >

10.0 -,------------_

1.0

0.1 5

Underlap SID (s = 21 nm)

Underlap SID (s = 15 nm)

10 15 20

(a) -1 gm/lds (V )

10.0 Underlap SID (s = 21 nm)

1.0

Tsi = 7 nm 0.1

5 10 15 20

(b) 1 gn/lds (V )

25 30

25 30

Fig. 4 Dependence of VIP3 ongnJ1d, for Double Gate (DG) SOl MOSFET (a) T,i = 10 nm and (b) T,i = 7 nm. Parameters: Lg = 20 nm, To, = 1.1 nm, Vd, =

0.95 V and CPm = 4.67 eY.

As shown in Fig. 4, ViP3 degrades significantly with increase in gd ids (decreasing ids). It will be difficult to operate abrupt SID MOSFETs in the moderate inversion region as low values of ViP3 are obtained. The highest linearity is observed at ids = 51 flA/flm (gdids = 13 V·l) for Tsi = 10 nm in abrupt SID devices (fig. 4a). This drain current value in abrupt SID MOSFETs can be lowered to 46 flA/flm (gmlids = 16 V·l) by reducing the film thickness to 7 nm (fig. 4b). However using underlap SID design s = 21 nm, the highest linearity is observed at ids � 20 flA/flm (gmlids � 23 to 26 V·l) for both film thickness. These current values correspond to peak-gm/'Tlids values described in figure 3 a-b.

Figure 5 shows the dependence of peak-gm/'Tlids on spacer-to-straggle ratio (slo). The optimum value of

underlap region parameters in terms of maximizing grr/TI ids is approximately 3. The corresponding grr/Tlids value for abrupt SID devices is also plotted as horizontal line on the y-axis for comparison. Nearly 3 times higher values for grr/TI ids are observed when compared with abrupt SID devices. The optimum SID profile can be achieved in many different ways: (i) optimizing s for a fixed d, (ii) optimizing d for a given s, and (iii) optimizing both sand d. In order to evaluate and optimize the values of s and d for optimal underlap devices, the dependence of spacer-to-straggle ratio (slo) on spacer-to-gradient ratio (sid) is shown in figure 6a-c. The highest value of sla corresponds to underlap design with minimum value of doping gradient (d = 1 nm/dec) and the lowest value of slafor each spacer with corresponds to d = 7 nm/dec. The two different spacer widths analyzed in this work i.e. 15 nm and 21 nm translate into sid of 5 and 7 and sl (J of 2.4 and 2.8, respectively, for d = 3 nm/dec. The relationship between sl(J and spacer to gradient (sid) ratio is s/a = �ln(10)/2�s/d

� 7 �--------------------------�

>< 6 '-"'

� 5 < Tsi=10nm N 4 Lg = 20 nm I

� 3 Tox = 1.1 nm '-"'

(/) '0 ::::: ..t- 2

E 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 0> s/cr

Fig. 5 Dependence of g,,jrI1d, on spacer-to-straggle ratio (sla) for underlap SID devices. The horizontal line on the y-axis corresponding to 2.14 represents the value for abrupt SID devices.

As shown in fig. 5, the optimum value for the design of underlap region in terms of sl (J is � 3. This optimal sl (J value of 3 can be achieved for various possible combinations of spacer widths and doping gradients. Considering the range of sand d values, SID design using d = 1 - 2 nm/dec should be avoided as it corresponds to very steep doping gradients which may not be feasible to achieve. Although LTRS [1] has projected the doping gradient (d) to be scaled in proportion to gate length (LJ by a factor of 0.1, it will be increasing difficult to do so due to process constraints and it would require development of costly annealing techniques. Hence, it will be better to fix d (generally decided by thermal budget) and optimize the spacer width. Also, SID design with gradual doping gradients (d = 5 to 7 nm l dec) at shorter spacers will result in overlap architecture (SID doping extends underneath the gate) instead of the desirable gate underlap design. Increasing the spacer width to 15 nm (fig. 6b), it is indeed possible to achieve the target sl(J of 3 but with a steep doping gradient of 2 nm/dec. All other d values (> 2 nm/dec) will either result in an underlap (3 to 5 nm/dec) or overlap (d > 5 nm/dec) SID design. The

underlap with d = 3 - 4 nm/dec at s = 15 nm may give

better performance as compared to abrupt SID but it will

still be below the optimal. Devices designed with d = 5 - 7 nm/dec with s = 15 nm will result in a gate overlap design

as s/ (J" is expected to be below 2. As a steep doping profile (d = 2 nm/dec) is difficult to achieve, the spacer width must be

increased in order to achieve the optimal s/ (J".

6 5 4

J2 3 en

2 1 o

..... S = 5 nm , . . , . . ·-------r-----------,------------�-----------, . .

, , , , , -----------,------------,------------r-----------�------------r-----------, , , , , . . . . ....... d = 1 nm/dec

-r-----------!------------!-----------

0 5 10 15 20 25 30

sid (a) 6 5 4

b 3 -en

2 1 0

(b)

.... ·s= 15 nm , , , -----�----------.�----------.-:---------.-

........ : ........ � ..... ; " d = 1 nm/dec

�' " , ,

-- -- -- ----- - -- -- -- -- - - -- - -

.. .. .: .. ;zr... : ........ � ....... � ........ � ........

o

, , , , , , , , , , , , , , , , , , , , d = 7 nm/dec

5 10

, , ,

15 20 25 30

sid 6 ,---�--�--�--�--�---,

5 4

J2 3 en

2 1

.... S = 25 nm

d = 7 nm/dec , , , , , , -,------------�-----------,------------, , ,

o +---.---�--�--�---+--�

o 5

(c)

10 15 20 25

sid 30

Fig. 6 Dependence of spacer-to-straggle ratio (s/u) on spacer-to-gradient ratio (s/d) for (a) s = 5 nm, (b) s = 15 nm, and (c) s = 25 nm.

Figure 6c shows the possible combinations in terms of s

and d to achieve the optimal s/ (J" of 3. A doping gradient of

3 nm/dec along with spacer width of 25 nm results in the

optimum combination for the desired s/(J" value. Any spacer

width lying between 20 and 25 nm at d = 3 nm/dec should

yield a significant improvement over abrupt SID design.

Larger values of s/ (J" (> 3.5) tend degrade analog/RF metrics

because of additional series resistance associated with very

wide spacers.

IV. CONCLUSION

The advantages of underlap SID design in significantly

enhancing analog/RF metrics at nanoscale regime in

moderately inverted MOSFETs have been demonstrated.

SID profile engineering offers a way forward for scaling

down of low power analog/RF devices. Underlap devices

should be designed with s/ (J" � 3 or s/ d � 8 for achieving

enhanced performance metrics. Biasing the low power

device within 10% of peak-gn/T/ Ids not only provides

substantial gain in terms of gm/ Ids and /T, but also improves

linearity. Results presented in this paper will prove useful

for ultra low power RFTCs with moderately inverted

MOSFETs.

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