20th Iranian Conference on Electrical Engineering, (ICEE2012), May 15-17, Tehran, Iran

A New Single-Phase Cascade Multilevel Inverter Topology Using Four-Level Cells

Mohammad Nilkar

Technical and vocational university Tabriz, Iran

m.nilkar@yahoo.com, m-nilkar@iau-ahar.ac.ir

Abstract-This paper proposes a new multilevel inverter with a

fewer number of power electronic switching devices and gate

drive circuits. In comparison with other classical topologies such

as cascade H-bridge and neutral-point-clamped multilevel

inverters, the proposed topology can generate more numbers of

voltage levels at the output. The proposed inverter consists of

cascade connected four-level basic cell inverters and a

conventional H-bridge. Less number of the switches leads to the

reduction of size and weight, simple gate drive and control

strategy, high efficiency, low power consumption and also

increases the total reliability of the inverter. The simulation

results obtained from PSCAD/EMTDC software confirm the

validation of the proposed configuration advantages and its

theoretical operation and control method.

Keywords-component; Cascade H-bridge nmltilevel inverter,

styling;multilevel inverter

I. INTRODUCTION

The term multilevel inverter has been introduced in 1975 [I]. The basic concept of a multilevel inverter is using a series of power semiconductor switches that connected in special arrangement with several lower dc voltage sources to synthesize a near sinusoidal staircase output voltage wavefonn. The main advantages of the multilevel inverter are having small output voltage step, lower hannonic components, better electromagnetic compatibility, low switches stress, and lower switching losses [2]. Multilevel inverters are the most proper technology for medium to high voltage and high power application. In general, the classical multilevel inverters are divided into three main structures: diode-clamped multilevel inverter (DCMLI) or neutral-point-clamped (NPC), tlying­capacitor multilevel inverter (FCMLI), and cascade H-bridge (CHB) [3-5]. The first topology introduced was the cascade H­bridge. Since this structure consists of series H-bridge power conversion cells, the voltage and power levels can be scaled properly. The CHB topology was followed by the diode­clamped inverter that utilized a bank of series capacitors. The FCMLI involves series of capacitor-clamped switching cells [6]. This topology has several attractive features when compared with the diode-clamped inverter. One unique feature is that additional clamping diodes are not needed. In recent years, many new topologies have been presented to multilevel inverter with a low number of power switches and gate drive system. The presented topologies in [7-9] are composed of

978-1-4673-1148-9112/$31.00 ©2012 IEEE 348

Ebrahim Babaei, Member, IEEE, Mehran Sabahi

Faculty of Electrical and Computer Engineering, University of Tabriz

Tabriz, Iran e-babaei@tabrizu.ac.ir, sabahi@tabrizu.ac.ir

modular sub-multilevel inverters that make it easily extensible to higher number of output voltage levels without increase the power circuit complexity and reduce controller design cost. In terms of the voltage sources, there are two types of inverters: symmetric and asymmetric multilevel inverters. The magnitudes of the all voltage sources are equal in symmetric type. In the asymmetric topologies, the values of dc voltage sources are unequal or are in predefined factors on binary or trinary [9]. Asymmetric and hybrid multilevel inverters have been presented in [10] and [1 I]. These inverters reduce the size and cost of the conversion systems. Using appropriate selection of the dc voltage source magnitudes the number of output voltage level is increased and the number of switches decreases in a given output level in compared with classical symmetric inverters.

Unfortunately, multilevel inverters have some disadvantages. One clear disadvantage is need to high number of power semiconductor switching devices. Although the switches with low rating can be utilized in a multilevel inverter, each switch requires a related gate drive circuits. This makes the overall system more expensive and complex [8]. So, in practical applications, reducing the number of switches and input dc voltage sources are very key solution.

In this paper, a new multilevel inverter with the ability of the production of all levels at the output is proposed. This inverter consists of several basic three-level cells with bypass capability and an H-bridge for producing positive and negative levels at the output voltage. The number of power semiconductor switches for the proposed inverter is reduced. The harmonic components of the output voltage waveform are also reduced. Capacitors, batteries, and other dc voltage sources can be used as the voltage sources of the proposed inverter. Therefore, the proposed multilevel inverter can be applied to grid-connected photo voltaic systems, fuel-cell energy conversion systems, active power filters and etc., while maintaining these advantages.

In section 2, the topology of the proposed inverter is presented. In section 3, the proposed topology and CHB multilevel inverter are compared from the point of switches number and producible voltage levels. In section 4, the case study for a typical 21-level two-cell and producible voltage is presented. In section 5, the simulation result is shown for two-

cell 21-level proposed inverter to validate the effectiveness of the proposed configuration.

[I. PROPOSED TOPOLOGY

The first proposed topology of the multilevel inverter is a basic cell which can be generating four different voltage levels at the output. The basic cell of the proposed inverter is shown in Fig. l. This topology consists of two dc voltage sources with four switches. When the switch Sc becomes ON and the other

switches become OFF, the VI is connected to the output in

parallel. Then, when the switch Sa becomes ON and the other

switches become OFF, the current flows in the switch Sa'

which connect the voltage source � and V2 series via the

switch Sa. When the switch Sb becomes ON and the other

switches become OFF, the V2 is connected to the output. When

all switches become OFF and the switch Sz is ON, the zero

voltage level can be produced at the output. Therefore, the four different voltage levels can be obtained at output by appropriate connection of the switches. The typical output

waveform of Vo is shown in Fig. 2. Table I shows the value of

va according to the switches conduction states.

o

s�

Figure I. The basic cell of the proposed inverter.

Va 1 V;+V2 -A--------- 1\

V2 ------Vi· o � t

Figure 2. Typical voltage waveform of Vo .

TABLE!. VALUE OF VO FOR DIFFERENT STATES OF SWITCHING

Switching states State

Sa Sh Sc Sz va

1 0 0 0 1 0

2 0 0 1 0 VI

3 0 I 0 0 V2

4 I 0 0 0 VI +V2

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Fig. 3 shows the general circuit topology of the proposed

inverter. This topology consists of n basic cells and 2n dc

voltage sources called Vj - V2n . These voltage sources are independent from each other. Each cell from the proposed inverter generates four different voltage levels. Switches

Sal - San' Shl - Shn and Sci - Sen are the switches which

connect the dc voltage sources in series or direct to the output

and Szl - Szn are the bypass switch of the cells.

S;J

Figure 3. Proposed topology in general.

The desirable aim in a multilevel inverter is to obtain the maximum number of steps with minimum number of switches. The basic cells in cascade arrangement can increase the

possible values for vo . [n the following, we will propose three

procedures for determination of dc voltage sources magnitudes which are utilized in the proposed multilevel inverter and evaluate the performance of each other. [n Fig. 3, [f the magnitude of all dc sources are equal to Vdc' the maximum

output voltage is given by:

(1)

The number of maximum output voltage steps of the n series cell can be expressed by:

N,tep = 2n+ I for (2)

In the proposed inverter can also increase the number of output voltage levels by changing the ratio of the magnitudes of dc voltage sources similarly cascade H-bridge multilevel inverter. Tn other case, the dc voltage sources in the proposed inverter are suggested to be chosen in unary incremental scheme according to the following equations:

(3)

for j = 2,3, ... ,2n (4)

The maximum output voltage and the number of voltage steps are calculated by (5) and (6), respectively:

v'"max = n(2n + l)Vdc

N,tep = n(2n + 1) + 1

(5)

(6)

Now, the dc voltage sources magnitude chosen according to a geometric progression with a factor of two or binary. Tn this case, the supplying voltages are VI = Ip.u. , V2 = 2p.u. ,

V:J = 4p.u. , and V4 = 8p.u.

In binary fashion, the number of output voltage steps increase considerably and can be determined by the following equation:

N,'lep =4n (7)

This is with typical two-cell arrangement equal to

N,tep = 42 = 16 as will be shown in Table IV.

The maximum output voltage is as follows:

(8)

The proposed structure is only able to produce a positive output voltage. To generate both positive and negative output voltages, an H-bridge is added to the output terminals. This topology is shown in Fig. 4. It is clear that the both switches Sl and S2 or (S3 and S4 ) can not be ON simultaneously

because a short circuit across the voltage Vo would be

occurred.

s z.!J

Sz�

Figure 4, Proposed topology with H-bridge,

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The number of output voltage steps considering H-bridge can be obtained from the following equations:

With equal magnitude of the dc sources, the number of output voltage steps can be obtained as follows:

Ns1ep =2(2n+l)-1=4n+l (9)

In unary case considering H-bridge the number of steps can be obtained from following equation:

N>le" = 2[ n(2n + 1) + 1]-\ (lO)

In binary case with H-bridge implementation, the maximum number of output voltage steps can be expressed by:

N,1ep = 2( 4n - I ) + 1 (11)

The number of IGBTs ( NIGBT) considering H-bridge

circuit is given by the following equation:

N IGBT = 4n + 4

III. PROPOSED TOPOLOGY COMPARISON WITH CONVENTIONAL CASCADE H-BRIDGE INVERTER

( 12)

Tables II, III summarize the number of steps and maximum value of the output voltage for conventional cascade multilevel inverter with three different methods in selection of the dc voltage sources magnitude and the proposed inverter respectively. One of the important problems for asymmetric multilevel inverters is the variety of magnitudes of dc sources. Fig. 5 shows, the magnitudes variety of the dc voltage sources in asymmetric state of the proposed topology (unary and binary methods) is less than recommended in conventional topology.

TABLE II. CONVENTIONAL CASCADE H-BRIDGE OUTPUT VOLTAGE AND OUTPUT STEPS VERSUS n ( n IS THE NUMBER OF BRIDGES)

Description same (Vdc) unary binary

Vo,max nVdc n(n + I)

(2n -1)Vdc 2

Ns1ep 2n+1 n(n+I)+1 2n+l_1

TABLE III. PROPOSED INVERTER OUTPUT VOLTAGE AND OUTPUT STEPS VERSUS n ( n IS THE NUMBER OF BASIC CELLS)

Description same (Vdc) unary binary

r�),max 2nVdc n(2n+ I)Vdc (4n -1)Vdc

N11ep 4n+1 2[n(2n+l)+1]-1 2(4n -1)+1

120

100

80

60

40

20

Sam e de sources

j � I B i n a ry I

j

40 60 80 100 120 No_ of voltage steps

(a) Conventional cascade inverter.

140

120 ,-----�--�--�-�--�-�

100 I S a me de sources

80

° O�-�1�OO�-=20�O -�300=- -- 4�OO--�50-0 ---600 No. of voltage steps

(b) Proposed structure.

Figure 5. Comparison of the required number of switches to realize

N,·tep voltage in conventional and proposed structures.

IV. CASE STUDY

Fig. 6 shows the two-cell arrangement of the proposed inverter. This circuit consists of four dc voltage sources and twelve switches. In this section, the overall output voltage with several possible series connection of the dc voltage sources to generate different voltage levels is explained.

S;J

S::J

+VI. _

L ad ------=-------

Sh] 11.

Sz:J SjJ

Figure 6. The two-cell arrangement of the proposed inverter.

In this section, the dc voltage sources with unary factor

scheme have been chosen. Table IV illustrates the value of V ()

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in accordance to the all possible series connection of cell voltage sources. This Table also shows, only one switch of each cell turns ON in different operation states of the inverter. This property is reduced the conduction loss of the switches.

TABLE IV. ALL POSSIBLE SWITCHING STATES

Switching states State Vo

Sal Sbl Scl Szl Sa2 Sb2 Sc2 Sz2

I 0 0 I 0 0 0 0 I VI

2 0 I 0 0 0 0 0 I V2

3 0 0 0 I 0 0 I 0 V3

4 0 0 0 I 0 I 0 0 V4

5 I 0 0 0 0 0 0 I VI +V2

6 0 0 0 I I 0 0 0 J!.3 +V4

7 0 0 I 0 0 0 I 0 VI +V3

8 0 0 I 0 0 I 0 0 VI +V4

9 0 I 0 0 0 0 I 0 V2 +J!.3

10 0 I 0 0 0 I 0 0 V2 +V4

11 I 0 0 0 0 0 I 0 VI +V2 +V3

12 I 0 0 0 0 I 0 0 VI +V2 +V4

13 0 I 0 0 I 0 0 0 V2 +V3 +V4

14 0 0 I 0 I 0 0 0 VI +J!.3 +V4

15 I 0 0 0 I 0 0 0 VI +V2 +V3 +V4

16 0 0 0 I 0 0 0 I 0

If the magnitude of all dc voltage sources ill Fig. 6 are equal to Vdc CV; = V2 = V3 = V4 = Vdc = \p.u.) , the effective

number of output voltage levels are in minimum because there are several common states to produce a same level at the output. The common voltages which can be obtained from several combinations of sources are listed follows:

v; = V2

= V3

= V4 = Ip.u.

V;+V2=V3+V4

=V;+V;

=V;+V4

=V2+V3

= V2 +V4 =2p.u.

v; +V2 +V3 = V; +V2 +V4

=V2+V;+V4

=V; +V; +� =3p.u.

When the dc voltage source magnitudes are not equal such as unary or binary schemes, inverter has more number of levels

at the output. This property is especially considerable in binary factor because in this method there is not any common state to produce the same voltage levels. In binary case, the inverter can generate 16-level at the output and with implementing of an H-bridge circuit, 3 I-level inverter can be obtained. Suppose that zero level is produced by H-bridge circuit. There are four defined switch states shown in Table V for H-bridge. Fig. 7 shows a two-cell 21-level typical output voltage waveform of the proposed multilevel inverter using unary scheme.

TABLE V. SWITCHING STATES FOR H-BRIDGE

State

1

2

3 4

T] +T] +T4 -----------------­

VI +13 +1'4 --------------­

'1+v2+v4············· v2 + v4 ----------­

v1 + v4 -------­v4 ------V, __ _

V _

S,

1

0

1 0

S2 S3 S4 vL 0 0 1 Vo

1 1 0 -Yo

0 1 0 0 1 0 1 0

2 V O�------------��------------�� --VI ---------------------------------------------------

--V2 ----------------------------------------------------. --V -------------------------------------------------------

3 --V4 ---------------------------------------------------------. --(v1+v4) --------------------------------------------------------------(v2 + V4) -------------------------------------------------------------

--(fl +V2 + V4) -------------------------------------------------------------------(Vi + [" + V4) ---------------------------------------------------------------------(v2 + [" + V4) ---------------------------------------------------------------------

--('1 + V2 +Vj +V4) ------------------------------------------------------------------------

Figure 7_ Typical output wavefonn of 21-leveL

V. SIMULATION RESULTS

To evaluate the performance of the proposed multilevel inverter, a single-phase 21-level with unary factor selection of input dc sources prototype is simulated and implemented based on the proposed topology according to the one shown in Fig. 6. In this investigation, the fundamental frequency switching strategy from several methods of modulation [12-15] has been applied to the inverter switches. The important advantage of the fundamental frequency switching technique is its low switching frequency compared to the other control strategies [8]. Figs. 8, 9 show the simulation results of output voltage before and after H-bridge. Fig. 10 shows the load current. As can be seen from the waveform, the output current is nearly sinusoidal. To generate a desired output with high quality of the waveform, the number of the voltage steps should be

352

increased. The inverter has been adjusted to generate 21-level 50-Hz staircase waveform. The load composed of R = 107Q and L = 55mH . The dc sources have been chosen in unary form by a factor of 10 (Vj = 10V, V2 = 20V , V3 = 30V and

V4 = 40V).

-Vo 100 90 ,..J L, ,..J L, ,..J L, ,.J L., 80 70 r' ., r' ., r' ., rI L, 60 J _L J _L J _L I I ..!::: 50 ,0 J l J l J l J L � 40

�� I � 10 lL

0

�I,J J

� ,J � L,

0.0000 0.0050 0.0100 0.0150 0.0200 0.0250 0.0300 0.0350 0.0400

Time [Sec] Figure 8_ Output voltage before H-bridge[v"J_

-VL 100 r C'-t L � 75

50 I ...'IJ. L ...'IJ. 25 1 � ..1 _\

� 0 JL -25

L\ L 1'1, / -50 -75 � L \ .I

-100 ---='= � '"'-!-t"

0.0000 0.0050 0.0100 0.0150 0.0200 0.0250 0.0300 0.0350 0.0400 TIme [Sec]

Figure 9. Output voltage after H-bridge [VLJ.

-IL 1.00 0.80 .... .... 060 / " / " 0.40 _L � -'- � 0.20 _L .1 0.00 IJ. .L

-0.20 Ll. 1,\ -0.40 � _L \ I

\. I \. I -0.60 '- / '- / -0.80 -1.00 , , , , , , ,

0.0000 0.0050 0.0100 0.0150 0.0200 0.0250 0.0300 0.0350 0.0400

Tillie [Sec]

Figure 10_ Output current [iiJ _

VI. CONCLUSION

In this paper, a four-level inverter topology named basic cell has been proposed. The proposed topology also have zero level (bypass) capability and this property make it possible to use in cascade arrangement with same basic cells for generating more number of the output voltage levels. The proposed inverter can reduce the number of switching devices compared with conventional multilevel inverters at the same number of output voltage levels. This topology has low conduction loss of the switches in comparison with other

topology because can generate the given level with low number of switches combination. The fundamental frequency switching scheme with low switching loss property have been used to produce firing pulses. Therefore, the proposed inverter can be applied to solar, fuel cell, and also medium/high power applications.

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