Modeling of NMOS Performance Gains from Edge Dislocation Stress Cory E. Weber, Stephen M. Cea, Hemant Deshpande*, Oleg Golonzka*, and Mark Y. Liu*

Process Technology Modeling/*Portland Technology Development, Intel Corporation, RA3-254, 2501 NW 229th Ave, Hillsboro, OR, United States, 97124 Phone: +1-503-613-9875, fax +1-503-613-8950, email:cory.e.weber@intel.com

Abstract

Stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching 1GPa at 100nm gate pitch. This scaling trend makes edge dislocations attractive for future technology nodes, as stress from epitaxial and deposited film stressors reduces as pitch is scaled (1,2). We show a gate last flow is best for maximizing the dislocation stress, and the stress varies with layout and topography. We arrive at these results by the application of the finite element method to model the dislocation stress.

I. Introduction

Vacancy-type edge dislocations are introduced from amorphization implants and subsequent solid phase epitaxial regrowth (SPER) processes (3), as illustrated in Fig. 1. These dislocations have been shown to introduce stress resulting in NMOS mobility enhancement (4). However, the previous analysis used an analytic model (5) that is only accurate in the case of an infinite bulk medium. To evaluate realistic devices with surfaces and material interfaces, a numeric model for dislocation stress is required.

II. Modeling Methods

Stress is calculated using the finite element method (FEM)

using a proprietary version of the FLOOPS software (6). To comprehend the stress from edge dislocations, a displacement boundary condition equal to the Burgers vector is introduced between nodes at the dislocation cores (7). All device simulations use the same nmos doping structure calibrated to Intel’s 32nm process technology (8). In the case of 3D simulations, this doping structure is extruded in the width direction. The stress fields from stress simulations are mapped onto this structure, so all simulated drive current differences in this paper are due to stress. Stress impact on device mobility is captured with the model of Kotlyar (9).

III. Analytic Results vs. FEM Simulations

The FEM stress solution is matched to the analytic solution when the surfaces are far from the dislocation cores, as seen in Fig. 2a, verifying the FEM approach. When we include the free surface in the FEM calculation, as seen in Fig. 2b, we see over 2.5x enhancement in the lateral stress near the surface. Fig. 3 shows the free surface causes complete relaxation of the vertical stress near the surface. The

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Fig. 1. A schematic showing how vacancy edge dislocations typically

appear in a nmos device with SPER processes. The dotted lines show

the dislocations.

Fig. 2. Lateral dislocations stress solutions for (a) a case where the

top surface is 50μm above the dislocation cores. Black line

contours are the analytic solution ranging from -600MPa to 600MPa

in 200MPa steps, color contours are the FEM solution. (b) The FEM

solution where the top surface is 30nm above the cores. Both

structures are symmetric about X=0nm and are 300μm wide.

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higher lateral stress more than offsets the relaxed vertical stress for the piezo mobility enhancement calculation (10), with the FEM solution showing 1.6x to 4.5x more enhancement than predicted by the analytic solution. FEM solutions are used for the remainder of the paper, with the dislocation core offset 5nm away from the gate and 25nm below the surface.

IV. Edge Dislocation Impact on Current

Fig. 4 shows the stress and idsat gains from edge dislocations increase as gate pitch is scaled. This is because the displacement from the edge dislocation is fixed at the Burgers vector, whereas the volume over which that displacement relaxes reduces as pitch is scaled. Experimental idsat shows the same trend vs. gate pitch that is seen in simulations. Going to a gate last (GL) flow increases the stress ~30% over a gate first (GF) flow, reaching 1GPa at 100nm pitch. The GL flow removes the constraint on strain at the channel surface, as illustrated in the stress contours in Fig. 5a and 5b. Introducing shallow trench isolation (STI) oxide with a STI oxide recess (STIR)

in the current flow direction reduces idsat gains by as much as 10%, as seen in Fig. 6. This is because the free surface introduced by the STI process in the lateral direction relaxes the lateral stress, as seen in Fig. 5c. This relaxation may be mitigated by eliminating the recess and by increasing gate to trench distance, as shown in Fig. 6. Fig. 7 shows

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Fig. 4. (a) Effective channel stress from edge dislocations vs. gate

pitch for GF and GL flows. Effective channel stress is calculated

by integrating the product of stress and electron density, then

dividing by the average electron density, in the on-state.

(b) Simulated and experimental idsat gains from edged dislocations

vs. gate pitch for GF and GL flows. These results are for nested

devices. The dashed vertical line is at the target pitch of Intel’s

32nm node.

Fig. 3. Lateral (Sxx) and vertical (Syy) edge dislocation stress

solutions, and piezo mobility enhancement along the dashed line cut

shown Figure 2. The analytic(ANA) results do not comprehend

surface effects, while the FEM results do.

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dislocation gain may decrease ~5% as device width is scaled to 50nm, as stress in the width direction becomes more compressive due to edge forces from the Poisson effect around the STI-silicon boundary, as shown in Fig. 8. Fig. 7 indicates this effect could be lessened by increasing the recess, but the gains from doing this would not offset the losses for isolated devices. It is also possible that layout differences may affect the formation of the dislocation, adding an additional source of variation not

modeled here.

V. Conclusion

Simulations show that unlike most conventional stressors, dislocation stress increases as gate pitch is scaled, reaching over 1GPa, making dislocation stress an attractive option for future technology nodes. FEM simulations show surfaces have strong impact on dislocation stress, resulting

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Fig. 6. Idsat gain and effective stress from dislocations as a function

gate to trench distance for wide isolated devices on a GL flow.

Fig. 5. Lateral stress contours(MPa) from edge dislocations in 113nm gate pitch nmos devices, for (a) a nested device with a GF flow, (b) a

nested device with a GL flow, and (c) an isolated device with GL flow and 30nm STIR.

Fig. 7. Idsat gain and effective stress from dislocations as a function

of device width for nested devices on a GL flow.

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in increased stress for a GL flow, and stress layout dependence. Narrow and isolated devices show some stress loss, but this degradation may be reduced by engineering the isolation recesses.

VI. Acknowledgements

We would like to thank our colleagues at Intel Corporation.

We are grateful to Kevin Johnson and Martin Giles for

helpful discussions on this topic. We would also like to

acknowledge Tahir Ghani and Sanjay Natarajan for

supporting the experimental work referred to in this paper.

VII. References

(1) G. Eneman et al., “Layout impact on the performance of a locally

strained PMOSFET,” VLSI Sym. Tech. Dig., pp. 22-23, 2005.

(2) P. Grudowski et al., “1-d and 2-d geometry effects in

uniaxially-strained dual etch stop layer stressor integrations,” VLSI

Sym. Tech. Dig., pp. 62-63, 2006.

(3) H. Cerva and K.-H. Kusters, “Defect formation in silicon at a mask

edge during crystallization of an amorphous implantation layer,” JAP,

vol. 66, pp. 4723-4728, November 1989.

(4) K-Y. Lim et al., “Novel stress-memorization-technology (smt) for

high electron mobility enhancement of gate last high-k/metal gate

`devices,” IEDM Tech. Dig., pp. 229-232, 2010.

(5) F.R.N. Nabarro, “The mathematical theory of stationary dislocations,”

Adv. Phys., vol. 1, pp. 269-395, 1952.

(6) M.E. Law and S.M. Cea, “Continuum based modeling of silicon

integrated circuit processing: an object oriented approach,” Comp.

Mat. Sci., vol. 12, pp. 289-308, (1998).

(7) K.Sasaki, M. Kishida, and Y. Ekida, “Stress analysis in continuous

media with an edge dislocation by finite element dislocation model,”

Int. J. Numer. Meth. Eng, vol. 54, pp. 671-683, March 2002.

(8) P. Packan et al., “High Performance 32nm Logic Technology

Featuring 2nd Generation High-k + Metal Gate Transistors,” IEDM

Tech. Dig., pp. 659-662, 2009.

(9) R. Kotlyar et al., “Effect of band warping and wafer orientation on

NMOS mobility under arbitrary applied stress,” J Comput. Electron.,

vol. 7, pp. 95-98, December 2007.

(10) C. S. Smith, “Piezoresistance effect in germanium and silicon,” Phys.

Rev. vol. 94, pp. 42-49, April 1954.

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Fig. 8. Z-stress contours (MPa) of a 50nm wide nested device on a GL flow. Cases shown are

(a) STIR=0nm and (b)STIR=30nm. The gate, insulator, and contact layers have been removed

from over the STI for visualization purposes. Dimensions of all features in the xy plane are

identical to Fig. 5a & b.

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