A Low Noise and Highly Linear 2.4-GHz RF Front-End Circuit for Wireless Sensor Networks

Chihoon Choi, Joonwoo Choi, and Ilku Nam School of Electrical Engineering, Pusan National University, Korea

Abstract- This paper presents highly linear and low noise RF

front-end circuits for 2.4-GHz low-IF receiver. The proposed RF

front-end circuits consist of a low noise amplifier (LNA) using

on-chip transformer and a down-conversion mixer using parasitic

vertical NPN bipolar junction transistor. By adopting these

devices, both linearity and noise performance are improved. The

RF front-end circuits have been implemented in 0.18 J.lIIl deep

n-well CMOS process. A gain of33 dB, an HP3 of -12 dBm, and a

DSB noise figure of 4.5 dB have been achieved. The circuits

consumes 5 mW from 1.8 V supply and occupies a chip area of 0.45 mm2•

I. I NTRODUCTION

A low-rate wireless personal area network, IEEE 802.15.4,

is designed for low-cost and low-power short-range wireless

communications [1]. Because the 2.4 GHz industrial, scientific,

and medical (ISM) band used by the IEEE 802.15.4 physical

layers is unlicensed in nearly all countries, the receiver for the

IEEE 802.15.4 radios must put up with many interferers caused

by other services operating in the same band. The improvement

of linearity in these receivers is essential. Because the receiver

linearity is dominated by that of RF front-end circuits composed

of a low noise amplifier (LNA) and a down-conversion mixer,

the linearity of RF front-end circuits is very important. To

improve the linearity of RF front-end circuits, several circuit

techniques have been used. For example, there are negative

feedback [2], MOSFET transconductance linearization by

multiple gated transistors [3], and current amplification [4], [5].

Also, on-chip transformer based RF circuits are very attractive

because power supply voltage continuously becomes lower

[6-9].

The noise figure (NF) of a receiver is also important because

the sensitivity of the receiver is dependant on the noise figure.

In general, 1/j noise of a down-conversion mixer does not

degrade the NF of the low-IF receiver. However, if the

transformer is employed as the load of a LNA to improve the

linearity, 1/j noise of the down-conversion mixer considerably

can affect the noise performance of the low-IF receiver.

In this paper, we propose highly linear and low noise RF

front-end circuits using an on-chip transformer and vertical

NPN (V-NPN) bipolar junction transistors for short-range

wireless sensor networks.

978-1-61284-193-9/11/$26.00 2011IEEE

Fig. 1. Simplified schematic of voltage-current converter chains.

II. 2.4-GHz RF F RONT-END C IRCUITS

The nonlinear characteristic of CMOS RF circuits is

dominated by the transconductacne nonlinearity [3]. In general,

as shown in Fig. 1, voltage-to-current conversion in

transconductors and then the current-to-voltage in load stages

reiterate in the receiver chain. The ac drain currents (iJ and i2) of

the voltage-to-current converter chains in Fig. 1 can be simply

expressed as

(1)

where g'm is the first derivative and g"m is the second

derivatives of transconductance gm with respect to the

gate-to-source voltage. As known in Eq. (1), due to the

transconductance nonlinearity, when voltage input signal is

converted to current output signal by the driving transistor, the

current output signal includes many distortion components. For

linearity improvement, it is important to remove transcoductors

which include distortion in critical nonlinear path. Therefore,

by coupling the LNA's output signal to the input of the

down-conversion mixer through a on-chip transformer without

voltage-to-current conversion in transconductors, we can

remove the distortion factor and improve the linearity of

receiver front-end circuits.

Figure 2 shows a layout of 4:2 transformer, where, P and S

s+

�J P+ efHlt., p. Top

s· p.

Fig. 2. Layout diagram of 4:2 transformer and its symbol.

C_ 95.91 IF C_

P+ p.

C.�

(F 1 c.", ..

T>p 1

s·

c_ 95.91 fF

R, 3.730

L, 5.6 nH

R, 3.730

731� . rlt T3�171f

'1�1--+" __ --.4II),:---""""N-"""-l I'

R,. .. 177.1Hl

Co 26fF

R,,1.7Q C�� 33.9 fF C"u . rr, 25�84fF ' 1'l.....,...J' "-

S + 501.46Q Center Tap s·

R_ 177.17 C!

Co 26 fF

C_ c ....

16.95fF

12iV "-

1000.92Q

Fig. 3. Equivalent circuit of transformer and its electrical value.

I·

denote the primary and secondary windings, respectively. The

primary winding is a four-turn symmetric inductor and the

secondary winding is a two-tum symmetric center-tapped

inductor. The size of transformer is 270 ,urn x 270 ,urn. Figure 3

shows an equivalent circuit of the on-chip transformer. The

equivalent circuit is modeled using EM field simulation and

process parameters provided by a foundry. The total current

transfer ratio Is /Ip of the parallel resonant transformer can be

represented as

(2)

where Ip and Is are the currents in the primary and the secondary

winding, k is the coupling coefficient, Q is the quality factor, Lp

and Ls is the inductance of the primary and secondary windings,

respectively [10].

As shown in Fig. 4, it is possible to obtain the current gain

from the output of the LNA to the input of the down-conversion

mixer as described in Eq. (2). However, the NF of the front-end

circuits in Fig. 4 is degraded by the l/j noise of the

down-conversion mixer. This is because the low Q -factor of

the transformer in a CMOS process and the loss from primary to

secondary port. To improve the NF of a low-IF receiver

adopting LNA with on-chip transformer as a load, the V-NPN

bipolar transistors available in deep n-well CMOS process can

2

RF�rr

Vb1 Ls ...

Fig. 4. Simplified schematic ofRF front-end circuits using on-chip transformer and NMOS switches.

RF�rr

Vb1 Ls ...

Fig. 5. Simplified schematic of proposed RF front-end circuits.

be used in the switching pair instead of NMOS switches [11].

Since the l/j noise of the vertical NPN is smaller than that of

NMOS, the NF of the low-IF receiver can be reduced.

Therefore, using on-chip transformer in the load of the LNA

and the input stage of the down-conversion mixer and V-NPN

in the switching pair of the mixer is a good solution for highly

linear and low noise RF front-end circuits. In addtion, it can be

the inter-stage matching between the output of the LNA and the

input of the down-conversion mixer by using the ratio of

primary winding and secondary of the on-chip transformer.

Also, by using on-chip transformer as a balun, the single-ended

signal from the LNA can be converted to differential signals to

the down-conversion mixer.

Fig. 6. Chip microphotograph of the receiver front-end circuits.

E m � � ·25 o Q. ::0 s-::0

o -50

-75

.or

-60 -50

.

... 0 -30

IIP3 = -12 dBm (V-NPN) IIP3 = -13 dBm (NMOS)

·20 -10 Input powe, (dBm)

Fig. 7. Measured IIP3 of the receiver front-end circuits.

The simplified schematic of the proposed RF front-end

circuits is shown in Fig. 5_ In order to improve the NF and

linearity at the same time, we adopt the common-source LNA

which has high gain and low NF and the common-gate

down-conversion mixer which has high linearity. As shown in

Fig 5, the load capacitor of the LNA and the cross-coupled

capacitors of the input stage of the mixer with parasitic

capacitance are used for the resonance mode. Also, these

cross-coupled capacitors enable the mixer to achieve gain

boosting [9].

III. EXPERIMENTAL RESULTS

The RF front-end circuits using on-chip transformer and NMOS switches and proposed RF front-end circuits with on-chip transformer and V-NPN switches have been

implemented in 0.18 J.LIT1 CMOS process. The chip photograph of the proposed RF front-end circuits is shown in Fig. 6. The size of the chip including LNA, on-chip transformer,

down-conversion mixer, LO buffer, and bias circuit is 0.4 mm x 1.12 mm. Fig. 7 shows the IP3 measurement results when two tones at 2402.5 MHz and 2403.5 MHz are mixed with the LO frequency of 2400 MHz. The IIP3 of the proposed front-end circuit is measured as -12 dBm and IIP3 of the RF front-end circuit using on-chip transformer and NMOS switch is measured as -13 dBm, respectively. In the case of two RF front-end circuits, the linearity is greatly improved by using on-chip transformer and the common gate down-conversion

3

35

30

CD 25 � � 20 0>

-=

� 15 '0 Z

10

10k lOOk 1M Output frequency (Hz)

• V-NPNI NMOS

10M

Fig. 8. Measured noise figure of the receiver front-end circuits.

TABLE I MEASURED RECEIVER FRONT-END PERFORMANCE SUMMARY

RF front-end circuit Proposed RF

using transformer and front-end circuit

NMOS switches RF frequency 2.4GHz 2.4GHz IF frequency 2 MHz 2 MHz

Gain 32 dB 33 dB IIPJ - 13 dBm - 12 dBm

NF (DSB) 9 dB 4.5 dB Current

3 rnA@ 1.8 V 2.78 rnA@ 1.8 V consumption

Technology 0.18 .urn deep n-well 0.18 .urn deep n-well

CMOS CMOS

mixer. Figure 8 shows the noise figure of two RF front-end circuits

measured with Agilent E4448A spectrum analyzer and a low-noise pre-amplifier, and a noise source. As shown in Fig. 8, the noise performance of the RF front-end circuits using on-chip transformer and NMOS switches is degraded even in the range of a few MHz by the flicker noise of the NMOS switches. Therefore, the RF front-end circuits are disadvantageous for low-IF receivers. On the other hand, because the proposed RF front-end circuits using on-chip transformer and V-NPN switches show I1f noise free characteristics, the proposed circuits are very suitable for low-IF receivers. Table I summarizes the measured performances of two RF front-end circuits. The proposed RF front-end circuits are suitable for highly linear and low noise RF front-end.

IV. CONCLUSIONS

Transformer based CMOS RF front-end circuit can improve

the linearity of a receiver. However, it is unsuitable for a low-IF

receiver due to poor noise performance. In this paper, a highly

linear and low noise RF front-end for a low-IF receiver is

proposed. The proposed circuit can improve both the linearity

and noise performance by using on-chip transformer and

V-NPN simultaneously. The proposed RF front-end chip is

fabricated in 0.18 J.LIT1 deep n-well CMOS process. A gain of 33

dB, an IIP3 of -12 dBm, and a DSB noise figure of 4.5 dB have

been achieved, consuming 5 m W from 1.8 V supply voltage.

ACKNOWLEDGEMENTS

This works was supported by the Human Resources

Development of the Korea Institute of Energy Technology

Evaluation and Planning(KETEP) grant funded by the Korea

government Ministry of Knowledge Economy (No.

20104010100670.

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