An Overview of Methods to Increase the Power Handling Capability of Single Stage AC-DC

Converters Mohammed S. Agamy1, Member IEEE & Praveen K. Jain2, Fellow IEEE

1: General Electric Global Research Center, Niskayuna NY, USA 2: Queen’s University, Kingston ON, Canada agamym@ge.com, praveen.jain@queensu.ca

Abstract- Single stage power factor correction converters provide a power dense and economic way for interfacing telecom systems to the utility grid. However, they face several efficiency and component stress issues that limit their applicability to low power applications. This paper reviews the methods used to improve the efficiency and power handling capabilities of single stage power factor correction converters.

I. INTRODUCTION

AC/DC converters (rectifiers) are the first building block in switched mode power supplies (SMPS). They form the interface between the utility grid and all the down-stream converters. Therefore, they should provide performance characteristics that are acceptable by both the supply mains and the output load. From the utility point of view, a power supply should provide good power quality, i.e. the input current and input line voltage should be purely sinusoidal at the line frequency (50 or 60 Hz) and be in phase with each other. Whereas, the load side requires that the rectifier provides a well regulated output voltage with adequate hold up time capabilities, low ripple content and high efficiency. However, the use of switched mode power supply introduces some adverse effects to be seen on the utility side. Examples of such effects are, distortion of line current/ line voltage, sags due to charging of bulk capacitors and electromagnetic interference (EMI) due to switches being turned on and off at high frequency. The relationship of telecom power supplies and power quality is similar to that of general purpose SMPSs. The telecom power supply has, however, some distinctive power quality related characteristics that set it apart from the common SMPS [1]. • It operates at a relatively high power level; therefore, it has

a much greater local impact on power quality than other power supplies operating at lower power levels.

• The greatest effect a telecom SMPS has on power quality is due to the harmonic currents and EMI injected in the line. Some earlier designs also introduced a lag in the fundamental current.

• Availability is very important because of the uninterrupted service required in telecommunications. This requires highly reliable equipment, as well as local energy storage.

• Energy conversion efficiency is more important in telecom applications than in other applications, due to the practically continuous operation and the relatively high power levels. There is a tradeoff that always exists between

converter cost and efficiency, due to the need of switches with higher ratings; however, this can be tolerated because of the long periods of operation of these converters, which consequently reduces the running cost [1].

Since regulations do not require a perfectly sinusoidal input line current, efforts have been made to obtain smaller converters with fewer switches that could comply with the regulations and be more cost effective. This led to the emergence of single-stage power factor corrected (SSPFC) converters. The basic SSPFC circuits were introduced in the early 1990s by Madigan et. al. This was achieved by integrating the boost input current shaping converter with either a flyback or a forward converter [2]. Since SSPFC converters operate as the interface between the power grid and the downstream converters and devices, these circuits are required to provide performance that is compliant with both the input and output requirements. They should provide a well regulated fast compensated output voltage, at the same time it isolates the effect of the high harmonic content produced by electronic circuitry from the input power mains as well as providing high conversion efficiency. Several topologies were introduced in the literature to achieve these goals, but these single stage converters had limitations over their output power and input voltage ranges because they were found to exhibit at least one of the following drawbacks: (i) existence of circulating currents, (ii) tradeoffs must be made between the DC-bus voltage level and harmonic content of the input current, (iii) for variable frequency control a very wide range of frequency variation is needed to cope with the universal line input voltage range, (iv) The need for complicated circuitry and/or control methods and/or (v) high component voltage and current stresses: the wide variation of the storage capacitor voltage with the change of either the input voltage or the loading condition is one of the main drawbacks of using SSPFC converters. The capacitor voltage can reach very high levels especially at light loading conditions. This imposes high stresses on the converter switches. Therefore, the single stage converters end up having lower efficiencies compared to the classic two stage solution and are thus, limited to power ranges of a few hundred Watts. Several methods have been introduced to solve the problems of high stresses/ low efficiency of SSPFC converters by topology modifications, using auxiliary circuits or through converter control. This paper presents an overview of the numerous attempts made to solve the problems of SSPFC

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converters in order to increase their efficiency and power range.

II. COMPONENT STRESS REDUCTION

In the classic SSPFC converters presented in [2], shown in fig. 1, the boost input current shaper operates in discontinuous conduction mode to achieve automatic current shaping, while the dc/dc converter cascaded with it may operate in either continuous or discontinuous conduction mode. However, if the dc/dc converter is in continuous conduction mode the dc bus voltage varies with the output load. For universal input applications, it will suffer high voltage stress at high input voltage and light load, which requires expensive capacitors and increases the switch voltage stress. One of the suggestions to solve this problem is to operate both the input current shaper and the dc/dc converter in the discontinuous conduction mode, but this leads to undesirable ripples and oscillations in the output voltage as well as very high current peaks which makes it impractical to use this type of converters for applications above a few hundred watts. Other approaches such as those presented in the literature [3-10]. In [3, 8] a compromise between the THD and the capacitor voltage stress is made in order to maintain the continuous conduction mode at the output. The voltage stress on the bulk capacitor can also be reduced by introducing a feedback loop in the power circuit [5, 9] as shown in fig, 2. This feedback winding is used to detect the dc bus voltage as a feedback signal. In this case, when the load becomes light, the duty ratio does not change. As a result the PFC stage provides more power than the load needs. The unbalanced power between the input and the output will be stored in the bulk capacitor, which in turn increases the dc bus voltage. When the increased dc bus voltage is fed back it tends to reduce the duty ratio. Furthermore, the absorbed energy in the input inductor becomes small since the charging voltage across the inductor is the rectified input voltage minus the partial dc bus voltage. The key design parameters for the reduction of the dc bus voltage are the boost inductor (Lin), the transformer magnetizing inductance (Lm) the number of turns in the primary flyback transformer winding (N1) and the feedback winding (N2). The smaller the (Lm/Lin) ratio, the lower the bulk capacitor voltage stress. The boost inductor cannot be arbitrarily large in order to maintain discontinuous conduction mode operation. Therefore Lin should be designed at the maximum value that can maintain this mode. A smaller value for Lm leads to getting a limited effect on reducing the output current stress and the output ripple; hence a compromise between these values and the voltage stress must be made. Asymmetrical pulse width modulated half bridge converters have also been proposed in order to limit the dc-link voltage rise as in [11], but this approach lead to high circulating currents and high conduction losses in the circuit. Whereas, in [12, 13] partial power flow in the capacitor is used to limit the capacitor charge at partial loading conditions and thus reducing the voltage stress across capacitors and switches. Other examples of SSPFC circuits use auxiliary

circuits in order to obtain a reduced bulk capacitor voltage. References [14] and [15] present an SSPFC rectifier based on a forward converter. This circuit, shown in fig. 3, has an auxiliary circuit whose purpose is to get a reduced bulk capacitor voltage stress. This converter is designed such that it always operates in the discontinuous conduction mode. This provides high power factor, however, this comes at the expense of an increased current stress on the power circuit components. This results in high conduction losses and thus reduced efficiency. This makes the operation of the converter restricted to a low output power range, typically below 200W.

.

s(t)

DiodeRectifier

L1 D1 D2C1

C2

Loadis(t)

Q1

Boost + FlybackBIFRED

DiodeRectifier

L1 D1

(t)

is(t)

Q1

C1a C1b Load

C2D2

L2

Boost + BuckBIBRED

(a)

(b)

Fig. 1 Basic SSPFC converters (a) Boost Integrated Flyback, (b) Boost Integrated Buck

Fig. 2 DC-bus voltage stress reduction techniques in SSPFC converters: (a) Using feedback winding [9], (b) Using auxiliary transformer [5]

(a)

(b)

Fig. 1 Basic SSPFC converters (a)

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III. SOFT SWITCHED CONVERTERS

Soft switching methods have been widely used in order to improve SSPFC converter efficiency. Soft switched SSPFC converters can be divided in two main groups: first, converters employing auxiliary soft switching circuits [16-20] and the second group includes resonant power converter topologies [21-32]. A. PWM converters with auxiliary circuits Auxiliary circuits are used with either regular boost PWM converters or half bridge or full bridge converters in order to provide discharge paths for the switch capacitances to achieve zero voltage switching (ZVS) or to limit the turn ON current in order to provide zero current switching (ZCS). The disadvantage of these topologies (an example of which is shown in fig. 4), is the added circuit and control complexity, furthermore, they do not provide a solution for conduction losses due to circulating currents.

B. Resonant Converters Resonant converters have many attractive properties, such as zero voltage switching, high power densities due to the operation at high switching frequency, low cost and high efficiency. Therefore, they have also been studied in their operation in high input power factor mode. The LC series resonant converter is not a very attractive candidate for PFC operation due its voltage step down characteristics; therefore, it cannot maintain line current into

the valley of the rectified input AC voltage waveform and hence must be shut off typically when the line voltage falls below 50% of its peak value. LC parallel and LCC series/parallel resonant converters, shown in fig. 5, have boosting capabilities; therefore, they can be used in high power factor operation modes [21 & 22].

The series/parallel resonant converter generally has lower component stresses compared to the parallel resonant converter. On the other hand, this converter requires active current control and a wide frequency swing to maintain ZVS over the line half cycle. The other problem is the high component of low frequency current at the output and thus the existence of low frequency oscillation in the output voltage, due to the lack of a storage capacitor in these circuits. In [23 & 24] series/parallel resonant converters were employed as single stage power factor correctors. They were operated with and without active current control giving good results in both cases but still the range of input voltage and output power for these converters is limited. Other topologies and control methods for full bridge resonant circuits operating as single stage power factor correctors are demonstrated in [25-31] but their efficiency, component stresses and/or compromised distortion of the input current waveform still limit their applicability to the range of output power to a few hundred watts. Resonant topologies have also been implemented with bridgeless SSPFC converters in order to eliminate/reduce switching losses. Since bridgeless converters have less diodes in their conduction path, a reduction in conduction losses is also achieved [32-33]. However, the use of resonant converters requires a very wide range of frequency variation to maintain the dc-bus voltage within a limited range for the whole load range (starting from the resonant frequency and up to 7-10 times the resonant frequency.) This complicates converter layout considerations, filter design and EMI suppression. Furthermore, variable frequency control in this fashion leads to significantly reduced part load efficiency.

Fig.3 SSPFC rectifier based on forward converter

Fig.4 An SSPFC full bridge converter with auxiliary ZVS branch [16]

is(t)

Vs(t)Co

Load

Vo

+

-

Lo

CpCi

Ls

RL

+

-

Ein

is(t)

Vs(t)Co

Load

Vo

+

-

Lo

CpCi

Ls

RL

+

-

Ein

Cs

(a)

(b)

Fig. 5 Resonant converters used for PFC: (a) LC parallel resonant converter, (b) LCC series/parallel resonant converter

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Using control methods such as self-sustained oscillation controllers limits the switching frequency range [26-28], but the input current quality is still degraded and despite complying with IEC 1000-3-2 for low power applications, it will not meet the IEC1000-3-4 standard for higher power applications [55-57].

IV. THREE-LEVEL CONVERTERS

Three level DC/DC converters were first proposed by J. Pinheiro and I. Barbi in 1992 [34-38]. This topology was first derived from hard switching three level inverters. The basic purpose of such converters is to reduce the voltage stress across the switches so that the converter can be operated at higher voltage levels with smaller switches having better switching and conduction characteristics. Three-level converters have been used in soft switched PWM as well as series resonant converters [39-45]. For all the different topologies presented, the converter gives good performance and high efficiency for a wide range of input DC voltage and high power applications. With proper design and switching sequences the converters also provide ZVS for a wide range of input voltage and output loads. Due to the features and performance of the three level DC/DC converters, they are considered good candidates for front end power factor correction converters. Several topologies for this application have been proposed in the literature [46-49]. As an example of these topologies, in [46] a three level boost converter was used as a power factor pre-regulator followed by a ZVS isolated DC/DC converter. The DC/DC converter is composed of two series connected half bridge converters. The use of phase shift modulation led to the reduction of voltage stress across the capacitors compared to the equivalent PWM converter. Moreover, the current stresses are shared equally among all switches resulting in higher converter efficiency. However these approaches have not taken full advantage of the flexibility of control provided through the use of multi-level converters, which led to the dc-bus voltage still drifting to very high levels at light loading conditions. Due to the features and performance of the three-level dc/dc converters and those of resonant power converters, they are considered good candidates for front end power factor corrected converters. Combining these two types of converters and utilizing the additional degrees of freedom obtained in three-level converters a family of SSPFC converters was presented in [50-52], shown in fig. 6. The converter is basically composed of a three level half-bridge resonant circuit with an input inductor connected directly to the lower pair of switches. Different types of resonant converters are applied for this purpose and in some cases auxiliary circuits are required. Due to the composition of this converter, there are more degrees of freedom to which the control can be applied. Therefore, two control variables are used, the two options studied here are (i) variable frequency + asymmetrical PWM (VFAPWM) and (ii) variable frequency + phase shift

modulation control (VFPSM). In the first, the variable frequency is used to regulate the output voltage, whereas the pulse width modulation is used to regulate the dc-bus voltage to a pre-defined level for all loading conditions as well as input current shaping. In the second control scheme the phase shift between the switching signals is used to regulate the dc-bus voltage. The combination of variable frequency with either phase shift or PWM control also alleviates the problem of wide switching frequency range required by the converter as seen in [21, 22 & 58] as both control variables assist each other (the frequency range starts at 1.1 times to resonant frequency and has a maximum of only 2.5 times the resonant frequency). This leads to the need of narrower range for the variation of both variables, therefore simplifying the design of the converter. Furthermore, in [54] self-sustained oscillation control is applied in combination with asymmetrical pulse width modulation for a three level half bridge SSPFC converter, where the APWM control is used for regulating the dc-bus voltage and input current shaping and the SSOC controller is used for fast output regulation. In this case the maximum switching frequency is limited to 1.5 times the resonant frequency.

Additional control features can easily be added to these converters to improve partial load efficiency as presented in [53], where the dc-bus voltage is regulated based on the loading condition in such a way that creates a virtual full load

(a)

(b)

Fig. 6 Three-level resonant SSPFC converters (a) using VFAPWM Control, (b) using VFPSM control

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condition for the resonant converter for a much wider range of loading. Three-level SSPFC converters have shown efficiencies in the range of 95% for power ratings of multiple kilo-watts and are showing very strong potential to be operated at very high switching frequencies which will allow for very high power density as well [54]. Three-level half-bridge converters do not result in added parts as compared to full bridge topologies since they only result in rearranged connections with lower rated switches.

V. CONCLUSION

Several issues that limit the power handling capabilities of SSPFC converters are presented. Combining resonant converters and three-level topologies shows a very strong potential for building high power, high frequency and efficient SSPFC circuits. Table 1 shows a qualitative comparison between different SSPFC converter technologies. Future efforts can be aimed at developing bridgeless three-level topologies and employing SiC devices in order to further improve efficiency and power density.

Table 1. Qualitative comparison between different SSPFC converter technologies

Efficiency Additional components

needed?

Power handling capability

Frequency range (if variable

frequency control is

used) Converters with voltage

feedback

Low Yes Low Wide

Full bridge with

auxiliary circuit

Medium Yes Medium Medium

Full bridge resonant

Low/Medium No Low Wide

Three-level resonant circuits

High No High Narrow

Boost/Buck-boost with

DCM

Low No Low Wide

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