18th IEEE Conference on Advanced Thermal Processing of Semiconductors - RTP 2010

Location- and orientation-controlled, large single grain silicon induced by pulsed excimer laser crystallization

M.R. Tajari Mofrad, R. Ishihara, J. van der Cingel and C.I.M. Beenakker

Delft University of Technology, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS)

Department of Microelectronics and Computer Engineering (ME&CE) Delft Institute of Microsystems and

Nanoelectronics (DIMES) Feldmannweg 17, POBox 5053, 2600 GB Delft, The Netherlands Tel: +31-(0)15-2787307 Fax: +31-(0)15-2787369

Abstract- We studied pulsed laser induced epitaxy of silicon using a seeding wafer to realize location­

and orientation-control of silicon grain. Silicon grains as large as 4 I'm x 4 I'm with mostly the

preferred (100) orientation area were obtained on top of contact openings through Si02 to seeding

silicon (100) wafer. The orientation of the seed is inherited by a-Si during the solidification phase of

molten-Si. The maximum process temperature of this process is 545°C which is for LPCVD deposition

of a-Si. This layer is suitable for high mobility SOl CMOS devices which serve as building blocks for

monolithic 3D integration.

I. Introduction

Down-scaling of transistors increases the

complexity of the process and thus the

fabrication. Whether there will be a hard limit to

down-scaling, it still needs to be determined [1].

However, higher transistor density needs more

space reserved for routing purposes, which

decreases the advantage of the scaling.

Moreover, the interconnect delay increases in

such a way that it becomes the limiting factor for

circuit performance [2].

Three-dimensional (3D) integration is a solution

for these issues as it shortens the interconnect

length and lowers power consumption. It also

increases the functionality of a chip by enabling

integration of a sensor layer on top of it. It can

be considered low cost since the expenses

required for developing new equipment or new

deep sub-micron processes is not needed [3].

978-1-4244-8399-0/10/$26.00 © IEEE

Between several existing 3D IC technologies,

monolithic integration is promising to offer the

highest density and speed. However, obtaining

high quality crystalline silicon (c-Si) in low

temperatures, demanded by monolithic character

of this technology is usually a severe challenge.

In the past, we have reported location-controlled

large single grains (SG) silicon obtained by the

so-called J.l-Czochralski process [4]. By placing

the channel of the MOS devices inside such

large grain, we could obtain thin film transistors

with mobilities as high as 600 cm2Ns [5][6].

This principle is shown in Fig. 1. Here we see

two adjacent silicon grains with a channel of the

TFT positioned in a grain-boundary-less area.

But lacking a single seeding crystal orientation

caused the grain to grain crystal orientation

differences. The point for improvement lied in

the non-uniformity of the electrical

characteristics of devices, since mobility of a

MOS transistor is dependent on the

crystallographic orientation of the channel

material. Controlling this parameter can reduce

the variability of transistors in a 3D Ie.

Laser induced epitaxy is the perfect method to

achieve this goal. By opening a hole into a

seeding layer e.g. bulk c-Si the

created in this manner reduce the hole diameter

down to 300 nm. The cavities are filled with 250

om thick low-pressure chemical vapor

deposition (LPCVD) a-Si at 545 °C. The

schematics of the process is shown in Fig. 2.

Pulsed XeCI excimer laser (A,=308 nm) is used

D MOO transistor Channel to melt the silicon. The schematics of the laser

D D crystallized silicon

D seeding openning

Figure 1: Principle of high mobility TFTs built on SG

siliconamorphous silicon

(a-Si) contacting the seed layer can inherit the

crystallographic orientation of the seed while

solidifying from the molten state due to laser

irradiation. By using a pulsed laser system we

can minimize the thermal damage of this process

step to the underlying layers.

There has been some research done in the field

of laser induced epitaxy [7]. However, a

comprehensive study on the subject is still

missing. Here, we studied pulsed laser induced

epitaxy process of silicon using a seeding wafer

to realize the location- and orientation-control of

the silicon grain. 4 /lm x 4 /lm large grains are

obtained and characterized. The effect of laser

pulse duration, diameter of the openings to seed

layer and the type of the seed wafer have been

investigated to optimize the epitaxy process.

II. Experimental

We start with deposition of 700 nm thick Si02 by

plasma enhanced chemical vapor deposition

(PECVD) on top of a (lOO)-oriented wafer,

which is either bulk or SOL This is done at 350

°C by using tetra-ethy l-ortho-silicate (TEOS) as

precursor. We palOOttern holes with diameters

varying from 0.5 to 2 /lm by dry etching the

Si02. The diameter of the holes is reduced by

deposition of a 500 nm of Si02, followed by

mask-less anisotropic dry etching. The spacers

system is shown in Fig. 4. There are two laser

modules which can perform independently, but

also in combination with a certain delay set by

the pulse generator unit shown in Fig. 3. The

smoothed normalized envelope of several pulse

shapes which can be obtained by this system are

shown in Fig. 5. Each module has 25 ns wide

pulse. By increasing the delay between the two

laser units, we can obtain a pulse width with a

maximum envelope of 100 ns which is shown by

the green line in Fig. 5. Beside changing this

delay, we can also engage the pulse extender

unit which will extend the pulse width of each

unit up to 250 ns for each. This extends the

pulses up to 500 ns wide (FWHM) as shown by

the black dotted line. The substrate temperature

during the crystallization can be raised up to 450

°C. Figure 5 shows the smoothed normalized

envelope of the pulse intensities.

The thickness of the 500 nm underlying TEOS

layer is optimized for the minimum reflectance.

Thus variations due to exposure energy

fluctuations must be minimized. Figure 3 shows

the SEM pictures of the holes after etching. Left

has been etched by purely dry-etching, while the

right sample has been etched partly dry with a

wet landing step. The bright ring around the

opening is a measure for the slope of the oxide

sidewall, knowing that the diameter of the

patterned holes were initially equal after the

photo resist patterning. The angle of the side

wall varies from 65° to 84° with straight forward

geometric calculations. The focus of this paper

is the results of the seeding holes with 84 °

angle.

III. Simulation

We use two different simulation methods based

on finite element method (FEM) technique for

predicting the thermal profile and/or the tracking

the melt front. For fast predictions and

comparison, we use the enthalpy method

including the latent heat. For more precise

simulations we use the comprehensive phase­

field approach which enable us to track the melt­

and solidification front. For the enthalpy

method, thermal characteristics of each layer e.g.

heat capacity, thermal conductance and density

is used. Also laser related parameters

like reflection and absorption @308 nm is

considered. Phase-field approach uses all those

parameters accompanied by data about the

temperature dependent melt velocity and surface

tension. For more detail about this simulation

see [8].

(b)

Figure 2: Schematics of Pulsed laser induced epitaxy process with bulk wafer seeding (a), and SOl wafer seeding (b).

Figure 3: Two examples of dry-etching (left) and wet­dry-etching combination and its effects on the oxide sidewall slope.

w. X-Y-Z1iIIIF f

Figure 4: Schematics ofXeCI pulsed excimer laser system

• 25 ns single pulse --·double pulse

double pulse with 2/8 pulse extender -double pulse with 4/8 pulse extender --·double pulse with full pulse extender

6 -7

x10

Figure 5: Measured pulse shapes with the excimer

laser system.

------ -- -- ---. 1600 c-SI meillemp_ -",'/-

;;< .. --, -"f 1400 /.,,, ....... : ... ..' � 1200 ........ ,,;:/.' � , ..... E 1000 --- 1 - - SUlk Wale' I 8OOL�_-=-=-- S=O=1 w=af =e ':J

0.6 0.8 I 12 Fluence (J/cm2( 1.4

� 1400 - - - -a:srmeTftomp�------ ----., �1300 e 8-�1200 11w"-______ -'

0.05 0.06 0.07 0.08 Fluence (J/cm2(

Figure 6: Maximum temperature as a function of laser energy density at a-Si/c-Si interface (left) and a­Si surface and (right)_ This is done for the bulk wafer substrate with an elevated temperature of 450°C and a pulse width of 70 ns_

IV. Results and Discussion

With an absorption coefficient of le8 m-I, a-Si

absorbs the largest amount of laser light in its

first 10 nm and melts. This thin layer of silicon

then acts as the heat source for the underlying

layers. As the melting continues to sink deeper

in the a-Si layer, the c-Si seeding layer is

reached by the melt front. Since the melting

temperature of the c-Si is almost 200 °C higher

than a-Si, it is not always melted by just coming

in contact by the molten-Si front. In case the c­

Si interface is not reached, the seed for

solidification will be fine grain polysilicon. Thus

the crystallized layer will have multiple

crystallographic orientations which means that

the epitaxial growth is not succeeded. We define

the onset of epitaxial growth to be a the laser

energy density by which the melting

temperature is obtained at the interface of

seeding c-Si and a-Si. This results in a

successful epitaxy process in which, the

crystallized a-Si layer will have the same

crystallographic orientation as the c-Si of the

seeding layer. In Fig. 6, simulated temperature

behavior at specific points in both SOl and bulk

wafer seeding structures have been plotted

against the increasing laser fluence. A substrate

temperature of 450 °C and a pulse width of 70

ns were considered in the phase-field simulation.

The schematic of each structure is shown in Fig.

2. Left figure shows the onset of epitaxial

growth with both SOl and bulk seed layer

against increasing laser energy density. The

structure with SOl wafer seeding reaches the

onset of epitaxial growth with approximately

100 [mJ/cm2] less energy density than that of

the bulk, which means that one needs less laser

energy to have an epitaxial growth for this

structure. The SOl wafer contains less silicon at

the seeding area. The high thermal conductivity

of Si and low thermal conductivity of Si02 cause

the SOl case to have a better heat confinement.

The right figure indicates the minimum laser

energy density needed to melt the a-Si on the

surface. It is rouphly the same for both structure

since it is mainly surface dependent.

A simple enthalpy simulation using two pulses

of 25 ns and 250 ns produces Fig. 7. Here the

temperature history is shown for several

coordinates in the structure. The X coordinate

stands for the lateral position in [m], from the

center of the epitaxy hole and y for the depth in

the structure. The schematic of each structure is

shown in Fig. 2. We observe that while the c­

Si/a-Si interface reach the same temperature in

shortly after one another, the maximum surface

temperature is decreased by 500 °C using the

longer pulse. The ablation temperature of silicon

is assumed to be roughly around its boiling

temperature of 2600 K. Although this

temperature is not reached in this simulation, the

surface temperature of both structures can be

relatively compared. It was found that the

ablation threshold is increased due to more

uniform temperature profile in case of long pulse

causing more energy to be given to the structure,

resulting in a deeper melt. By using shorter

pulses, the heating is more abrupt, causing the

maximum surface temperature reach the ablation

temperature.

The experimental counter parts of these results

are summarized in Table I. The minimum

energy densities needed for epitaxial growth and

Temperature [K) 2000 �����������

1800

g1600

<II 3 1400

� �1200 E <II f--1000

800

-(4e-8,0) - (4e-8, -8e-8) -(4e-8, - 2 . S e - 7) -(4e-8, -7e-7)

6000 0.5 2 2 1 1.5 .5 3 3.5 4 4.5 5

Time x10-7

Temperature [K) 1 4 00 .-����������

1300

1200 Q �1100 :::> � 1000 <II c. E 900 <II f--

800

700 ILL-._-

6000 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Time x10-7

Figure 7: Simulated temperature history, for two

different pulse widths of 25 ns (left) and 250 ns

(right), with the same energy density of 1.4 mJ/cm2.

Bulk seeding was considered in this calculation The

depicted coordinates are in [m]. X value stands for

the lateral position, zero begin the center of the

epitaxy hole, y for the depth in the structure

to reach ablation threshold are shown. Process

window is defined to be the energy density

difference between the onset of epitaxy and the

ablation threshold. Though ablation is not a very

abrupt happening at die level. By comparing the

onset of epitaxy between the short and long

pulses, it is obvious that the process window is

increased by using longer pulses. This is valid

for both SOl and bulk wafer seeding. This can

be justified by the more uniform temperature

profile in case of longer pulse, which is due to

the more uniform heat flow in to the system. We

observe that while using the shorter pulses, SOl

wafer still leads to successful epitaxy. The onset

of epitaxy is so close to ablation threshold of the

bulk wafer seeding structure, that no large area

epitaxy is observed. However, longer pulse

responds better with bulk wafer. The increase in

process window is larger in case of bulk wafer

seeding. Since heat sink of this structure is better

than the SOl wafer, the flux towards the heat

sink is also larger in magnitude. With other

words, once the surface is not ablated which

happens in case of short pulses, the surface

remains cooler and allows more heat to flow into

the system without reaching ablation

threshold. Silicon grains with 4 Ilm x 4 Ilm area

were obtained on top of the holes. Arrays of

Si02 openings of 84 0 sidewall with 4 Ilm pitch

were designed. Areas as large as 2.5 mm x 1.7

mm, which is the laser beam spot size, were

crystallized. By EBSD measurement, the

orientations of these grains have been

investigated. Preferred (l00) orientation have

been observed for samples of both bulk and SOl

seeding layers. In case of 250 ns pulse, energy

density for crystallization is less than 1500

mJ/cm2 for a SOl seeding wafer and 1600 mJ/cm

2 for

bulk wafer seeding, we do not melt the c-Si seed

layer. Thus the seed for nucleation consists of

several orientations.

Figure 8 shows the SEM image of an array of

grains crystallized by 1.4 mJ/cm2 laser energy

density. Since this energy is lower than onset of

epitaxial growth, the results is an unsuccessful

epitaxy. The red lines are drawn to emphasize

the contrasts that exist within each large grain,

which are indication for existence of several

sub-grains. Figure 9 shows a EBSD

measurement of 25 Ilm x 25 Ilm large array of

grains, similar to SEM picture of Fig. 8. It

indicates that many crystallographic orientations

exist in the surface of the crystallized layer. In

Fig. 10, the SEM image of an array of grains is

shown, which are crystallized by a 250 ns pulse

with an energy densitiy of 2 J/cm2• This energy is

higher than values mentioned as onset of epitaxy

in Table 1. One can observe that the epitaxy in

case of bulk wafer seeding appears less

defective. This could be due to the fact that

crystalline quality of bulk wafer is generally

higher than a SOl wafer. Figure 11 shows a

EBSD measurement of 25 /lm x 25 /lm large

grain array, similar to SEM picture of Fig. 10. It

indicates that the (l00) is the main

crystallographic orientation that exists in the

surface of the crystallized layer. In EBSD and

pole figure, the existence of four secondary sub­

grains is visible. Figure 12 indicates the size and

position of these sub-grains. A TEM cross­

sectional image of an epitaxy process with a

laser fluence of 2 J/cm2 is shown in Fig. 13. In

this figure, we can see a successful epitaxy

process, but also the formation of the sub-grains

due to twin formation originated at the oxide

sidewall.

Table 1: The onset of ablation and epitaxial growth shown for the shortest and longest pulse duration, for different substrate types. All energies have [mJ/cm2] unit. The stepping for the energy density increase of the laser has been 50 [mJ/cm2]. Substrate temperature was raised to 450 °e.

[0011 1 1 1

001 101

Figure 9: EBSD mapping (left) and pole figure (right) of an epitaxially grown sample with (100) bulk wafer seeding with a laser fluence of laser fluence of 1.4 J/cm2. No crystallographic orientation-control is achieved.

Figure 10: Successful epitaxial process for bulk (left) and SOl (right) wafer with (100) orientation by a laser fluence of 2 J/cm2 which appears to be sufficient.

,------,--------------,------------------, Pulse 25 [ns] 250 [ns]

width Ablation Epitaxy Ablation Epitaxy

Seed type [001] SOl 1500 1400 2000 1500 1 1 1 Bulk 1550 2200 1600

Figure 11: EBSD mapping (left) and pole figure ........... iooiiiioi----......

...J(right) of an epitaxially grown sample with ( 100) bulk wafer seeding. Laser fluence of 1600 mJ/cm2 is used. Figure 8: Unsuccessful epitaxial process for bulk

(left) and SOl (right) wafer with (100) orientation by a laser fluence of 1.4 J/cm2 which appears to be insufficient.

Figure 12: AFM (left) and surface TEM image (right) of epitaxially grown single cry stalls showing the existance of four sub-grains.

Figure 13: TEM a cross-sectional image of a epitaxy process with a laser fluence of 2 J/cm2• Formation of facets at oxide sidewalls is shown.

V. Conclusion

Orientation- and location-controlled grains as

large as 4 J.lm x 4 J.lm were obtained by the

pulsed excimer laser induced epitaxy process.

Longer pulse durations result in deeper melt

depths and higher surface ablation threshold.

Seeding from a SOl wafer seems to require less

laser energy density due to better heat

confinement of the structure, due to thinner

seeding silicon and the low thermal conductivity

of underlying buried oxide layer. However, by

increasing the pulse duration, bulk wafer has a

larger increase in process window and more

suitable to be used as seeding layer for epitaxy.

The quality of the crystallized layer appears to

be better in case of bulk wafer which can be

explained by the better quality silicon. The oxide

sidewall angle can be varied by changing the

etching type. However, the defect density

remained mostly equal for both sidewall angels.

This study shows successful location- and

orientation-controlled large 4 J.lm x 4 J.lm silicon

grains, with (100) orientation, which can be used

for transistor layer of the building blocks for

high quality 3D IC, applicable for e.g. SRAMs

and SoCs.

Acknowledgment

The authors would like to thank the ICP

members and staff of DIMES research center for

their support during the fabrication of these

devices and the Dutch Technology Foundation

STW for their financial support.

References

[I] International Technology Roadmap for Semiconductors 2009 edition, Process Integration, Devices, and Structures, pp. 5. [2] K. C. Saraswat and F. Mohammadi, "Effect of Interconnection Scaling on Time Delay of V LSI Circuits", IEEE Transaction Electron Devices, Vol. ED-29, pp. 645-650. ( 1982) [3] M. Koyanagi et aI., "Future System-on-Silicon LSI Chips"IEEE Micro, Vol. 18, NO. 4, pp.17-22. ( 1998) [4] P. C. van der Wilt, B. D. van Dijk, G. 1. Bertens, R. Ishihara, and C. I. M. Beenakker, Appl. Phys. Lett. 79, pp. 18 19. (2001) [5] R. Ishihara et aI., "Single-grain Si TFTs with ECR­PECV D Gate Si02", IEEE Transactions on Electron Devices, Vol. 51, NO. 3, pp.500-502. (2004) [6] V. Rana et aI, "High Performance Single Grain Si TFTs inside a Location-Controlled Grain by J.l­Czochraski Process with Capping Layer", Proceedings of International Electron Devices Meeting 2006, pp. 37-3. [7] Yong-Hoon Son, "Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity", Proceedings of International Electron Devices Meeting 2007, pp. 5B-3. [8] M. R. Tajari Mofrad, A. La Magna, R. Ishihara, H. Ming, K. Beenakker, "A three-dimensional phase­field simulation of pulsed laser induced epitaxial growth of silicon", Journal of Optoelectronics and Advanced Materials, Vol. 12, NO. 3, pp.lOI-706. (2010)