A Digitally-Assisted

Electrothermal Frequency-Locked Loop

S.M.Kashmiri and K.A.A.MakinwaElectronic Instrumentation Laboratory / DIMES

Delft University of TechnologyDelft, The Netherlands

E-mail: S.M.Kashmiri@TUDelft .NL

(a)

Figure I. The analog FLL of (I], (a), and the digitally-assisted FLL, (b).

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II. SYSTEM-LEVEL DESIGN

In Fig. 1a, a simplified block diagram of an analog FLL of[1] is shown. The YCO drives the ETF as well as asynchronous demodulator, which detects the phase of theETF's output signal. The output of the synchronousdemodulator is then integrated by an analog filter, whichdrives the YCO. The loop locks when the demodulator 's DCoutput is zero, corresponding to a YCO frequency fvco = .190atwhich the phase shift of the ETF's near-sinusoidal output isabout 90°. The FLL's phase-frequency characteristic is thuslocked to that of the ETF.

A block diagram of the proposed digitally-assistedelectrothermal FLL is shown in Fig. 1b. Besides a YCO andan ETF, it consists of a phase domain M: modulator(PDM:M), a DAC, and a digital filter. The YCO drives theETF, whose phase shift is then digitized by the PDM:M [5,6].The latter's bitstream output is then compared with a phasereference of 90°, and the resulting error signal is then

Hz were achieved with the help of a large (1 IlF) off-chipcapacitor. In the digitally-assisted FLL described here, thenoise bandwidth is defined by a digital filter, resulting in asolution that is more amenable to CMOS integration.

In the next section, the system-level design of a digitally­assisted electrothermal FLL is described. Section III providesan overview of the circuit, while the measurement results arepresented in section IY. The paper ends with conclusions.

I. INTRODUCTION

An integrated electrothermal filter (ETF) consists of aheater and a temperature sensor, e.g. a thermopile, realized inclose proximity on the same silicon substrate. AC powerdissipation in the heater causes an AC temperature gradient inthe substrate, which is sensed by the thermopile and convertedinto an electrical signal. Due to the substrate' s thermal inertia,the phase of this signal lags that of the heater power [1 - 6]. Ata given frequency, the amount of phase shift will bedetermined by the ETF's geometry and by the thermaldiffusivity of bulk silicon. Since the latter is well defined, theaccuracy of this phase shift will be mainly limited bylithographic inaccuracy [1, 4].

In [1-3], the output frequency of an electrothermal FLLwas locked to the phase shift of an ETF. Due to thetemperature dependence of the thermal diffusivity of silicon,the resulting frequency is proportional to r 1.8 [1, 7], where Tis the absolute temperature. The result is a temperature sensorwith a robust output signal, which can be easily interfaced to amicroprocessor. The FLL in [1] achieved an untrimmedtemperature sensing inaccuracy of ±0.5 °C (Jo) from -40°C to105°C. This is in the same order of magnitude as theinaccuracy of untrimmed band-gap temperature sensors [8].

Silicon is a good thermal conductor, and so the output ofan ETF is quite small (sub-millivolt). Since this signal alsoconsists of thermal noise, the noise bandwidth of anelectrothermal FLL must be very low (sub-Hz) in order toachieve reasonable temperature sensing resolution. In [1], aresolution of about 0.04 °C (rms) and a noise bandwidth of 0.5

Abstract-s- A digitally-assisted electrothermal frequency-lockedloop (FLL) is presented, whose output frequency is determinedby the temperature-dependent thermal diffusiv ity of bulksilicon. In contrast to previous work, its noise bandwidth isdefined by a digital, rather than an analog, filter . This obviatesthe need for external capacitors, thus enabling full CMOSintegration. Without trimming, an implementation in a O.7JlmCMOS process achieves an output frequency spread of about±O.3% (3u) from -55 DC to 125 DC. This corresponds to atemperature sensing inaccuracy of about ±O.7 DC (3u).

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Figure 2. A detailed block-diagram of the digitally-assisted electrothermal FLL.

integrated by the digital filter and fed back, via a DAC, to theYCO. Once more, the feedback forces the YCO to operate atfvco = 190. The PD~~M, the digital filter, and the DAC aresampled at the same frequency Is, which is a sub-multiple offvco. The result is a self-referenced system, whose noisebandwidth is determined by the digital filter, and so can bealmost arbitrarily low.

A detailed block diagram of the digitally-assisted FLL isshown in Fig. 2. Here the ETF is driven at a sub-multiple of[vco denoted by Jdrive' Its output is then converted into a currentby a wideband transconductor gm in the front-end of thePD~~M [5, 6]. An embedded chopper demodulator detects thephase of this current by multiplying it by one of two phasereferences, Jdrive(~O) or Jdrive<~l)' which are ±45° phase-shiftedversions of Jdrive. The resulting phase-difference current isintegrated by the modulator's loop filter Cint• The modulator'sbitstream output is then a digital representation of the ETF'sphase shift.

The signals Jdrive.Jdrive(~o), Jdrive(~l), and Is are all derivedfromfvco. In order to implement ±45° phase references with a50% duty cycle,jvco = 16Jdrive' The FLL's 90° phase referenceis a square-wave with a frequency of fs/2. This is subtractedfrom the PD~~M bitstream output and the resulting 3-levelsignal is integrated by a 12-bit up/down counter. When theresult is zero, the XOR gate disables the counter; otherwise,the counter's state is appropriately incremented ordecremented. The counter's output is then fed to a 12-bitdigitally-controlled oscillator (DCa), consisting of a 12-bitDAC and a YCO.

The noise bandwidth of the system is determined by thelength of the counter and the value ofIs. For a 12-bit counterandj, =Jdrivel64, the FLL's noise bandwidth is 0.4 Hz (at roomtemperature). This ensures sufficient suppression of the ETF'swide-band noise and the PD~M's quantization noise.

III. CIRCUIT D ESIGN

The main analog blocks of the proposed digitally-assistedelectrothermal FLL are the ETF, the PD~M and the 12-bitDCa. The first two have been extensively described in [6] andso are only summarized here. The DCa consists of a 12-bitDAC that drives a relaxation oscillator.

A. PD~IM

The function of the PD~~M is to accurately digitize theETF's phase shift. Potential sources of error are excesselectrical phase shift and residual offset.

The ETF was designed to have an 190 of about 100 kHz atroom temperature and a lithography-limited phase spread of0.12° (Jc) in a 0.711m process [3]. This leads to a temperaturesensing inaccuracy of 0.5 "C over the military temperaturerange. The PD~M consists of a transconductor gm, and anembedded chopper demodulator (Fig . 2). The transconductorhas a simulated bandwidth of 115 MHz and contributes lessthan 0.01° of additional phase shift at 100 kHz. Thiscorresponds to an output frequency error of less than 0.04%and an overall temperature sensing inaccuracy of 0.08 "C.Furthermore, errors due to the demodulator's residual offsetare minimized by chopping the entire front-end at Jdrivel8192(not shown in Fig. 2). The combination of the ETF andPD~~M resulted in a temperature sensing inaccuracy of 0.7 "C(Jc) and a resolution of0.05 °C in a bandwidth of 0.5 Hz [6].

B. Relaxation Oscillator

At room temperature, the oscillator's frequency fvcoshould be at 16Jdrive, or about 1.6 MHz. It should also betunable over the range 800 kHz to 3.2 MHz, whichcorresponds to the expected variation of the FLL's outputfrequency over the military temperature range (-55°C to 125"C), The oscillator's most critical specification is its jitter, asthis is a major component of the FLL's output jitter and, thus,limits the FLL's temperature sensing resolution.

The relaxation oscillator [9], and its transient waveformsare shown in Fig. 3. Depending on the state of the latch, eithercapacitor C1 or Cz is charged to Vdd by transistor M 1 or M3

respectively, while the other capacitor is gradually dischargedby Ire! via M, or M4• Ire! is provided by the cascode currentmirror including MS-8• When the voltage over the capacitorsreaches Vrefi comparators Comp.j feed the latch with theappropriate set or reset pulses, which then toggles after a shortdelay, td ~ 100 ns. The period of oscillation is then:

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In which C = C1= C2 = I pF. For Iref = 20 /lA, Vdd = 5 V, andVref = 2.25 V, the center frequency is 2.6 MHz. To vary thisfrequency, the reference current is varied by pushing orpulling a current Illm e into the current mirror (drain of M7) .

This current is provided by the DAC, and lies between ± 18/lA, corresponding to a tuning range from 350 kHz to 4 MHz.The range is wide enough to accommodate the FLL'sexpected frequency range plus the ±40% variation in centerfrequency due to process and temperature variations.

The cascode transistors M5 and M7 are gain-boosted bytransistors M9 and MIQ. This ensures that the mirror ratio iswell defined despite the voltage excursions on C1,2 and thevariation of Illme. The comparators Comp. j consist of positivefeedback latches with 50 mV of hysteresis, preceded by pre­amplifiers to minimize the effect of their "kickback." In thisoscillator, the main cause ofjitter is the input referred noise ofthe comparators [10, II]. Over process comers andtemperature, their maximum input-referred noise is 140 p.V(rms), which translates to 50 ppm of jitter at an oscillationfrequency of 1.6 MHz [10].

e. 12-Bit DAC

The DAC provides the oscillator's tuning current, 1llme•

Since the FLL's expected accuracy is about 0.25% [1], it wasdecided to design a DCO with a resolution of 0.05% over theFLL's expected frequency range. This requires a 12-bit DAC,whose LSB corresponds to an 800 Hz step infvco.

Since the DAC is in a control loop, it should bemonotonic. Therefore, a segmented architecture (Fig. 4) waschosen in which the 4 MSB 's are implemented by 15 unarycurrent sources, while the 8 LSB's are implemented by an R­2R ladder network [12]. The DAC 's reference current is 1.125/lA, which is copied 15 times by current sources Ma,bl-15 thatare degenerated by resistors with a value of 2R. The outputcurrent of the unary cell is then selected by STHI-15, driven by athermometer code representation of the 4 MSB's. An extracopy of the reference current is copied by Ma,b16 to provide a1.125 /lA reference for the R-2R network (R = 80 kQ). Thiscurrent is divided into binary weighted currents and selected

Figure 4. The l2-bit DAC.

by binary switches SB I-8 driven by the 8 LSB's. The outputcurrents of the unary and binary sections are added in adifferential to single ended current buffer, CB I and result inthe oscillator's tuning current 1llme•

For a monotonic characteristic, the matching between thereference current sources Ma,b16 and the unary sources shouldbe better than 8-bits (0.4%). Therefore, the current sourceswere carefully laid out in a common centroid manner. The R­2R network resistors were also laid out in close proximity tothe degeneration resistors. The input-referred offset of CB Iproduces an offset current on the R-2R network, which shouldbe less than the current corresponding to one LSB. Thistranslates to a worst-case input referred offset of2 mY, whichwas targeted by proper sizing and careful layout.

IV. M EAS UREMENT R ESULTS

The critical components of the proposed digitally-assistedelectrothermal FLL have been realized in a standard 0.7/lmCMOS process. The chip (Fig. 5) has a die area of 4 mrrr'. TheETF dissipates 2.5 mW, while the PDLU:M and the 12-bitDCO together dissipate 5 mW from a 5 V supply. Forflexibility, the frequency divider and the up/down counterwere realized in an FPGA.

Figure 5. Chip Photo .

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expected 1IT 1.8 dependency of ./drive (Fig. 7). The spread in theFLL's output frequency is about 0.3% (30') (Fig. 8a) from -55°C to 125°C. This corresponds to a temperature measurementinaccuracy of about 0.7 °C (30') (Fig. 8b). This level ofaccuracy is comparable to that of the analog electrothermalFLL's reported in [1-3]. However, these required the use oflarge external capacitors. The measured 30' frequency spreadis an order of magnitude better than that of the, similarlytemperature dependent, mobility-based frequency referencedescribed in [13].

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v. CONCLS IONS

A digitally-assisted electrothermal frequency-locked loop(FLL) has been implemented. The output frequency of theloop is determined by the temperature dependent thermaldiffusivity of bulk silicon. Compared to prior art, the proposedarchitecture provides a fully integrated solution for such anFLL. An implementation in 0.711m CMOS process achievedan untrimmed device-to-device output frequency spread ofabout ±0.3% (30') from -55 °C to 125 0C. This corresponds to atemperature measurement inaccuracy of about ±0.7 °C (30').

REFERENCES

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Figure 7. Measured characteristic ofthe FLL over temperature. [I ] K.A.A . Makinwa and M.F. Snoe ij, "A CMOS temperature-to­frequency converter with an inaccuracy of ±0.5°C (Jo) from -40 to105°C," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2992 -2997,December 2006 .

[2] C. Zhang and K.AA Mak inwa , " Interface Electronics for a CMOSElectrothermal Frequency-Locked-Loop," IEEE J. Solid -State Circuits,vol. 43, no . 7, pp. 1603-1608, July 2008 .

[3] S. Xia and K.A.A. Mak inwa , "Design of an Optimized ElectrothermalFilter for a Temperature-to-Frequency Converter," Proc . IEEE Senso rs,pp . 1255-1258, October 2007.

[4] C. Zhang and K.A.A. Makinwa, "The effect of substrate dop ing on thebehaviour of a CMOS electrothermal frequency-locked-loop," Digestof Transducers, pp. 2283-2286, June 2007.

(5) C.P.L. van Vroonhoven and K.A.A Makinwa, "A CMOSTemperature-to-Digital Converter with an inaccuracy of ±0.5°C Ocr)from -55 to 125°C," IEEE ISSCC Dig . Tech . Papers, pp. 576-577,February 2008 .

[6] S.M. Kashmiri, S. Xia, and K.A.A Makinwa, "A Temperature-to­Dig ital Converter Based on an Opti mized Electrothermal Filter," to bepublished at IEEE J. Solid -State Circuits, vo l. 44, no . 7, July 2009 .

[7) V. Szekely, "Thermal monitoring of microelectronic structures,"Microelectronics Journal, vo1.25, no . 3, pp. 157- 170, 1994 .

[8] A.L. Aita , M.A. Pertijs , K.A.A Mak inwa, J.H.Huijs ing, "A CMOSSmart Temperature Sensor with a Batch-Calibrated Inaccuracy of±0.25°C (Jo) from -70 to 130°C," IEE E ISSCC Dig. Tech. Papers, pp.342-343, February 2009 .

(9) S.Y. Sun, "An analog I'LL-based clock and data recovery circuit withhigh input j itter tolerance," IEEE 1. Solid-State Circuits, vol. 24, no. 2,pp. 325-330, April 1989 .

[IO] AA Abidi, R.G. Meye r, "Noise in Relaxation Oscillators," IEEE J.Solid-State Circuits, vol. 18, No .6, pp. 794-802, December 1983.

[II] S.LJ. Gierkink, Ed (AJ.M.) van Tuij l, "A Co upled Sawtooth OscillatorCombining Low Jitter with High Control Linearity," IEEE 1. Solid ­State Circuits, vol. 37, no . 6, pp. 702-710, June 2002 .

[12] J.A. Schoeff, "An Inherently Monotonic 12 Bit DAC ," IEEE J . Solid­State Circuits, vol. 14, no . 6, pp . 904-911 , December 1979 .

[13] F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B.Nauta, "A Low-Voltage Mobility-Based Frequency Reference forCrystal-LessULP Rad ios," in Proc . ESSCIRC, pp . 306-309, September2008 .

100 120800 20 40 60Temperature(·C)

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Figure 8. The output frequency error of the FLL measured for 16 samp les(bold lines : ±3crborde rs), (a) , the equ ivalent temperature sens ing inaccuracy

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The measured characteristic of the DCO versus input codeis shown in Fig. 6a. Its tuning range is sufficiently large, andits non-linear characteristic will be compensated for by theFLL. The measured DNL of the DAC is shown in Fig. 6b.Although the DAC is not monotonic (DNL < -1.LSB), this didnot cause problems in practice, because the loop is effectivelydithered by the ETF's thermal noise (about 2 LSBs p-p). TheDAC's LSB corresponds to a DCO step of 890 Hz. Thesampling rate of the PDLU:M and the DCO was set to./drivef32,which corresponds to a noise-bandwidth of 0.4 Hz. The jitterin./drive (= fvco/16) was about 100 Hz (rms), which correspondsto a temperature sensing resolution of 0.015 °C (rms).Measurements on 16 samples from one batch show the

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