Implementation of an IEEE802.11a Transmitter Module for a Reconfigurable System-on-a-Chip Design

Tanya Vladimirova and Jean Robert Paul Surrey Space Centre

Department of Electronic Engineering University of Surrey Guildford GU2 7XH

{j.paul, t.vladimirova}@surrey.ac.uk

AbstractFuture formation flying satellite missions are being developed for a number of applications including Earth observation, space weather monitoring, etc.. To carry out such missions effectively, intersatellite communication and on-board computing systems with adaptable processing capabilities will be needed. The underlying communication parameters and the satellite network topology will vary as a result of orbital dynamics and perturbations. In such a context, a flexible and reconfigurable on-board computing system becomes necessary. In this paper a system-on-a-chip design is proposed comprising of a general purpose processor and an IEEE 802.11 wireless network transceiver core, adapted to the space environment. Initial results on a novel implementation of the IEEE802.11a transmitter module are presented.

1. Introduction

Owing to the increasing in-flight success of very small satellite platforms like CubeSats, satellite missions based on CubeSats [1] are gaining popularity in the research community. This is motivated by the low cost and short development time of these educational satellites, which are built using commercial-off-the-shelf (COTS) components [2]. It is envisaged that CubeSats can be used to develop low cost distributed mission, in which spacecraft will perform cooperative sensing and data processing tasks.

A low Earth orbit (LEO) cluster mission based on a CubeSat design, codenamed S-Cube, is currently being developed at the University of Surrey, which has a long tradition in building small satellites. The mission comprises of three CubeSats used in a master–slave configuration to cooperatively process payload data. Images of the Earth will be collected and processed by all S-Cube satellites; the slave satellites will forward

compressed data to the master satellite via intersatellite links, which will act as a gateway to the ground station.

The S-Cube mission will be used as a testbed for demonstration of advanced terrestrial technologies in space. The targeted demonstration technologies consist of distributed computing processing, inter-satellite links (ISLs) and a reconfigurable system-on-a-chip (SoC) design. To keep costs to a minimum, COTS wireless network technologies, such as IEEE 802.11 will be employed for the ISLs. The satellite wireless data network must take into account the dynamic nature of the LEO environment and the limitations of the IEEE802.11 protocol, which require that it is capable of adapting to a mobile environment and orbit dynamics.

The aim of this research is to develop a COTS ISL controller based on a reconfigurable system-on-a chip that integrates an IEEE 802.11 transceiver, adapted to the space environment, with a high-performance computing system. The resultant low-power and adaptive wireless communication system will be used as part of the distributed computing payload of the S-Cube. The main design focus is on reducing the power consumption and increasing the flexibility of the design to make it suitable for the resource-constrained CubeSat satellite platform.

The paper is organized as follows. Section 2 elaborates on previous work. Section 3 looks at factors that affect communications in space. The system-on-a-chip architecture is presented in section 4. The transmitter and the receiver designs are discussed. In section 5, initial work on the implementation of the transmitter is presented. Section 6 concludes the paper.

2. Related Work

IEEE802.11 is defined at the Medium Access Control (MAC) and Physical (PHY) layers [3].The IEEE802.11 Working Group for wireless local area network (WLAN)

2009 NASA/ESA Conference on Adaptive Hardware and Systems

978-0-7695-3714-6/09 $25.00 © 2009 IEEE

DOI 10.1109/AHS.2009.61

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standards [4] has defined the PHY layer of standards a and g based on the Orthogonal Frequency Division Multiplexing (OFDM) modulation scheme, the hardware implementation of which requires computationally intensive signal processing. Given the sophistication and high performance associated with today’s WLAN, the design of such communication systems demands fast hardware implementations that possess the ability to compute complex signal processing.

The realization of OFDM essentially employs a number of digital signal processing (DSP) techniques. In the past only specially designed Application Specific Integrated Circuit (ASIC) optimised for performance could be used for real-time applications [5]. However, ASICs are not flexible and it is not possible to change values of OFDM parameters once the chip is manufactured. As a result of the lack of flexibility in ASIC OFDM transceivers, they are increasingly being implemented on Field Programmable Gate Arrays (FPGAs). FPGAs can operate at high speeds and have built-in reconfigurable digital signal processing blocks such as multipliers and memory, which makes them a suitable implementation medium for OFDM.

The efficient hardware implementation of the IEEE802.11 wireless protocol is an active area of research [6]. Previous works on the implementation of OFDM on FPGAs have evaluated design trade-offs in terms of power, area, latency and ease of customisation. Several approaches to the implementation of the IEEE802.11 transceiver have been considered including conversion from high-level language representation, e.g. Matlab, using tools such as the Xilinx System Generator and AccelDSP [7, 8, 9]. Their primary goal was the demonstration of OFDM transceiver implementations on FPGAs. High-level languages provide a means for automatic synthesis of signal processing hardware. As a result of that the verification process is greatly simplified, and the development time is reduced. However, the optimization capabilities of such languages are weak. Several pipelined architectures were explored at register transfer level (RTL) in [10, 11]. The aim was to speed up the processing time by adding Random Access Memory (RAM) blocks and memory elements (registers) between the system modules. The intellectual property (IP) cores employed for the Inverse Fourier Transform (IFFT), which is the most demanding block in terms of resources, were based on a continuous stream processing.

Inter-frame timing constraints are introduced at the IEEE 802.11 MAC layer in order to support high data rates. Before a station is allowed to initiate a transmission, it senses the channel to verify whether it is free for a predefined minimum period called Distributed

Inter Frame Space (DIFS). If the channel is busy, a random backoff interval is calculated to determine the waiting time before the sending station tries to access the channel again. DIFS is a function of the Short Inter-Frame Space (SIFS), which is the minimum time between the transmissions of two frames. SIFS introduces very little latency at both the MAC and PHY layers (10 �s).SIFS plays an important role in accessing the transmission medium, as the channel access is a function of SIFS and the air propagation delay. Sidibeh and Vladimirova show in [12] that redefinition of the IEEE 802.11 timing parameters based on the propagation delay and use of smart antennae could significantly extend the IEEE802.11 range in space.

In the literature on IEEE802.11 WLAN implementation, the MAC layer is usually implemented as a hardware/software co-design [13], where a dedicated ASIC microprocessor is used to run control functions, and the memory management unit is implemented in software. Real time operating systems are proposed to manage the memory unit and the upper layers in the protocol stack [13, 14].

Due to drag and other perturbations, ISL distances will vary over time, to the point where communication will no longer be possible. Therefore attitude determination and propulsion systems are necessary to correct the orbits and help the satellites stay in range. As nodes initiate transmission asynchronously, they will have to take into account the high mobility between nodes during communications exchanges. Keeping the channel access timing requirements static will lead to an inefficient channel capacity and a reduction in throughput. The timing requirements must be adaptive to changes in network topology. Thus the need of having a wireless platform that allows reconfigurability is a prerequisite to porting IEEE802.11 in space.

Stamenkovic et al. combine IEEE802.11 IP cores and the SPARC-V8 compliant LEON-2 processor in an SoC ASIC design to implement a high-performance low-power wireless engine [15]. To the best of the authors’ knowledge, an adaptive IEEE wireless communication SoC has not yet been implemented on a reconfigurable FPGA. It is the final goal of this research to design a reconfigurable SoC supporting the IEEE 802.11 wireless network protocol. The software required to support the upper layers of the communication protocol stack and the application code will run on the general purpose LEON-3 processor [16].

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3. Impact of Orbit Dynamics on Communication Parameters

In terrestrial networks, communication links between IEEE802.11 nodes are typically in the range of hundreds of meters. In contrast, in space nodes will be at distances in the order of hundreds of kilometres. This presents a set of new challenges with regard to the range, power and computation time. A link budget was devised to estimate the communication range achievable with the same power restrictions as in IEEE802.11 terrestrial communications. Assuming that smart antennae are used to extend the range of ISLs, simulations with the STK software package [17] show that a smart antenna transmitter with a gain of16 dB, an EIRP of 16 dB and a data rate of 2 Mbps, gives the bit error rate (BER) results presented in Table .1

Table 1: BER as a function of ISL range

ISL Range (km)

Eb/No

BER

2,325-2,755 5.5 4.64 x 10-42,001-2,300 7.42 5.88 x 10-51,000-2,000 12.5 2.87 x 10-7400-1,000 17.5 1.6 x 10-9

If the IEEE802.11 standard is used for inter-satellite communication in satellite networks, the power would be constrained to 1 W and the maximum BER to 1 x 10-6. As seen in Table 1, conforming to the maximum power of 1 W in IEEE802.11 communications would severely limit the range. Other factors inherent to the standard’s functionality also limit the range, for example, the

computation of timing parameters at the physical layer. In terrestrial networks for each packet sent, the time that the sending node should wait for before deciding that packet is lost, is prescribed to as 1 �s. In LEO, propagation delays are variable and significantly higher (in the order of milliseconds). Therefore, a packet could be considered lost before it reaches its destination if the terrestrial IEEE802.11 protocol is applied for ISLs in LEO constellations in its original form.

The implementation of IEEE802.11 for space applications needs to deal with dynamically changing communication parameters and variable propagation delays. This presents difficulties at all layers of the standard’s protocol stack. To achieve efficient intersatellite communication, the IEEE802.11 standard needs to be adapted to the dynamic nature of the space domain. In addition, the limited visibility between the master and the ground station requires the payload data, i.e. the compressed images, to be available by a certain real-time deadline, so that they are ready for transmission before the master satellite passes over the ground station.

All the factors mentioned above call for satellites with adaptive and fast processing capabilities on board. Consequently, the proposed SoC design employs an adaptive IEEE802.11a transceiver and its implementation is targeted at a reconfigurable FPGA device allowing fast processing.

4. System Level Design Overview

In CubeSats, on-board computing is carried out with a set of microcontrollers to manage the various bus subsystems. The on-board microcontrollers can be replaced by a unified SoC-based design with the

LEON-3Processor

JTAGdebug Link

AHBController

UARTdebug Link

IEEE802.11 MAC and baseband PHY

TransceiverEthernet

Memory Controller

AHB /APB Bridge

UART Timers I/O port

PROM I/O SDRAM

External Memory

AHB

APB

DMAController

Image Compression

Core

Figure 1: Block diagram of the system-on-a-chip on-board controller

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subsystems being connected via a COTS bus. To reduce the risk of a failure in the S-Cube design, the demonstration technologies are considered as payloads. The high performance computing payload will house a reconfigurable SoC implemented in a Xilinx Virtex 5 FPGA as it is of importance for the SoC to be easily adaptable to future needs. The SoC architecture is structured as a plug & play configuration of IP cores that provides reliability and versatility to the design.

The SoC block-diagram is shown in Figure 1. The main IP cores are as follows:

� LEON-3 processor � Memory controller and error detection and

correction (EDAC) unit � I/O including JTAG, I2C and UARTs � Custom-built wireless transceiver core based on

IEEE802.11� Custom-built lossless image compression core

compliant with the Consultative Committee for Space Data Systems (CCSDS) recommendation

LEON-3 is a VHDL based SPARC V8 compliant soft processor core. It is a highly configurable general purpose processor and can be customized to suit the user’s application [16]. The main components are the processing unit, memory controller, separate instruction and data caches, 16-bit I/O ports, debug support unit (DSU) and on-chip peripherals. The AMBA Advanced High Speed Bus (AHB) connects high performance modules to each other and to the master that can request access to other slaves and the memory controller (see Figure 1). The APB is a slower data bus that provides access to peripherals with a lower data rate and is in a slave configuration. Just like the AHB, devices are connected on the APB by a plug–and-play method. The LEON-3 acts as the AHB master to the IEEE802.11 transceiver. The IEEE80211 transceiver IP core will include a slave AHB interface to communicate with LEON3.

To provide this new wireless networking capability to the SoC, additional functionalities such as middleware for the implementation of protocols at different layers will be required. This due to the fact that the nodes are allowed to transmit using a random method called Carrier Sense Multiple Access / Collision Avoidance (CSMA/CA) access. The transmitter must be able to store information while trying to access the channel. The transmitter must also be able to access external memories asynchronously; an interrupt handling capabilities will be required to access the SDRAM. The memory controller is programmed though the APB, as a result the IEEE80211 transceiver IP core will also include a slave APB interface for memory access.

The LEON-3 processor will be carrying out the distributed computing tasks over the wireless data network and an operating system will be required to support network standards such as TCP/IP and user applications. It was shown that RTEMS was the most suitable open source real-time operating system for picosatellite missions [18], although it does not provide memory management functions. Since the processor executes application code and processes created by the operating system, which are stored into the memory, a memory driver will be required to allow memory management at software level.

4.1 IEEE802.11 Transmitter Design

To conform to the SITS specifications, speeding up processing delay at both the MAC and Physical layers is necessary. The improvement in processing time leads to increasing clock speed and power consumption, two factors that are conflicting in keeping power consumption low in CubeSats. An investigation of the tradeoffs in power/area/latency performance is necessary. In this section, a novel approach to the implementation of an IEEE802.11 transmitter with pipelining is presented.

This work focuses on the design of the Physical layer of the IEEE802.11a wireless standard, which is based on OFDM. The implementation of the IEEE802.11a transmitter baseband can be partitioned into a set of blocks as shown in Figure 2.

Figure 2: IEEEE802.11a transmitter baseband

In order to remove repeated patterns such as long sequence of zeros or ones, a scrambler is used to randomize the sequence of the inputs. The resulting scrambled sequence is coded with the convolutional encoder Convolutional coding adds redundancy to a sequence of bits by spreading the sequence both in time and space. The sequence of bits is convolved with known polynomials. For each bit, the encoder generates a number bits corresponding to the number of polynomials used. The benefit of spreading the input bits is to allow

Scrambler Conv. Encoder

Interleaver

Modulation Mapper IFFT

CyclicPrefix

Insertion

Window shaping

To Radio

308

enough space for errors to occur; as a result the transmission system provides a means for error correction.. The encoder also uses a shift register and a modulo-2 adder to process every bit.

The interleaver is used to decrease the likelihood of receiving the encoding incorrectly by reallocating adjacent bits to non-adjacent channels.The interleaver permutes the input bits in a prescribed pattern. A challenge in hardware implementation is the conversion of mathematic expressions into hardware description language. Direct translation leads to a large number of multiplexers in the design. The complexities associated with designing the interleaver are numerous. They range from performing modulus numbers that are not multiples of 2 to allocating RAMs with different sizes [10]. The easiest option is to calculate the permutation indexes and store them in a look-up table. Interleaved data are subsequently sent to the modulator.

The role of digital modulation is to map binary information into complex signals. The modulator converts a set of bits to convert into complex numbers representing constellation points. Interleaved data are mapped into real parts, called the In-phase (I) components, and imaginary parts, called Quadrature (Q) components. The great advantage of this method is that the carrier can modulate data independently, then I and Q components are added together to be sent over the same physical medium.

In this design only the lower data rates are of interest, as a result only BPSK and QSPK modulations are considered. The data from the interleaver is serially fed to the constellation mapper, to produce the corresponding I and Q components. The I and Q components are stored in a look-up table (LUT) in the form of 16-bit fixed-point data. The values in the LUTs are already normalized by a k factor. Regardless of the modulation used the OFDM symbol consists of 48 complex numbers.

The role of the mapper is to translate 64 complex numbers into subcarriers. For the mapping an indexing structure made of combinational logic is used to combine 48 complex numbers with 16 complex numbers consisting of 4 pilots and null vectors. The pilots are stored in a LUT and are accessed by matching their indexes with the nth OFDM symbol. Given that the LUT has 127 values, a modulus 127 counter is also used to control indexing.

In OFDM systems, the modulation of the subcarriers is done directly in the frequency domain using complex multiplications. The resulting data are transformed into the time-domain using the Inverse Fast Fourier Transform (IFFT) at the transmitter and transformed back to

frequency-domain using the FFT at the receiver. This means that each point of the IFFT is considered to be a frequency tone. To mitigate time dispersion fading a guard interval equal to the channel impulse is inserted at the beginning of the OFDM symbols. The last 16 samples from the IFFT are appended to the beginning of the OFDM symbol and are called the cyclic prefix (CP). Thus the OFDM symbol is formed of 80 samples of complex numbers.

4.2 IEEE802.11 Receiver Design Considerations

The IEEE802.11 standard has left the receiver specifications to the designer’s own choice. The receiver blocks perform the inverse to their corresponding transmitter blocks. However, two blocks are added to help with the synchronization and the mitigation of channel impairments as shown in Figure 3. The receiver’s added blocks and the Viterbi decoder correspond to a substantial increase in signal processing when compared to the transmitter. This automatically translates to more hardware resources. Two blocks call for particular attention: the synchronizer and the Viterbi decoder.

The synchronizer has several functions; it firstly detects packet preambles. As OFDM is sensitive to time and frequency offsets, it is necessary for the receiver to able to determining the starting position the packets. Packet detection is done by performing autocorrelation or cross-correlation on the short preamble, which has a periodic sequence of samples. The short preamble’s periodicity receiver is a safeguard against false detection. The synchronizer second role is to calculate carrier frequencies offset due to the receiver oscillator and Doppler frequency shift. In most implementations the synchronizer calculates the timing offset before determining the frequency offsets.

The data bit streams from the de-interleaver is decoded using the Viterbi algorithm. Recall that the convolutional encoder is a state machine, and the resulting encoded binary information is a reflection of the encoder state. The role of the Viterbi decoder is to retrace the encoder state transitions given a sequence of bits. The maximum likelihood algorithm is used to trace back the sequence. In most implementations the trace back length’s is set to 35. The decoder has major computation units, the path metric unit and the traceback unit.

The path metric unit is a register that stores accumulated errors between the estimated state and the actual state. A path metric unit is assigned to each of the 2k states possible. The encoder codes are represented by a trellis diagram, which maps the possible state transition for a given input and the time domain. The decoder

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retraces the sequence by eliminating the previous state with the lowest error cost. The traceback unit is a register that stores the surviving state.

Figure 3: IEEE802.11a receiver baseband

In [19] it is shown that the implementation of the synchronizer and the Viterbi decoder account for 70% of the receiver’s power consumption. As a result, low power dissipation components will have to be considered for our design.

5. IEEE802.11 Transmitter Implementation

The design of the OFDM transmitter, described in section 4.1 above, features a novel structure, which is based on pipelining registers placed between the modules to store intermediate data instead of RAM blocks as in the existing designs [10, 11]. In order to minimise the utilization of resources, ROMs are used to store LUT data derived from complex mathematical operations in Matlab, such as the computation of the preambles, interleaver indexes, modulation complex mapping, etc..

Memory blocks in the form of RAMs are omitted from the transmitter top-level design. They are only used inside the IFFT block as the transform needs two dual–port RAMs for data storage between stages. Using registers between the transmitter modules mimics the process of vector manipulation in Matlab. Vectors can be either shifted between modules, or they can be manipulated by unrolling the loops to work on multiple bits in a few clock cycles. The use of vectors stored in registers provides a degree of flexibility not found with RAM storage. If the data require shifting from the RAM to another block it would take a large number of clock cycles depending on the data size. Although FPGAs have a large amount of on-chip memory, the use of registers as storage elements could take away valuable hardware resources that could be used for other applications.

Given the gain in processing time that can be obtained with a pipelined IEEE802.11a transmitter architecture, initially registers were employed as storage to enable the

computation of the OFDM symbols. The amount of the hardware resources needed by the registers as compared to RAM storage was then quantified. It was found that the design with registers as storage elements required considerably more hardware resources when compared to the architectures employed in [10] and [11]. To trim the occupancy area, a method called register binding [20] was applied, in which some of the variables were bounded directly to embedded memory, and others were bounded to registers.

5.1 IFFT Block

For the implementation of the IFFT block, a public domain radix-4 FFT core, written in the hardware description language VHDL, was downloaded from opencores.org [21]. The FFT implementation is configurable to 1024, 256 and 64 points. This VHDL module can be used for both IFFT and FFT operations by just inverting the INV signal. The IFFT collects a burst of data serially, stores 64 complex data samples in block RAMs (BRAMs) and then performs calculations in 240 cycles before it can output the 18-bit values of the 64 transform points. To meet the standard specifications, the IFFT is required to output the 64 transform points in 3.2 µs and the CP should be transmitted for a duration of 0.8 µs. Thus, the 64 transform points and the CP produce an OFDM symbol within a 4 µs time interval. The standard requires the OFDM symbol to be transmitted on the air interface at a clock speed of 20 MHz. If the IFFT core is clocked at the same rate as the OFDM symbol flow, the 320 clock cycles required by the IFFFT core to produce 64 points could be completed in 3.2 µs. As a result, the clock of the IFFT core was set to 80 MHz to produce 64 complex samples during an interval of 3.2 µs. The employed public domain IFFT core does not perform continuous stream processing and therefore it is idle at times, which leads to a reduction in the power consumption.

The selected VHDL IFFT core [21] was functionally verified using the ActiveHDL simulation tool, which employs the same IFFT model. The numerical values produced by the IFFT core were compared against the values generated by the Matlab built-in IFFT macro instruction. The ActiveHDL function that allows VHDL arrays to be ported to Matlab was used to carry out the comparion. It was found that the IP core output matched the Matlab results with accuracy in the region of 10-4,which is satisfactory.

5.2 Implementation Results

As discussed above, the proposed transmitter design is a pipelined architecture exclusively using registers as

Synchronizer FFT ChannelEstimator

De-Mapper De-Modulator

De-Interleaver

ViterbiDecoder

De-Scrambler

To MAC

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storage elements instead of RAM blocks. This is motivated by the need to reduce the computation time in order to achieve a real-time OFDM transmission for the purpose of intersatellite communication. The proposed design will be referred to as Design-2 below. It will be compared with the RAM-based IEEE802.11a transmitter design in [10] and [11], which will be referred to as Design-1.

The two transmitter designs use different IFFT cores. Design-1 uses an IFFT core from Xilinx [22] and Design-2 uses a public domain IP core [21]. The IFFT chosen for the proposed transmitter (Design-2) differs from the Xilinx IFFT core used in [10, 11] as follows. Firstly data is taken in bursts of 64 samples, and the transform computation time is 40 % longer. Secondly the chosen IFFT has no internal pipelining structure to allow continuous streaming.

The transmitter implementation is targeted at the Xilinx Virtex 5 series of FPGA devices, however for the purpose of the performance comparison with published work the design was mapped on the Xilinx Virtex-2 Pro XC2VP30-ff1152 device. The synthesis results for Design-2 gave latency of 10.293 ns and the maximum frequency was found to be 97.157 MHz. This is more than sufficient for the maximum frequency requirement of 80 MHz. Table 2 presents a summary of the resources utilised by the implemented transmitter (Design-2). The required number of slices is 4,738 (3,568 in [10]), an increase of the area usage by 8% when compared to [10]. The number of look-up tables is 5,397, which is 7% less than Design-1 [10].

Table 2: Transmitter resources utilisation

ResourcesUsed

by the Desig

n

Available

on the FPGA

%

Slices 4,738 27,392 34 Slices Flips-Flops 4,490 13,696 16 Number of LUTS 5,397 27,392 19

The dynamic power consumption for Design-2 was estimated with the Xilinx XPower tool to be 150 mW. As there is no published results on power consumption of FPGA-based transmitter designs, it is not possible to compare the performance in terms of power consumption with other implementations. However, if the mapping of variables to the embedded memory is analyzed, we can see that Design-2 uses 3 BRAMS, whereas the design in [11] uses 10 BRAMS. This observation supports favourably the conclusion that the proposed design has lower power consumption [23].

Table 3 presents a comparison between the latency (measured in clock cycles) of the proposed register based transmitter, Design-2, and the RAM-based Design-1 [11] when both IFFT IP cores are used. The number of clock cycles required to produce an OFDM symbol with Design-1 using the Xilinx IFFT IP core is provided in [11]. The number of clock cycles to generate an OFDM symbol with Design-2 using the public domain IFFT IP core is obtained from ModelSim simulation. The performance of both designs when using the “non-native” IFFT IP core is estimated. As it can be seen from Table 3 Design-2 provides a significant speedup in comparison with Design-1 when using both cores.

Table 3: Comparison of OFDM symbol computation latency (clock cycles)

IFFT core

Design

Xilinx IFFT core

[22]

Public domain IFFT core

[21]

Design-1 583 647(estimated)

Design-2 310(estimated) 421

Speedup 273 (45 %) 209 (32 %)

Although the register based design performs significantly faster than the RAM based, this achievement is at the expense of an increase in on-chip resources, whereas the embedded memory approaches are much more economical in terms of chip area.

6. Conclusions

Future formation flying satellite missions are being developed for a number of applications including Earth observation, space weather monitoring, etc.. To carry out such missions effectively, intersatellite communication and on-board computing systems with adaptable processing capabilities will be needed. The underlying communication parameters and the satellite network topology will vary as a result of orbital dynamics and perturbations. In such a context, a flexible and reconfigurable on-board computing system becomes necessary.

In this paper, a reconfigurable system-on-a-chip design is proposed comprising of the general purpose processor, LEON-3, and an IEEE 802.11a wireless network transceiver. The SoC is aimed at implementation on the Xilinx Virtex-5 series of FPGAs to serve as a high-

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performance computing distributed payload of a CubeSat cluster mission.

Using COTS for wireless networks shows that the DSP operations performed in OFDM systems for IEEE802.11 can slow down the final hardware implementation. Initial results on a novel pipelined implementation of the IEEE802.11a transmitter are presented. It is shown that the proposed transmitter could speed up the OFDM data symbol computation time compared with existing designs.

Acknowledgements

This research is sponsored by EPSRC under a doctoral training grant and research grant EP/C546318/1.

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[20] H. Al Atat, I. Ouaiss, ”Register Binding for FPGAs with Embebbed Memory”. Proc. 12th Anuual IEEE Symposium on Field Programmable Computing Machines, 2004, FCCM, 20-23 April 2004, pp. 165-175.

[21] FFT IP core, http://www.opencores.org/cvsweb.shtml/cfft/. Last visited on the 27th February 2009.

[22] Fast Fourier Transform, http://www.xilinx.com/products/ipcenter/FFT.htm

[23] R. Tessier, V. Betz, D. Neto, T. Gopalsamy, ”Power-aware RAM Mapping for FPGA Embedded Memory Blocks”, Proc. 2006 ACM/SIGDA 14th International symposium on FPGAs, February 22-24, 2006, pp. 189-198.

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