A Novel Transconductor with High Linearity

Yaohui Kong, Huazhong YangDepartment of Electronic Engineering, Tsinghua University, Beijing, China

E-mail: kyhgtsinghua.org.cn, yanghzgmail.tsinghua.edu.cn

Abstract-A novel transconductor based on folded cascode local some simulation results are listed. The paper concludes infeedback loop to provide low resistance nodes around source section VI.degeneration resistor is presented. The proposed transconductorachieves high linearity and shows less sensitive to channel length II. PRINCIPLE OF SOURCE DEGENERATION STRUCTUREmodulation and mismatch than traditional topology. This designuses UMC 0.18um CMOS process. Simulation result shows the i iproposed transconductor operates in 1.8V supply voltage and has 0+ O_

a total harmonic distortions (THD) of lower than -80dB with10MHz 1.2Vpyp different input. The power consumption is 1.6mW.

ml M2

I. INTRODUCTION

As the CMOS process entering the nanometer scale, analog Rs

signal processing circuits need to operate in lower and lower VIdsupply voltage to meet the process scaling down.Transconductor is regarded as one of the most important Xbuilding blocks in analog circuits such as Gm-C filter and dataconverter, for the overall linearity is mainly determined by thetransconductor in many systems. Especially in modemrcommunication, the THD of -80dB or even -90dB is oftenrequired. Many techniques have been proposed in literatures to One of the most widely used transconductors is the sourceimprove the linearity performance of CMOS transconductors, degeneration based simple differential-pair operating in saturatewhich include cross coupling of multiple differential pairs [1], region as shown in figure 1. In this circuit, the input differentialsource degeneration [2], body-driven [3], shift level biasing [4] voltage falls to the gate to source voltage of two inputand balance pseudo-differential stages [5]. Due to the inherent transistors and the degeneration resistor which can be describednonlinear of transistor and other influences, in these literatures, bylinearity range of only 40-60dB and input range far below ivd Vgsl +iRs - Vg52power supply are reported. With the high demand of low power Fic gsh S gat (1)applications and rapid reduction of transistor dimensions For the quadratic relraionship of the gate to source voltageachieving higher operating-speed and obtaining higher linearity and drain current in saturate region MOS transistors, somewith reasonable signal level become more challenging for nonlinearity will be introduced to transconductor by t thewo

transconductor circuits. input transistors[9]. The linearity can be improved if most of theSome new techniques have been proposed recently to provide input differential voltage falls to the degeneration resistor [10],

high linearity. New method proposed in [6][7] has achieved which gives us a new sight to reconsider the sourcehigh linearity by adding extra amplifier. But these topologies degeneration structure.constrain the linearity to some given level due to using the lowresistance node with value of only / g, ro,, . Another effective l io+ io- lapproach to improve the linearity uses two resistors and an Rsoperational transconductance amplifier in unity-gain i+ Bufrfeedback[8]. However, using resistors at input terminal makesthis kind of transconductor lack of infinite input resistancerequired by some filter applications. Figure 2. Principle of source degeneration transconductor

In this paper, a new highly linear transconductor with sourcedegeneration is developed in CMOS process. The paper is The principle ofthis structure can be simplified to figure 2,organized as following: section II, the principle of source where the transconductor is to replicate the differential inputdegeneration transconductor is described. The proposed voltage by two voltage buffers to the degeneration resistor andtransconductor is given in section III. In section IV nonidealities the current in degeneration resistor is sensed out by currentand stability issue ofthe transconductor are analyzed. Section V, mirror. So the output current oftransconductor can be given by

This work has been sponsored by National Natural Science Foundation of Chinaunder Grant No.90307016

1-4244-0969-1/07/$25.OO ©C2007 IEEE.

G(vi,~~ ~ ~ ~ ~ ~ ~ ~ IVA -9 v,- IVA VddOl MU

where G is the gain of the buffer, vi+ is the positive inputvoltage, v; is the negative input voltage, and Rs is the pH 2 11*degeneration resister. The voltage buffer used here should have MA8 Vbp2 Vbp2the feature of low output resistance and wide input and output I M

swing. If the output resistance of the voltage buffer is small A

enough, the gain of buffer is more close to 1 which makes allthe voltage fall to Rs and less distortion is produced. So the VbM2performance of source degeneration transconductor is mainly MA5 MA4I MB41 MB5limited by the voltage buffer.

V 0

III. PROPOSED TRANSCONDUCTOR -The output resistance is the precondition that should be met Figure 4. Schematic of proposed transconductor

to ensure high linearity of the transconductor.In present published designs, voltage buffer such as the super The full schematic of transconductor is shown in figure 4.

source follower [11] or flipped voltage follower [12] is used in The low resistance node is made by the single stage foldedsource degeneration transconductor design for its low output cascode feedback loop, thus no compensate capacitor isresistance (about 1/ g rog ). But this level of output resistance required for frequency compensation. MA1/MB1 is the inputcan not meet the high linearity required by OFDM and other transistor. MA3/MB3 and MA2/MB2 together with the currenthigh quality applications. Lower output resistance of voltage mirror build the folded cascode feedback loop. Abovebuffer in source degeneration is needed. mentioned transistors form two voltage buffers around

In order to overcome the aforementioned problem, a lower degeneration resistor. The unity gain voltage followers senseoutput resistance voltage buffer with wide input and output and copy the voltage variation of the input to the node A and Bswing is used in this design. around degeneration resistor. The source couple pair outputThe core of the proposed topology is shown in figure 3. It stage is made of MA2/MB2, MA8/MB8 and tail current mirror

uses a folded cascode structure to booster the gain of extra MA6/MB6. Current is produced around degeneration resistor,amplifier and produces the ultra low output resistance node by then the current variation in MA2/MB2 is sensed and flows tolocal feedback loop. output by the PMOS transistor source couple pair. In this

Vdd differential transconductor, common mode feedback circuitshould be used to stabilize the output node. A compact CMFBblock in [13] is adopted in this design.

out IV. NONIDEALITIES AND STABILITY

M2 A. Channel Length Modulation

E VYb The channel length modulation of input transistor MA1/MB1Low resistance node Ml in 3 is regarded as a main distortion source of present source

FMl degeneration transconductor designs, which makes the Vgs ofinput transistor not hold constantly. The proposedtransconductor can alleviate this lambda effect in MA1/MB1.

12 13r Because MA3/MB3 can provide extra loop gain, which forces

I2 W W I3 the drain node of MA1/MB1 to be low resistance, as a resultless voltage variation is introduced to this node.

Cascode current mirrors are also used in this design to reducethe effect of channel length modulation and then improve the

Figure 3. Core of proposed transconductor linearity.

The output resistance is given by B. Mismatch Problemout 1 (3) Mismatch is a critical problem which should be alwaysro.t`~g.1ro1g.3ro3g.2 concerned in most of analog circuit designs. This

where parameter r and gm1 denote the output resistance and transconductor will be less sensitive to mismatch mainly fromtrancondctorof tansitor 1 repectvely Thi low two reasons. First reason, the current produced in degeneration

Z ~~~~~~~resister flowing to output iS not by current mirror, but by sourceresistance node ensures to obtain higher linearity in source couple pairs. So some mismatches between couple pair will notdegeneratiOn WhiCh iS proved in [7]. seriously alleviate the linearity. Second reason, the mismatch

between input-transistors only introduces a current offset for the source degeneration resistor. The power consumption oflow resistance node of the voltage buffer forcing most of proposed transconductor is 1.6mW.differential input voltage to fall on degeneration resistor. Figure7 is the transconductance of the proposed circuit, by

C. Stability Consideration sweeping Rs in range from 14 kQ to 26 kQ, in steps of 3 kQ.The tunability of this kind transconductor can be seen.Furthermore, the source degeneration resistor can be replaced

v test by transistor working in triode region, and then a flexible tuning9Ib 3 ( rb3 can be realized.

2 _- 10MHz ordinary

I r 1MHz ordinaryM3 1-20 - 10MHz proposed -

Ml;| -20 r-|I A lMHz proposed

1 |13 Vreturn 40-

rbl I i4 0 rb2-8

-100

Figure 5. Open loop analysis of the voltage buffer-120

The voltage buffer in the transconductor is made of feedbackloop, so the stability condition should be satisfied. Figure5 is the 140open loop analysis of the voltage buffer where MI, M2 and M3 0.1 0 0 0 Input0.5t0.6( 07 0.8 0.9 1form a three pole (node 3 is the dominant pole) negativefeedback loop. The loop is broken at the gate of M2, and then Figure 6. Simulated THD of ordinary and proposed transconductorAC test signal is added to test the phrase margin of open loopvoltage buffer. At least 60 degree phase margin which meansthe non-dominant pole to be about twice of gain-bandwidth 100u(GBW) should be ensured. By proper sizing the transistors, thistransconductor can meet the stability condition. Some further 90u 4 -

stability analysis of the voltage buffer will be provided in future 80u _work. PsB 14kOhm

70u

V. SIMULATION RESULTC 60u -4 - -_ - -k

The proposed circuit has been simulated using UMC 0.18umlP6M process. The power supply voltage is 1.8V. Simulation of 0

this transconductor is performed via HSPICE simulator. C

An ordinary transconductor based on super source follower is F/also conducted, for a comparative performance demonstration. 30u-6kOhmThe ordinary transconductor uses the same small transistor 20u _length as the proposed one and is optimized to have a goodTHD performance as the main design criterion. The simulated -1 .8 4.6 4.4 4.2 0 0.2 0.4 0.6 0.8THD against differential input amplitudes and frequencies are Input voltage (V)shown in figure6. In order to reach a wide signal swing, all thetransistors are working in moderate inversion region with VDsat Figure 7. Simulated large signal transconductance of proposed circuitaround lOOmV-120mV to maximize the linear range. Theproposed transconductor circuit shows high linearity at test Figure8 is the simulated IM3 of the transconductor. Twofrequencies. The THD is less than -80dB for all the test sinusoidal tones separated by 1MHz around IOMHz, with totalfrequencies with 1.2V differential Vpp. At the test frequency of amplitude of 0.8 Vpp are applied to test the circuit. The IM31MHz, the transconductor exhibits a THD less than -100dB for shows to be about -75dB.differential input more than 0.8 V_ _.

The performance of proposed transconductor does notdecrease greatly with increasing the frequency. The proposedtransconductor shows to have wider input range than ordinarytransconductor, for there is more voltage headroom around the

transconductor will be used as a critical part of the Gm-C filters20 and other analog circuits.

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