Extensive Reliability Analysis of Tungsten Dot NC Devices Embedded inHfAlO High-k Dielectric under NAND (FN/FN) Operation

Pawan K Singh*, Aneesh Nainani.Department of Electrical Engineering, IIT Bombay, Mumbai, INDIA, PIN-400076

Phone: (91-22-25764481) No. Fax: 91-22-25723677 *Email: pawan@ee.iitb.ac.in (Corresponding author)

Abstract: In this work we present an extensive reliability expected in 40nm and below should have excellentand performance evaluation of Tungsten dot Nanocrystal performance making NC devices a very suitable candidate as(NC) devices under NAND mode of operation. Improvement the alternative for FG devices. Effect of length (L) andin performance and reliability was observed with scaling W width (W) scaling on the NAND performance and reliabilityand L. The use of better high-k processing is proposed to is presented. It is found through experiments that theimprove the reliability. We also propose a numerical memory window increases with W and L scalingsimulation model for NC memory devices using transientcapacitive charging model. The approach is very generic and 2. Fabrication Detailscomputationally less extensive than the previous works. Fabrication details are given in our earlier paper [8], key

steps are mentioned here. After the cleaning steps, 8nm thick1. Introduction HfAlO layer was deposited using atomic layer depositionConventional floating gate flash memory device [1] has been (ALD) technique. This was followed by sputtering of a thinthe dominant NVM technology for many years. The (lnm) Tungsten metal layer. Rapid thermal annealing (RTA)difficulty in scaling the tunnel oxide thickness due to SILC of the sample was performed at 9000C for lOs to form therelated charge loss has forced researchers to look for nanocrystals. Another thick HfAlO film (15nm) was thenalternatives. NC devices with semiconductor dots were the deposited using ALD to form the blocking oxide followedfirst to appear. These structures suffered from low by metal (TaN) gate deposition. This was followed by gateworkfunction and quantum confinement effects which limit patterning, S/D implant and activation, metallization andthe minimum dot size and hence the dot density [2-4]. contact formation. The final structure is shown in Fig 1.Nanocrystal flash memory devices consisting of metal dotsembedded in gate dielectric have emerged as one of the mostpromising candidates [5-7]. Extensive evaluation of metaldots embedded in high-k gate dielectric is currentlyunderway. Achievement of high density and uniformity ofdot size is the most important concern for these devices. WStrong emphasis has been placed in the previous works onimproving the performance of the NC devices by optimizingthe materials and process. In this work we report an HfAIOextensive reliability study of NC devices under scaling. NCdevices have been shown to be promising candidate toreplace FG and can be introduced in the 40nm node. p-SiPerformance and reliability study for such heavily scaleddevices has not been reported yet. Tungsten metal dotsembedded in HfAlO gate dielectric with TaN metal gate waschosen as device structure under analysis. Tungsten has ahigh workfunction (4.6eV), making it a suitable choice fornanocrystal. Also Tungsten is a well known material in thefabrication process as it is used extensively as via plugs and Fig. 1: Schematic of device under investigation in thisas interconnect liner. The use of thick HfAlO film improvesinjection efficiency [3] due to lower barrier and minimizeschrg los du to fil thcns. 3. Results and DiscussionInargethsswor we repor In this section we discuss in detail the experimental resultsperformancrkweresu orts edxdevicestawithauptoL .nm obtained for both NAND (FN/FN) mode of operation. Laterperformance results for scaled devices with upto L=60nm intesconwalodcusaimainmdlthteunder~~~NAN (F/N mod of..operation...Scln a n the section we also discuss a simulation model that weobserved toNDimp e bot eprfopermatinc a lablit A have developed for the simulation of NC dot devices. Thisobservedito modei op sth ispworkato model t model utilizes capacitive coupling and then calculates the

P/mcaactio oeriss .oNC ode in s tudy theec o threshold voltage change (after charge injection) using theP/E cAirnofiarkfocs of NIC diavioia andl stuay1 t1ne eiafiat OIf.scain nueial. Siuato reut vaiat.h Percolation model [9]. Lastly we analyze the reliability ofexeietldt*n hwta prfrac of NCdvie NAND mode of operation and the effect of the use of high-k

kep imrvn wit scln an sue sclddvcsa gate material on the performance ofNC flash devices.

1-4244-101 5-0/07/$25.00 ©C2007 IEEE 197 Proceedings of 14th IPFA 2007,Bangalore,lIndia.

4.4 ......I also improves the available memory window. The device4.2 C PROGRAM +9V were programmed and erased at the same bias for identical4.0 : *_--' +8V times. We propose that the improvement in the performance3.8 : */'A~k-~~ +'7v is due to increase in the percentage of edge dots in the NC

>3.6 *-.-. +6v structure with scaling. The greater effect of W scaling is3.4 . explained through the greater increase in percentage of edge

X 3.2 ./X .< . X *-X+5v - dots withW scaling as compared to L scaling.O 3.0> 2.8 Capacitive Charging Model: While a lot of attempts have

o 2.4 t -_A R-A9v been made to model Nanocrystal (NC) based memories [4,s A

-v A -O0oo -0-iov 10], most of them do not take the inter-dot coupling into( 2.2 0-v v v-lV account. One of the recent studies [11] gives a full quantum

20 E-12V mechanical solution to the problem. Depending on the bias1.8.I . ..........1...1voltage, the electron energy levels and wave functions in a

0 10~1 10° nanocrystal is calculated using a finite element method. ThisTime (s) solution is computationally intensive and unsuitable for a

system having more than a few dots. We present the(a) Capacitive Charging Model, a first comprehensive model for

program/erase dynamics and channel characteristics of these4.0 devices considering the dot-to-dot coupling and transport.

A Floating Gate (FG) device is modeled by determining the3.5 relationship between the FG potential that controls the

A / A channel conductivity and the control gate potential. The33.0 charge in the floating gate is related to the terminalO 0 0 0 0 potentials as:

0. 2.5 0 [Q Q= CC (VF - VC) -CS (VF -VS)

2.0 W -CD(VF -VD)-CB(VF-VB) (1)E0

W= 20ocm z3E

E) 1.5 0 W= 5ocm Where, Q is the charge within the FG, Vc, Vs, VD and VB areA/\ W= 2ocm~ the control gate, source, drain and bulk potentials

1.0 ., ., ., ., ., ., ., ., . respectively and Cc, CS, CD and CB are the capacitance50 60 70 80 90 100 110 120 130 140 150 between FG and control gate, source, drain and bulk region

Channel Length (nm) respectively. Junction and fringe capacitance of the FG are(b) ignored as they are negligible in comparison.

A similar approach can be extended to NC flash if the gate,a) P.EcharacteristicsunderNAsource, drain, bulk and also the dot-to-dot and fringe

operatio.na) Effe/B ofWchaacteriicsundr onAN tcapacitances for each NC dot for a given distribution of NCoperation. b) Effect of W and L scaling on the dt skon qain()cnte ersae savaiabl meoywno. o Cmmr dots iS known. Equation (1) can then be restated as:available memory window of NC memoryX

devices. n

I= Cy(V-L/§) + CG1(V -VG) + CBi(V-VB)+C(V-VD)The devices were programmed using FN program and erase.Typical P/E transients obtained in the experiments are +Csi(Vi - Vs) + CFi(V - aVGi- (1- a)VBi) (2)shown in Fig. 2 (a). As can be seen that increasing the where, Qi is the charge on ith dot and Cij, CGi, CBi, CDi, Csi,programming voltage has a very strong impact on the CFi are the inter-dot, gate, bulk, drain, source and fringethreshold voltage shift. These show excellent P/E capacitance for the ith dot respectively, and Vj, VG, VD, VS, VBcharacteristics of the NC device with very small undererase are the potentials of the jth dot, gate, substrate, drain, sourceand fast erase speeds. VT shift of -2V can be achieved in and substrate respectively. Fringe capacitance cannot be50ms at +9V, whereas complete erasure can be achieved at - ignored as it significant especially for the edge dots. The13V in less than 50ms. A very slight overerase is observed factor a specifies the percentage of the fringe coupling withwhich saturates with increasing erase voltage. Further the gate. As capacitance varies inversely with distance,optimization can result in better program/erase speeds. fringe capacitance is divided among the control gate and the

substrate in the ratio of effective tunnel oxide (t-,) toMemory Window: Effect of W and L scaling on the memory effective control oxide (ta) thickness.window is shown in Fig. 2 (b). It is seen that with L scalingvery significant improvement can be achieved. W scaling

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tox Imax is the maximum of tunneling currents. This methodaC = ensures that the maximum charge updated in each step is

tox + tc (3) less then or equal to one electron in each dot. After eachtime step (Jt), the charges are updated in (5) to obtain an

CAPEM© [12] - A 3D Capacitance extraction tool is used updated set of potentials for each dot. This sequence of stepsfor the calculation of all capacitances listed in (2). Device is repeated till saturation/specified time. Fig. 3 summarizesstructure for simulation is created by placing the cubical the flow of the Capacitive Charging Model.nanocrystal in the gate stack by using a Monte Carlo methodto introduce a 10% variation in the average dot distance. The _capacitances are extracted for each storage node with thegate, substrate and source/drain and neighbouring dots forthe required terminal voltages. Only the nearest neighbors _are considered while calculating the capacitances for lsimplicity. Based on the capacitive coupling, voltage on Initial Charge = 0each node is calculated and field is calculated. Directtunnelling expressions are then used to obtain tunnelling CompLAt [ot Potlcurrents between NCs-substrate and also between the dots.Again, only the nearest neighbours are considered whilecalculating the tunnelling current between the dots. CalcuLae TunneIing CurrerrtsPercolation model [9] is used for threshold voltagecalculation after the charge on each dot has been computed NSfrom the tunneling currents. For a given charge distribution Charge Saturationand with a fixed VG, VS, VD and VB, (2) can be rearranged as: or Time Elapse?

n n eHCom e VT usin PercoWlon Moe(E CU+ CGi + CBi + CDi + Csi+ CFi)V-> Ci V =

Fig. 3: Capacitive charging model flow chart forQ-CG VG-C VB-CDVD-C VS-CFi(C/Gb+(1-aj)V&E) computation of Charge and VT profiles in NC flash

(4) structures.

Writing (4) for each of the dots results in a square matrix in It is observed that the edge dots i.e. near the drain and sourceterms of potentials: and at the side ends of the channel show a higher coupling

with the gate and much higher fringe capacitance values as

CT -C12 -C13 -C14 ........ -C,n VI ,_o compared to dots in the center, its effect is reflected in thecharge distribution on the dots at end of programming with

-C21 CT2 -C23 -C24. -C2n V2 Q2-ga2 edge dots storing 20-25% more charge as compared to theV3 Q3-Q?3 (5) dots in the center (Fig. 4).

After the charge on each dot is computed, threshold voltageof the device is calculated using the Percolation model. Theeffect of greater charging of edge dots is seen in VT, as the

-GI -Gn2 -G3 -G4 ......... -CTm Iv\I \Q-Qgng scaled devices show larger window. The threshold voltagen change qualitatively follows similar trend as the percentage

CTi Z, Cuj + CGi + CBi + CDi + Csi + CFi of edge dots as seen in Fig. 5.where, j i andQFi = CcW& + CB, Vi +Ci VDr +Ci Vs, +CF1(aVcG +(1-a)Va) Endurance: Excellent endurance characteristics of the NCThe potentials obtained are used for the calculation of dot- devices are shown in Fig. 7. The maximum window closurebulk as well as inter-dot tunneling currents (FN and Direct observed is - 0.2V for L= 200nm, while L=60nm deviceTunneling [13]). Again only the nearest neighbors are shows flat endurance characteristics. Note that lower bias isconsidered for inter-dot tunneling. After the inter-dot required to maintain similar cycling window for identicaltunneling currents are obtained for each dot, bulk current P/E time in scaled length devices (more fraction of edgetunneling is added to this to obtain the net current tunneling dots), which results in lower dielectric damage and lowerin/out from a dot. Charge in each dot is updated as: window closure with cycling. However, no impact is

observed for W scaling in the range studied, which does not

_ (1.6x10-19> rule out endurance improvement for deeply scaled W.Qi= Ii .t where .t =- .61 (6) devices (more fraction of edge dots) as expected from

Imax simulation (Fig. 6) and needs experimental verification

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2.0-1.8 *

1.6 -Square: L=60nm1 -Triangle: L=200nm w20 m

\>0 p 1.2 P: +9V1 OOms

>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~-. 1P/Pyce

.W10.1,~ ~ ~ 1 1 1 1

Fig. 6: Endurance characteristics of NC flashFig. 4: Simulated charge stored in the dots after lOOms under NAND operation. Effect of W and Lof programming for L=lOOnm, W=lOOnm device variation is shown. L scaling is found to improve

endurance significantly but no effect ofW scalingon endurance is seen.

70 70

65 L i*\ Percent of Edge Dots60 z \-{I-VT H60 2.5..'°). 55 2.01 5|

~~~50 50 1~~~~~~~0 .5

L 45 * 1.00 P:VG=+9Va

° 40 -< H4O 0.51 E:VG=12V@, 35 1:L=GOnm,W=3Onm *\ >. 0.0.°PX3L2:L=60nm,W=100nm \ k 30 >M 0.5 -0-Virgin

0.30~~~~~~~~~~~~~.

3:L=100nm, W=100nm *U * -1.0F -0-- After10K Cycles-l25 4: L=100nm, W=200nmlr20 Lengtt 20 -1.5p 3 40 12 3 4 5 1 10 l

Device Number -2.0 c 1-2.5 ' |

Fig. 5: Simulation Results for memory 0.01 0.1 1improvement under NAND scheme. As the Time (s)percentage of edge dots increases the calculatedVT also increases. Fig. 7: Effect of cycling on the Program and

Erase speeds of W/Ls2mm/200nm devices

.The P/E speed before and after cycling are compared for a under NAND operation.W/L =2Oocm/200nm device in Fig. 7. Very smalldegradation is observed in both program and erase speeds.Even though small window closure of O.15V was observed Retention: Retention results for NC devices under NANDfor this device during cycling, it was found to not operation are shown in Fig 8. It is observed that W scalingsignificantly degrade the P/E speeds. Slight increase in the greatly improved the retention, while L scaling caused slighterase saturation VT was observed after cycling, arising due degradation. Also, device retention did not degrade muchto cycling induced permanent charge storage in the gate with cycling and the observed bad retention characteristicsdielectric. are because of poor virgin device retention (not shown).

Trap assisted tunnelling induced charge loss due to leakyhigh-k gate dielectric results in poor retention for virgindevices. Degradation of gate dielectric due to cycling furtherdegrades retention. Improvement in high-k deposition shouldimprove the retention reliability. Further improvements are

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expected for more W scaled devices and needs to be Acknowledgementsexperimentally verified. The authors would like to acknowledge the help of Dr.

Santanu Kumar Samanta from Cypress Semiconductors,0.0 , Bangalore, India for helping in the fabrication of the devices.

. L=60nm We would also like to thank Prof. Won Jong Yoo,-0.2 Sungkyunkwan University, Korea and Prof. Souvik

Mahapatra, IIT Bombay for their valuable suggestion for thework.

> -0 4 0 X °0°0 \z-0-00SReferences`-0.6 - v o [1] P. Cappelletti et al, "Flash Memories", Kluwer> * ^\ \o4Academic Publishers, Boston, 1999.

'Square: W=2°m -00 [2] J D Blauwe, "A novel aerosol nanocrystal floating gate-0.8 -Circle: W=5'cm - device for nonvolatile memory application", IEDM

Triangle: W=20cm Tech. Dig 2000, pp. 683-686.

-1.0 ... ...... . [3] Jing-Hao Chen et al, "Nonvolatile Flash Memory Device102 103 104 Using Ge Nanocrystals Embedded in HfAlO High-k

_____________________________________ Tunneling and Control Oxides: Device Fabrication and0.0 I . I Electrical Performance", IEEE Trans on ElectronW=20o4l Square: L= 60nm Devices, 2004, pp. 1840-1848.

-0.2 - Triangle: L= 200nm [4] Min She, Tsu-Jae King, "Impact of crystal size andtunnel dielectric on semiconductor nanocrystal memory

-0.4 performance", IEEE Trans on Electron Devices, Vol.0[{\A ] 50, pp. 1934 -1940, Sept. 2003.

-0.6 ^ , 1 [5] Z. Liu et al, "Metal Nanocrystal Memories Part I:>-0.6- Device Design and Fabrication", IEEE Trans on.L0 z .Electron Devices, 2002, Vol. 49, pp. 1606-1613.

-0.8 -A [6] Z. Liu et al, "Metal Nanocrystal Memories Part II:.3- \ .Electrical Characteristics", IEEE Trans on Electron

-1.0.. . . . .. . . . . ..E-ElDevices 2002, Vol. 49, pp. 1614-1622.102 103 104 [7] J. J. Lee et al, "Metal nanocrystal memory with high-k

tunneling barrier for improved data retention", IEEETime (s) Trans on Electron Devices, 52, pp. 507-511, Apr. 2005.

[8] Samanta S K et al, S. K. Samanta et al, "Enhancement ofFi2. 8 Post cycling retention characteristics ofNC memory window in short channel non-volatile memoryflash under NAND operation a) Effect of W devices using double layer tungsten nanocrystals",scaling b) Effect ofL scaling. IEDM Tech Dig 2005, pp. 170-173. IEDM Tech. Dig

2005, pp. 170-173.[9] D lelmini, et al, "A new channel percolation model for

4. Conclusion VT shift in discrete-trap memories", IRPS 2004, pp.515-521.

NC flash device analysis shows that large memory window [10] C. M. Compagnoni, D. lelmini, A. S. Spinelli, A. L.is possible at low operating voltages in NAND operation. Lacaita, "Modeling of tunneling P/E for nanocrystalScaling the device showed further improvement in the memories", IEEE Tran on. Electron Devices, 52, pp.memory window. This result is validated by the Capacitive 569-576, Apr. 2005.Charging model proposed in this work. It is found that [11] A. S. Cordan, Y. Leroy, B. Leriche, "Electrostaticscaling the device increase the percentage of edge dots coupling between nanocrystals in a quantum flashwhich are the cause of improvement in memory window as memory", Solid State Electronics, Vol. 50, Feb. 2006.they store more charge than the centre dots. Endurance of [12] CAPEM©Dthe L scaled devices showed better characteristics as http://www. ee. iitb. ac. inl-vlsilresearchlsoftwarelcapextIcompared to large channel devices. P/E speeds were very capext. html.slightly degraded after cycling and do not pose a serious [13] Klaus F. Schuegraf and Chenming Hu, "Hole Injectionreliability issue. Retention, although poor, did not degrade Si02 Breakdown Model for Very Low Voltage Lifetimeafter cycling and showed improvement with W scaling. Extrapolation", IEEE Trans on Electron Devices, Vol.Improvement in gate-dielectric quality would improve the 41, No. 5, May 1994, pp. 761-767.retention characteristics. Overall, it can be stated that NCflash devices show promising results for 65nm and beyondtechnologies.

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