RELIABILITY STUDY OF MICROWAVE GaAs FIELD-EFFECT TRANSISTORS*

Ronald E. Lundgren and Glenn 0. LaddtHughes Research LaboratoriesMalibu, California 90265

(213) 456-6411

Ohmic Contacts

A two-phase study was performed to investigatebasic failure mechanisms, alternate fabrication methods,and operational life times of low-noise microwaveMESFETs fabricated on GaAs channel layers grown byliquid-phase epitaxy. The basic sub-elements of theFET were investigated, and a Cr link for connecting theAl gate to Au bond pad was developed and incorporatedinto an improved PET. The first high-temperature (230 to270°C) accelerated life tests of GaAs FETs under oper-ational low-noise bias conditions (VD = S V, ID = 10 mA)were performed, and decreasing saturated drain currentwas found to be the primary failure mode below 270°C.An activation energy Ea = 1.5 eV was determined forthis mode, and an MTTF of 2 x 108 hr at 1000C is pro-jected. At 270°C the primary failure -mode is cata-strophic gate failure caused by Au-Al intermetallicformations. Comparisons of parameter aging data supporta relationship between dc and rf failure criteria, butconsiderable scatter appears to weaken its usefulnessfor individual devices.

Introduction

The GaAs FET has emerged as the most importantmicrowave device for low-noise amplifiers in the rangefrom 2 to 30 GHz. The major remaining questions withrespect to system applications, especially in long-lifecommunication satellites, are device reliability andoperational lifetime. This paper reports the results ofa two-phase study performed to investigate basic fail-ure mechanisms, alternate fabrication methods, andoperational lifetimes of low-noise microwave GaAs FETsfabricated on channel layers grown by liquid-phaseepitaxy (LPE). At the beginning.of the study, theHughes baseline FET design included Au-Ge/Ni Ohmicsource and drain contacts and a l-,am-long Al/GaAsSchottky--barrier gate. The gate bond pad was eitherplain aluminum or Al overlaid with a barrier metal anda Au bond pad. These basic metallizations are fairlycommon within the industry. The devices had no glassi-vation protection and they were in unpackaged chipform. The investigation consisted of two phases. Dur-ing Phase I, the basic sub-elements of the FET wereinvestigated using various test structures and high-temperature storage tests. The results of this phaseled to a change in our baseline FET design. DuringPhase II of the study, devices fabricated with this im-proved design were subjected to constant-stress accel-erated life tests, under both dc biased and unbiasedconditions.

Investigation of FET Sub-Elements

The Phase I sub-element tests will not be describedin detail. Only a brief review of the findings is pre-sented here and summarized in Table 1.

Both Au-Ge/Ni and Au-Ge/Pt Ohmic contacts were

tested. The test structures consisted of pairs ofsimple rectangular Ohmic contacts on LPE GaAs channellayers. The contact resistance of the Au-Ge/Ni con-

tacts was quite stable; it was approximately 10% higherafter an 80-hr anneal at 300°C. In contrast, the Au-Ge/Pt contacts had starting resistances approximately50% higher than the Au-Ge/Ni contacts, and the same

anneal found the Au-Ge/Pt resistance increasing byabout 75%. These tests are not considered conclusivesince we did not carry out extensive tests to optimizethe deposition and annealing conditions of the Au-Ge/Ptcontacts, but relied instead on the existing literatureand some spot checks at several annealing temperatures.

We did conclude, however, that the Au-Ge/Pt contactoffers no clear advantage ove- Au-Ge/Ni and, therefore,that the latter would continue to be used.

Schottky-Barrier

Several different test structures were used to

investigate the properties of Al Schottky-barrier gates.

Measurements showed that Al/GaAs diodes have no sig-nificant reverse-bias leakage currents either initiallyor following 84-hr anneals at 3500C. Step-stress tests

also showed that the barrier height and diode qualityfactor n are relatively stable up through 20 min annealsat 400°. Rutherford backscatter and Auger spectros-

copy measurements did reveal, however, that Ga diffusesrapidly through 1000 A Al layers, even at 300°C. Al-though no catastrophic failure mode was identified, thisdiffusion is probably of considerable significance forGaAs technology. Similar processes may also occur inAu films.

The alternative Schottky-barrier metallizationtested included 1000 A layers of Ti, Mo, and Cr. Tosimulate practical FET gate structures, which requirelow series resistance to achieve low noise figures,each of these alternative Schottky-barrier metalliza-tions was overlaid with 1000 A of Pt and 1000 A of Au.Neither the Ti/Pt/Au nor the Mo/Pt/Au Schottky-barrierdiodes degraded significantly following 80-hr annealsat 300°C and 350°C, respectively. Both metallizationsappear, therefore, to offer potentially reliable alter-

natives to Al gates. But because they have higherresistance and are more difficult to fabricate, we

retained the Al gate metallization. In contrast to theother materials, the Cr/Pt/Au metallization showed con-

siderable deterioration after 85 hrs at 350°C; theSchottky-barrier converted to a nonrectifying, nonlinearOhmic contact.

Gate Bond Pad

Following the decision to retain Al for the gateSchottky-barrier, new designs for the gate bond pad were

This paper is based in part on work performed under the sponsorship of the

International Telecommunications Satellite Organization (INTELSAT). Anyviews expressed are not necessarily those of INTELSAT.

tNow at the Hughes Industrial Electronics Group, Torrance Research Center,Torrance, California.

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Abstract

Table 1. Summary of FET Sub-Element Tests

lFET Element MTest Test Results Final SelectionPETElement Metals

Au-Ge/Ni Stable contact resistance (80 hr/3000C)Ohmic contact Au-Ge/Ni

Au-Ge/Pt No advantage over Au-Ge/Ni

Al No significant leakage currents (84 hr/350°C)

t and n stable (20 min/400°C)

Ga diffuses rapidlySchottky-barrier diode Al

Ti/Pt/Au Stable (80 hr/350°C)

Mo/Pt/Au

Cr/Pt/Au Nonrectifying after anneal (80 hr/350°C)

Al Au-Al interaction with Au wire bond. Ultimate loss of gatecontrol

Au-Al

Gate bond pad Pt/Al Intermetallic degradation Au-Cr-Al

Ti/Al Satisfactory couples

Cr/Al

investigated. When Au bond-wires are bonded to an Al orAu/Al pad, well known Au-Al intermetallic formationscan occur, usually with the eventual result that sig-nificant quantities of the Al disappear from the gate.This leads to voids in the gate and catastrophic lossof gate control over source-drain current. To find a

satisfactory barrier to Au/Al interaction, some teststructures consisting of a square aluminum pad over-lying or overlaid by a refractory metal were fabri-cated. Platinum, titanium, and chromium refractorylayers were tried. Degradation of the Pt/Al coupleswas noted immediately on annealing at 300°C for 30 min.The Ti/Al and Cr/Al pads, however, showed no change ineither metallurgical structure or electrical resist-ance after 120 hr at 3000. Although either Ti or Crappeared satisfactory for use as a bond pad transitionbetween gold and aluminum, chromium was selected be-cause of its lower resistivity.

Improved FET

As a result of these Phase I tests, the baselineFET design was changed to incorporate an Au gate bondpad and a Cr link io the gate. The original Au-Ge/Nisource-drain Ohmic contacts and the Al Schottky-barriergate stripe were retained. The resulting 1 pm x 300 pmgate GaAs FET is shown in Figure 1. The figure showsthat the layout of the gate bond pad is such that whena gold wire bond is made to the gold metallization, theCr barrier between the Au and Al will not be bridgedwithout being visually obvious.

Accelerated Life Tests

The low-noise microwave GaAs FET shown in Figure 1was the subject of the ,Phase II constant-stress accel-erated life tests. Both dc biased and unbiased deviceswere studied. Previous GaAs FET life tests had beenlimited to unbiased samples. Forty-five FETs were

tested, 15 in each of three ovens. The oven temperatures were 230°C, 255°C, and 270°C. Five of the test

samples in each oven were unbiased, and 10 were dcbiased to approximate optimum low-noise bias condi-tions: VD = 5 V and ID = 10 mA. The Hughes Space andCommunications Group has determined that this bias is

DRAIN

GATE

SOURCE-

K - 300 ,m

(b) Au-Cr-Al GATE PAD

Fig. 1. 1 pm x 300 pm gate GaAs FET with improvedgate bond pads.

256

K.

t

close to optimal for low-noise amplifiers when noisefigure, associated gain, and third-order intermodula-tion are considered.1 All of the FET chip test sampleswere mounted on NEC-type alumina microstrip carriers(Figure 2) using Au-Sn eutectic and gold wire bonds.These carriers protect the chips during repeated hand-ling, provide a convenient means for applying dc biasin the stress ovens, and provide a good microwavemedium for both dc and rf characterization.

FET CHIP

Fig. 2. Alumina microstrip carrier for PET chip.Carrier is 1 cm square.

Special ovens, shown in Figure 3, were constructedfor thermally stressing the FETs under dc bias condi-tions. Normal high-performance GaAs PETs tend to oscil-late under dc bias unless care is taken to suppressthese oscillations. Because of the high stress tempera-tures used, it was necessary to construct ovens havinglow-pass bias filters outside, at room temperature. Theindividual bias leads are then brought into thestainless-steel oven chamber through s50 Q coaxiallines consisting of stainless-steel tube, glass dielec-tric, and nickel wire. The only materials in the high-temperature chamber with the test devices are alumina,gold, stainless steel, glass, quartz, and nickel. Thechambers are continuously purged with pre-heated drynitrogen gas derived from a liquid source.

Fig. 3. Photograph of a life test oven with coverremoved and 10 carrier-mounted FETs in position.

Six of the carriers are shown coveredby hold-down fixtures.

Device Characterization and Failure Criteria

Visual, dc, and rf characteristics of the deviceswere monitored periodically, at room temperature, duringthe accelerated life tests, and the results were usedto measure the degree of aging and to signal devicefailure. Table 2 lists the specific characteristicsthat were monitored and the conditions of their measure-ment. All of the test samples were characterized inthis manner before accelerated aging began. Subse-quently, at the end of each stress cycle, all sampleswere subjected to visual inspection and dc I-V measure-ments, but only three randomly selected samples fromthe biased group were tested for dc drift and microwavenoise figure and gain. The 10 GHz microwave measure-ments required tuning input and output double-slugtuners to obtain minimum noise figure settings, a taskwhich is tedious, time-consuming, and subject to systemor operator errors.

The criteria adopted for determining device failureare based on measured changes in the dc parameters. Thefailure limits are shown in Table 2. For most of the dcparameters, functional failure is assumed to have occur-red if the parameter has changed by 10% or more; thespecific drain current IDS is allowed 20% variation,however. These criteria are similar to those of IRIEet al.,2 which were based on the results of a sensitiv-ity analysis of the equivalent circuit model for the NECGaAs PET, a device similar to ours. In practice, ofcourse, the microwave characteristics of the FETs areof greater operational importance than their dc charac-teristics. For low-noise amplifier applications, anincrease of 0.5 dB in Fmin or a decrease of 1 dB in Garepresent reasonable failure criteria. However, measur-ing rf characteristics is considerably more difficultand time consuming than measuring dc characteristics.Therefore, during these life tests, we relied solely onthe dc criteria for determining device failure; theFmin/Ga measurements at 10 GHz were made on a sampledbasis only, and the data was used to investigate cor-relations between the dc and rf parameter agingcharacteristics.

Test Results

As a result of the constant-stress acceleratedaging of the test samples, it was found that decreasingsaturated drain current (IDSS) was the primary agingsymptom of the 230°C and 255°C biased test devices. Thegroup-average percentage change in IDSS with accumulatedstress time is shown in Figure 4. The vertical barsshow the one-standard-deviation range of the data, andthe dashed curves are the least-squares straight-linefits. IDSS decreases with time for both the 230°C and2550C cases, and this parameter was the first to exceedits 10% failure limit. In contrast, the IDSS of the2700C group increased with time. All of the 270°C de-vices ultimately experienced catastrophic gate failure,resulting from Au-Al intermetallic formations. Thesestarted at the gate bond pad edge of the Al and pro-gressed toward and along the gate, eventually consumingenough Al to cause significant loss of gate control overdrain current. It is still undetermined whether theincrease in IDSS resulted because of intermetallicformation or because the test samples came from a dif-ferent wafer than the lower temperature test groups.

The IDSS failure of the 230°C and 255°C biased de-vices contrasts with the results of Irie et al. ,2 whoperformed life tests on unbiased devices. They reportedthat their GaAs FETs failed because increasing sourceand drain contact resistance caused the specific draincurrent, IDS, to decrease by more than the assignedfailure limit. The IDS of out devices also decreased,but the IDS failure limit was not reached until well

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LI

Table 2. FET Characteristics Monitored During Life Test

Typical Failure LimitFET Characteristixc Measurement Conditions Value on Change

Visual Appearance 200x to 1000x ---- - |

Saturated drain current, VD < 3 V, VG = 0 V 53 mA |10%

IDSS =max (ID)DC Specific drain current, IDS VD = 0.5 V, VG 0 V 28 mA ±20%

Pinchoff gate voltage, Vp VD -3V, ID 100 PA -3.0 V +10%

|Gate bias voltage, VG VD = 3 V, ID = 10 mA -1.9 V |10%

DC drift, ID versus time V = 3 V, V fixed (I -10 mA) _ _ _ _D D~ ~~~~G D

Minimum noise figure, F f = 10 GHz, VD = 3V, input and 4.2 dB 0.5 dBRF nin output tuned for minimum F

Associated gain, G 6.7 dB -1.0 dB_,a

Ia

iil

0

-5

-10

-15

0

-5

-10

-15

-5 l1l 1 1 1 1 1 -

1io 2 4 6 102 2 4 6 103 2

TIME, HR

Fig. 4. Percentage change in average saturateddrain current, IDSS, as a function of stress

time and temperature.

after IDSS had failed. Our results also show that un-

biased samples age significantly slower than biaseddevices; it would not be surprising if dc bias leads toa different failure mode as well. The life tests on theunbiased samples have not proceeded long enough todetermine if this is the case or to make direct com-

parisons with the NEC results.

We assume the standard log-no-rmal Arrhenius fail-ure model3 to interpret the test data. Figure 5 showsthe MTTFs determined for our three biased stress cases.

The values for 230°C and 255°C represent the MTTFs for

failure of IDSS. The 270°C value represents the mediantime for catastrophic gate failure; that is, the timeat which an abrupt change in gate voltage was requiredto restore low-noise bias conditions in the oven. Astraight-line extrapolation through the 230°C and 255°Cvalues was used to estimate a failure-mode activationenergy Ea = 1.5 eV and to predict MTTFs at lower tem-peratures. At 1000C, the predicted MTTF is 2 x 108 hr.The 270°C data point was not included in this extrapola-tion because the failure mode at this temperature isdifferent; this mode is believed to be of importanceonly at high temperatures. Figure 5 includes the re-

sults of Irie et al.2 for comparison. They determinedan Ea Of 1.8 eV for their unbiased FETs and a higherMTTF curve, as shown.

106

LLH-

102

10 L

120 140 160 180 200 250

TEMPERATURE, C

300 350 400

Fig. 5. MTTF as a function of ambient temperature fordc biased (VD = 5 V, ID = 10 mA) HRL GaAs FETs

and unbiased NEC FETs.

Failure Analysis

Samples of the failed devices were examined by SEMand electron microprobe. Figure 6 shows a photomicro-graph of a biased FET following 431 hr- at 270°C. The

258

I' 12'

tSi

104

103

Optical microscope examination of the 230°C and2559C test samples shows that the source and drain goldhave become rough and pock-marked (Figure 8), leadingto increased resistance of the Ohmic contacts. Thegold on the gate pads has also become darker and mot-tled in appearance. None of the samples exhibit evi-dence of gold electromigration.

Fig. 6. Biased FET after 431 hr at 2700C.

left-hand gate bond pad and a portion of the gate areseverely degraded to the point of partial loss of gatecontrol. The right-hand pad appears undisturbed. AnSEM photo of the left pad is shown in Figure 7; theoptically black Au-Al formation appears white to theSEN. Portions of the Au layer have disappeared, downto the underlying Cr layer; they have served as sourcesof gold for the intermetallic formation along the Almetallization. Electron microprobe analysis of thesame device reveals that both gold and aluminum havebeen transported across the chromium barrier andthroughout the gate pad region, leading to the Au-Alformations. Similar analysis of the undeterioratedright-hand gate pad shows no evidence of transport; theAu and Al are still in place, separated by the Crbarrier.

Fig. 7. SEM photograph of deteriorated gatebond pad and gate.

Fig. 8. Photomicrograph of biased FET showingroughened texture of gold metallization.

FET has been at 255°C for 799 hr.

Biased samples from all three test groups alsodeveloped a dark gray-brown discoloration of the GaAssurface between the gate and drain metallizations; thesource-gate area appears unchanged. None of the -un-biased FETs developed this symptom. The cause of thediscoloration was not identified; SEN examination re-vealed no significant differences between the source-gate and gate-drain areas, and electron microprobeanalysis failed to detect any unexpected element.

DC-RF Correlations

There are serious questions regarding the validityof using dc parameter measurements to determine thefunctional failure of a microwave device. To investi-gate correlations between the dc and rf aging charac-teristics of the FETs, scatter diagrams were plottedfor various dc and rf parameter pairs. Figure 9 showsthe change in minimum noise figure, AFmin, versus thecorresponding change in saturated drain current, AIDSS.Each point represents the measurement results for anindividual test sample at a particular point in time.Because we are most interested in the parameter cor-relation in the neighborhood of the assumed dc failurecriteria, we have excluded those few points for whichAIDSS < - 20% (i.e., twice the failure limit). Theleast-squares linear regression fit (LRF) to the datais shown in the figure. This line passes close to thefailure point (AIDSS = - 10%, AFmin = 0.5 dB). A goodagreement is also found for AFmin versus AIDS; some-what poorer agreements are found for AGa versus AIDSSand AGa versus AIDS. Thus,-the rf data tend to supportthe assumed dc failure criteria on average; however,there is considerable scatter in the data, and thevalidity of applying dc criteria to individual GaAsFETs remains unsupported. This topic needs furtherinvestigation.

Conclusions

During Phase I, it was determined that Au-Ge/NiOhmic contacts and Al Schottky-barriers are, by them-selves, relatively stable metallization components on

259

k.l

4

3

co

ELL

2

6459-11 RI

-20 -16 -12 -8 -4 0 4 8

A IDSS' 96

Fig. 9. Change in Fmin versus change in

IDSS for biased life-test FETs.

GaAs. It is important in FET construction, however,

that an effective barrier be placed between the gate Aland its Au wire bonds. A new Au-Cr-Al gate bond padstructure successfully eliminates Au-Al interaction as

a major reliability problem, at least up to 2600C.

As a result of the Phase II accelerated life testson low-noise-biased GaAs FETs, long operational life-times are projected (e.g., 2 x 108 hr at 1000C). Theprimary failure mode below 2700C was decreasing sat-urated drain current; the activation energy for thismode is Ea = 1.5 eV. Unbiased FETs age significantlyslower than dc biased FETs, thus supporting theneed for realistic electrical stress levels in life-test programs. Comparisons were made between dc andrf parameter aging characteristics, and it was deter-mined that, on the average, there is a reasonable cor-relation between the two; however, on an individualdevice basis, the measurement scatter was large enoughto negate the usefulness of this correlation. Because

of the potential saving of time and effort in beingable to rely on low-frequency measurements, this cor-

relation problem should be investigated further.

References

1. B.L. Walsh, private communication.

2. T. Irie, I. Nagasako, H. Kohzu, and K. Sekido,"Reliability Study of GaAs MESFETs," IEEE Trans. onMicrowave Theory and Techniques MTT-24, 6/76,pp. 321-328.

3. J. Vaccaro, et al., Reliability Phjsics Notebook,Battelle Memorial Institute, Report No. RADC-TR-65-330, 10/65, pp. 1-5.

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