ics 259/280 functional test program generation for microprocessors prabhat mishra
Post on 19-Dec-2015
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TRANSCRIPT
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Outline
Introduction Test Program Generation: Taxonomy
Test Program Generation Techniques Past Approaches Present Trends Future Directions
ConclusionReferences
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Introduction
Shrinking time-to-market, short product life .. Need to reduce design cycle time for embedded
microprocessors.
Functional verification is one of the major component of this design cycle time.
Existing validation approaches Simulation based approaches using random tests Formal techniques to verify certain properties
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Verifies stuck-at, bridging, delay.. faults Verifies Functional Correctness
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Fault Oriented
Fault Independent
Random Combined
(Critical Path)(RAPS, SMART)
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Fault Oriented
Fault Independent
Random CombinedImplicit (universal)
FaultWithout
FaultFunctional
Fault
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Fault Oriented
Fault Independent
Random CombinedImplicit (universal)
FaultWithout
FaultFunctional
Fault
Heuristic BDD
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Fault Oriented
Fault Independent
Random CombinedImplicit (universal)
FaultWithout
FaultFunctional
Fault
Heuristic BDD Exhaustive PseudoExhaustive
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Fault Oriented
Fault Independent
Random CombinedImplicit (universal)
FaultWithout
FaultFunctional
Fault
Heuristic BDD Exhaustive PseudoExhaustive
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Test Generation: Taxonomy
Test Generation
Functional TestManufacturing Test
Fault Oriented
Fault Independent
Random CombinedImplicit (universal)
FaultWithout
FaultFunctional
Fault
Heuristic BDD Exhaustive PseudoExhaustive
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Functional Test Program
TestProgGen
MOV R1, 011
MOV R2, 010
ADD R3, R1, R2
# R3 == 101
R3 == 101 ?
Verifies the functionality of the processor using assembly programs
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Test Program Generation Techniques
Past Approaches Functional Fault Model based Test Generation
Present Trends Micro-Architecture Coverage driven Test Gen. Instruction-Level Self Test Specification based Test Generation
Future Directions Software based Self Test Specification driven Validation
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Test Program Generation Techniques
Past Approaches Functional Fault Model based Test Generation
Nair et. al., IEEE Computers 1978Thatte et al. IEEE Computers,1980Brahme et al. IEEE Computers,1984Lin et al., DAC 1988Kannah et al., ATS 2000
Present Trends Micro-Architecture Coverage driven Test Gen. Instruction-Level Self Test Specification based Test Generation
Future Directions Software based Self Test Specification driven Validation
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Testing Random-Access Memories
Presented a fault model which views faults in memories at a functional level instead of at a basic gate level.
Memory Fault Model Memory cell array
One or more cells are stuck at 0 or 1.One or more pairs of cells are coupled.
DecoderDoes not access the addressed cellAccess multiple cells, including the addressed cell
Read/Write LogicSome output lines of the sense amplifier logic or
write driver logic may be stuck-at-0 or stuck-at-1
Nair et. al., IEEE Computers 1978
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Testing of Microprocessors
Graph model of the architecture Node = Register groups Edge = Instructions
Functional fault models Register decoding Instruction decoding Data Storage Data Transfer Data Manipulation
Test generation procedure Register decoding
Thatte et. al., IEEE Computers 1980
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Graph Model of the Microprocessor
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
Registers
R1: accumulator
R2: general purpose register
R3: scratch-pad register
Instructions
I1: Load R1
I2: Load R2
I3: Add R1 = R1 + R2
I4: Mov R2 = R1
I5: Store R1
I6: Store R2
I7: Mov R3 = R1
I8: Mov R1 = R3
R3
I7
I8
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Graph Model of the Microprocessor
Registers
R1: accumulator
R2: general purpose register
R3: scratch-pad register
Instructions
I1: Load R1
I2: Load R2
I3: Add R1 = R1 + R2
I4: Mov R2 = R1
I5: Store R1
I6: Store R2
I7: Mov R3 = R1
I8: Mov R1 = R3
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
Write (R3) = {I1, I7}
Read(R3) = {I8, I5}
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Microprocessor Fault Models
Register Decoding fd(Ri) = Ri
Write (Ri) and Read (Ri)
Instruction Decoding No instruction executed – f (Ij / ) Different instruction is executed – f(Ij / Ik ) F(Ij / Ij + Ik )
Data Storage Any cell of a register can be stuck-at-0 or stuck-at-1
Data Transfer A line in a transfer path can be stuck at 0 or 1 Two lines in a transfer path can be coupled
Data Manipulation
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Test Generation for Register Decoding
Initialize Q with all registers so that Ri lies ahead of Rj iff l(Ri) <= l(Rj)
A = register at the front of the Q
Repeat Write each register Ri of set A with data ONE and
register Rj at the front of Q with data ZERO Read each register Ri of A Read Rj
A = A U Rj
Q = Q - Rj
Until Q is empty
f(Ri) , for every Ri A
f(Ri) f(Rj) = for every Ri, Rj A
f(Ri) = 1
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Register Decoding Algorithm
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
A = {}
Q = {R1, R2, R3}
R1 ZERO
R1 ZERO ?
LOAD R1, ZERO
STORE R1
# Out == ZERO ?
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Register Decoding Algorithm
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
A = {}
Q = {R1, R2, R3}
A = {R1}
Q = {R2, R3}
R1 ZERO
R1 ZERO ?
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Register Decoding Algorithm
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
A = {}
Q = {R1, R2, R3}
A = {R1}
Q = {R2, R3}
R1 ZERO
R1 ZERO ?
R1 ONE, R2 ZERO
R1 ONE ?, R2 ZERO ?
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Register Decoding Algorithm
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
A = {}
Q = {R1, R2, R3}
A = {R1}
Q = {R2, R3}
A = {R1, R2}
Q = {R3}
R1 ZERO
R1 ZERO ?
R1 ONE, R2 ZERO
R1 ONE ?, R2 ZERO ?
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Register Decoding Algorithm
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
A = {}
Q = {R1, R2, R3}
A = {R1}
Q = {R2, R3}
A = {R1, R2}
Q = {R3}
R1 ZERO
R1 ZERO ?
R1 ONE, R2 ZERO
R1 ONE ?, R2 ZERO ?
(R1, R2) ONE, R3 ZERO
(R1, R2) ONE ?, R2 ZERO ?
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Register Decoding Algorithm
In
R1 R2
Out
I1
I3
I3
I4
I2
I6I5
R3
I7
I8
A = {}
Q = {R1, R2, R3}
A = {R1}
Q = {R2, R3}
A = {R1, R2}
Q = {R3}
A = {R1, R2, R3}
Q = {}
R1 ZERO
R1 ZERO ?
R1 ONE, R2 ZERO
R1 ONE ?, R2 ZERO ?
(R1, R2) ONE, R3 ZERO
(R1, R2) ONE ?, R2 ZERO ?
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Extended Fault Model
Representation for Instructions An instruction is composed of a sequence of
microinstructions. Each microinstruction is made up of a set of
microorders which are executed in parallelSWAP, CLR, NOT, MOV, EXG, ADD, MUL, DIV
Simple ADD has 4 microorders
Fault model for the Instruction Sequencing One or more microorders can be inactive Microorders which are normally inactive become
active F(I) = I + + - -
Brahme et. al., IEEE Computers 1984
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Further Improvements
Chen-Shang Lin and Hong-Fa Ho, DAC 88 Signal flow model of the processor Functional fault models are derived from Turing
machine model Developed O-algorithm to eliminate redundant
tests and obtain improved fault coverage
Rajesh Kannah, C.P. Ravikumar, ATS 2000 Reduce the test application time. Use structural information to eliminate certain
functional tests using the notion of fault-grading.
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Test Program Generation Techniques
Past Approaches Functional Fault Model based Test Generation
Present Trends Micro-Architecture Coverage driven Test Generation
Iwashita et al., ICCAD 1994Ho et al., ISCA 1995Ur et al., DAC 1999Campenhout et al., DAC 1999
Specification driven Test GenerationGeist et al., DAC 1999 (Specman Elite from Verisity)Mishra et al., HLDVT 2002
Instruction-Level Self TestLai et al., DAC 2001Chen et al., DAC 2003
Future Directions Software based Self Test Specification driven Validation
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High-Level Test Generation
Campenhout et. al., DAC 1999
DPTRACE: Path Selection
DPRELAX: Value Selection
CTRLJUST: Signal Justification
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Test Program Generation Techniques
Past Approaches Functional Fault Model based Test Generation
Present Trends Micro-Architecture Coverage driven Test Generation
Iwashita et al., ICCAD 1994Ho et al., ISCA 1995Ur et al., DAC 1999Campenhout et al., DAC 1999
Instruction-Level Self TestLai et al., DAC 2001Chen et al., DAC 2003
Specification driven Test GenerationGeist et al., DAC 1999 (Specman Elite from Verisity)Mishra et al., HLDVT 2002
Future Directions Software based Self Test Specification driven Validation
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Specification driven Test Gen. using Model Checker
Architecture Specification
Properties (SMV) ADL Specification
Processor Model
SMV
Counterexamples
Simulator
Sim
ula
tor Gen
eratio
n
Coverage Report
No
t En
oug
h P
rop
ert
ies
Automatic
ManualTest Programs
Mishra et. al., HLDVT 2002
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Test Program Generation
Specification of Properties Stall Decode Unit of the DLX architecture stall: assert G(ID._stall = 0);
Test Program The Decode unit (ID) will be stalled in cycle 4.
Fetch Cycle Opcode Dest Src1 Src2
1 NOP
2 ADD R3 R1 R2
3 ADD R4 R3 R2
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Test Program Generation Techniques
Past Approaches Functional Fault Model based Test Generation
Present Trends Micro-Architecture Coverage driven Test Generation
Iwashita et al., ICCAD 1994Ho et al., ISCA 1995Ur et al., DAC 1999Campenhout et al., DAC 1999
Specification driven Test GenerationGeist et al., DAC 1999 (Specman Elite from Verisity)Mishra et al., HLDVT 2002
Instruction-Level Self TestLai et al., DAC 2001Chen et al., DAC 2003
Future Directions Software based Self Test Specification driven Validation
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Conclusion
The boundary is blurring …..
Confluence of Functional Verification and Manufacturing testing Software-Based Self-Test
Top-down and Bottom-up Validation Specification driven Test Generation Micro-Architecture Coverage driven Techniques
Combined Simulation and Formal Techniques
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References
Test Generation for Microprocessors: S. Thatte et al., IEEE Computers, June 1980
Functional Testing of Microprocessors: D. Brahme et al., IEEE Computers, 1984
Automatic Test Program Generation for Pipelined Processors: H. Iwashita et al., ICCAD 1994
Architecture Validation for Processors: R. Ho et al., ISCA 1995
Automatic Functional Test Program Generation for Microprocessors: C. Lin et al., DAC 1998
Micro Architecture Coverage Directed Generation of Test Programs: S. Ur et al., DAC 1999
High-Level Test Generation for design Verification of Pipelined Microprocessors: D. Campenhout et al., DAC 1999
Functional Testing of Microprocessors with Graded Fault Coverage: R. Kannah et al., ATS 2000
Instruction Level DFT for Testing Processor and IP Cores in System-on-a-Chip: W. Lai et al., DAC 2001
Automatic Functional Test Program Generation for Pipelined Processors using Model Checking, by P. Mishra et al., HLDVT 2002.
A Scalable Software-Based Self-Test Methodology for Programmable Processors: L. Chen et al., DAC 2003