icons - intracortical neuronal stimulator graphic simulation of response of 555 type vco to a vctrl...

ICONS - Intracortical Neuronal Stimulator

Wireless Power and Data Front End Unit

Andreia Vieira de Vasconcelos Otão

Dissertação para obtenção do Grau de Mestre em

Engenharia Electrónica

Júri

Presidente: Prof. Doutor João Costa Freire

Orientador: Prof. Doutor Moisés Simões Piedade

Co-Orientador: Prof. Doutor Marcelino Bicho dos Santos

Vogais: Prof. Doutor Pedro Santos

Novembro de 2009

Acknowledgements

I would like to thank to Prof. Moisés Piedade for the help, explanations and guidance that

he gives in the development of this work, and to Prof. Marcelino Santos, for his availability and

help.

A special thanks to Ângelo Monteiro for the help along the development of the LDO design.

I also would like to express my appreciations to my colleagues in SIPS group and Quality,

Test and Co-Design of HW/SW Systems Group at INESC-ID Lisbon.

I am grateful to my family and friends for all the support, motivation and patience during the

course.

i

Abstract

This research concerns on three blocks of a cortical prosthesis system: the Radio frequency

(RF) transformer; the block to recover and transform power; and the block to recover the clock

and demodulate the carrier.

The RF wireless resonant transformer allows data and power transfer. The transmitter (out-

side unity) modulates the data to be sent to the receiver (implant) where is decoded to process

the visual cortex stimulation.

The DC voltage obtained by rectification and filtering in transformer secondary side is a non

regulated signal. Thus, a LowDropOut (LDO) voltage regulator is used, which offers protection

and filtering from electrical transients and noise.

The clock recovery and data demodulation are made using a low power Phase locked loop

(PLL). The system implemented in a complementary metal-oxide semiconductor (CMOS) 0.35

µm technology was manufactured and tested.

Simulation results and the layout of a prototype are presented to prove the presented work

feasibility.

Keywords: CMOS, RF wireless resonant transformer, Rectifier, LDO, PLL.

iii

Resumo

Esta pesquisa incide em três blocos de um sistema de prótese cortical: o transformador

Rádio Frequência (RF); o bloco para recuperar e transformar a energia; e o bloco para recuperar

o relógio e desmodular o sinal da portadora.

O transformador RF sem fios ressonante permite a transferência de dados e energia. O

transmissor (unidade exterior) modula os dados a serem enviados para o receptor (implante)

onde são decodificados para processar a estimulação do córtex visual.

A tensão contínua (CC) obtida por rectificação e filtragem no lado secundário do transfor-

mador é um sinal não regulado. Assim, um LowDropOut (LDO) regulador de tensão é usado, o

que oferece proteção e filtragem de transientes elétricos e ruídos.

A recuperação do relógio e a desmodulação de dados são feitos através de uma malha de

captura de fase (PLL). O circuito integrado da PLL na tecnologia CMOS 0.35 µm, foi fabricado e

testado.

Os resultados das simulações e o layout de um protótipo são apresentadas de modo a

provar viabilidade do trabalho apresentado.

Palavras Chave: CMOS, Transformador RF sem fios ressonante, Rectificador, LDO, PLL.

v

Contents

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 RF Transformer Design 7

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Secondary Circuit in Series Resonance . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Secondary Circuit in Parallel Resonance . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Series Resonance vs Parallel Resonance . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Power extraction from carrier 13

3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Rectification with a Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Class E rectifier with a series capacitor . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Class E rectifier with a parallel inductor . . . . . . . . . . . . . . . . . . . . 17

3.2.3 RF AC Rectification Summary . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Low Dropout (LDO) Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.1 Conventional LDO regulator topology . . . . . . . . . . . . . . . . . . . . . 21

3.3.2 Proposed LDO regulator topology . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

vii

CONTENTS

4 Data Receiver 35

4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2 Phase Locked Loop Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2.1 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.3 Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.2.5 PLL Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3 Phase Locked Loop Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4 IC test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.5 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5 Conclusions 55

5.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Bibliography 59

A LDO Transistors Sizes 61

B LDO Simulation Graphics 63

C PLL Schematics 71

D PLL Transistors Sizes 75

E Low pass filter auxiliary calculations 79

viii

List of Figures

1.1 Illustration of retinal prosthesis system. . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Schematic of retinal prosthesis system architecture (this work consists on the two

white blocks and on the RF Transformer). . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 RF coil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Schematic of simplified Steinmetz model of a RF transformer. . . . . . . . . . . . . 9

2.3 Schematic of the model of tuned transformer for low frequencies (frequencies much

lower than resonant frequency (fp)). . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 AC simulated response of the RF transformer with series resonance. . . . . . . . . 11

2.5 AC response of the RF transformer with parallel resonance. . . . . . . . . . . . . . 11

2.6 Schematic of resonant RF transformer with a class E power amplifier as source. . 12

3.1 Schematic of power recovery circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Schematics of class E rectifier with a series capacitor. . . . . . . . . . . . . . . . . 15

3.3 Current and voltage waveforms in class E ZVS rectifier (with series resonant trans-

former). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Current and voltage waveforms in class E ZVS rectifier (with parallel resonant trans-

former). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5 Output voltage waveform in class E ZVS rectifier (with series resonant transformer). 16

3.6 Output voltage waveform in class E ZVS rectifier (with parallel resonant transformer). 16

3.7 Schematics of class E rectifier with a parallel inductor. . . . . . . . . . . . . . . . . 17

3.8 Current and voltage waveforms in class E ZCS rectifier (with series resonant trans-

former). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.9 Current and voltage waveforms in class E ZCS rectifier (with parallel resonant trans-

former). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ix

LIST OF FIGURES

3.10 Output voltage waveform in class E ZCS rectifier (with series resonant transformer). 18

3.11 Output voltage waveform in class E ZCS rectifier (with parallel resonant transformer). 19

3.12 AC response of the class E ZVS rectifier. . . . . . . . . . . . . . . . . . . . . . . . 19

3.13 AC response of the class E ZCS rectifier. . . . . . . . . . . . . . . . . . . . . . . . 19

3.14 LDO regulator topology with output capacitor. . . . . . . . . . . . . . . . . . . . . . 21

3.15 AC response of conventional LDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 LDO regulator topology proposed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.17 Schematic of the error amplifier for LDO. . . . . . . . . . . . . . . . . . . . . . . . . 24

3.18 Schematic of bias unity for LDO ciruit. . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.19 Schematic of control unity for LDO ciruit. . . . . . . . . . . . . . . . . . . . . . . . . 26

3.20 LDO transient response with full and no load. . . . . . . . . . . . . . . . . . . . . . 28

3.21 PSR curve of a conventional LDO voltage regulator. . . . . . . . . . . . . . . . . . 29

3.22 LDO Line Regulation response with full and no load. . . . . . . . . . . . . . . . . . 30

3.23 LDO Load Regulation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1 Basic block diagram of the PLL implemented. . . . . . . . . . . . . . . . . . . . . . 36

4.2 Block diagram of a sequential PD (PFD). . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3 PFD state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.4 Input signals (clkre f and clkvco) and output signals (up and dw)from phase detector. 38

4.5 Input signals (clkre f and clkvco) and output signals (up and dw)from phase detector,

when both the signals have the same frequency, but lagged one of another. . . . . 39

4.6 Dynamic PFD circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.7 Graphics of UP and DOWN pulse with variation as a function of input phase differ-

ence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.8 Block diagram of Hodge phase detector (Linear PD). . . . . . . . . . . . . . . . . . 40

4.9 Graphic with the simulation result of Hodge phase detector operation. . . . . . . . 41

4.10 Basic schematic of charge-pump and low pass filter of PLL implemented. . . . . . 41

4.11 Schematic of charge-pump implemented. . . . . . . . . . . . . . . . . . . . . . . . 42

4.12 Plot of the function Icp vs. phase error θe. . . . . . . . . . . . . . . . . . . . . . . . 43

4.13 Block diagram of the ring oscillator with 9 inverters . . . . . . . . . . . . . . . . . . 43

4.14 Schematic of source coupled delay with symmetrical loads. . . . . . . . . . . . . . 44

x

LIST OF FIGURES

4.15 Schematic of the bias cell that provide the vbn voltage. . . . . . . . . . . . . . . . . 44

4.16 Schematic of the differencial-to-single-ended converter used with the ring oscillator. 45

4.17 Graphic simulation of response of ring oscillator to a vctrl = 1.5. . . . . . . . . . . 46

4.18 Graphic of ring oscillator gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.19 Basic block diagram of a similar 555 type VCO. . . . . . . . . . . . . . . . . . . . . 47

4.20 Illustration of the 555 VCO’s capacitor charge/discharge operation. . . . . . . . . . 47

4.21 Graphic simulation of response of 555 type VCO to a vctrl = 1.5. . . . . . . . . . . 48

4.22 Graphic of relaxation VCO gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.23 Schematic of a second-order low pass filter. . . . . . . . . . . . . . . . . . . . . . . 49

4.24 Loop capture process of PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.25 Layout of low power PLL implemented. . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.26 Foto of the PLL PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

B.1 LDO AC open-loop simulation with/without load and max/min Vin. . . . . . . . . . 64

B.2 LDO output impedance evolution with full load and maximum Vin. . . . . . . . . . 64

B.3 LDO output impedance evolution with full load and minimum Vin. . . . . . . . . . . 65

B.4 LDO output impedance evolution with no load and maximum Vin. . . . . . . . . . . 65

B.5 LDO output impedance evolution with no load and minimum Vin. . . . . . . . . . . 66

B.6 LDO PSR curve with full load and maximum Vin (for all corners). . . . . . . . . . . 66

B.7 LDO PSR curve with full load and minimum Vin (for all corners). . . . . . . . . . . 67

B.8 LDO PSR curve with no load and maximum Vin (for all corners). . . . . . . . . . . 67

B.9 LDO PSR curve with no load and minimum Vin (for all corners). . . . . . . . . . . 68

B.10 LDO Line Regulation response with no load (for all corners). . . . . . . . . . . . . 68

B.11 LDO Line Regulation response with full load (for all corners). . . . . . . . . . . . . 69

C.1 Schematic of a similar 555 type VCO. . . . . . . . . . . . . . . . . . . . . . . . . . 72

C.2 PCB schematic of PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

C.3 Schematic of PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

xi

List of Tables

2.1 Experimental results for both RF coils. . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 RF tuned transformer parameters (k = 0.3; Q1 =Q2 = 279; Rload = 220 Ω; fr = 13.5

MHz) for experimental coils. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 RF tuned transformer efficiency (series and parallel topology). . . . . . . . . . . . 12

3.1 Low pass filter elements of the ZVS class E rectifier. . . . . . . . . . . . . . . . . . 17

3.2 Low pass filter elements of the class E ZCS rectifier. . . . . . . . . . . . . . . . . . 17

3.3 RF transformer + Rectifier Efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 LDO Regulator overall specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.5 Pass Transistor parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.6 LDO AC open-loop simulation results. . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.7 Location of poles and zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.8 LDO output impedance simulation results. . . . . . . . . . . . . . . . . . . . . . . . 27

3.9 PSR simulation results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.10 Summarized LDO characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 Low pass filter elements values for the two cutoff frequencies and two VCOs. . . . 50

4.2 Summarized PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.3 Power consumption of each block of PLL. . . . . . . . . . . . . . . . . . . . . . . . 51

A.1 Error Amplifier transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

A.2 Bias Unity transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

A.3 Control Unity transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

A.4 Power-Down transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

xiii

LIST OF TABLES

D.1 PFD transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

D.2 Charge-Pump transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

D.3 Bias delay cell transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

D.4 Delay cell transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

D.5 Differencial-to-single-ended converter transistors sizes. . . . . . . . . . . . . . . . 77

D.6 555 type VCO transistors sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

xiv

Acronyms

AC Alternating Current

CMOS Complementary Metal-Oxide-Semiconductor

DAC Digital-to-Analog Converter

DC Direct Current

D-FF Flip-Flop D

FSK Frequency Shift Keying

IC Integrated Circuits

ICONS Intracortical Neuronal Stimulator

ISM Industrial, Scientific and Medical

LDO Low-Dropout regulator

ng Number of Transistor Gates

PAE Power Added Efficiency

PCB Printed Circuit Board

PD Phase Detector

PFD Phase Frequency Detector

PLL Phase Locked Loop

PSR Power Supply Rejection

RF Radio Frequency

RS-FF Reset-Set Flip-Flop

VCO Voltage Controlled Oscillator

ZCS Zero-Current-Switching

ZVS Zero-Voltage-Switching

xv

1Introduction

Contents1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1

CHAPTER 1. INTRODUCTION

The project described in this report is integrated into a larger research project named ICONS

(Intracortical Neuronal Stimulator), developed in INESC-ID (Institute for Systems and Computer

Engineering - Research & Development) and INESC-MN (Institute for Systems and Computer En-

gineering - Research & Development - Microsystems & Nanotechnology), and supported by FCT

(Portuguese Foundation for Science and Technology) under the contract PTDC/EEA-ELC/68972/

2006.

This chapter begins by stating the relevance of the scientific area in question and presenting

some related works already done. Then, it is described the main goals and challenges of this

work.

1.1 Motivation

Biomedical applications have seen an intense research effort in the last few years. Due to

its high complexity it is a multidisciplinary area where microelectronics plays an important role

for the feasibility of most systems. Although, implementations in the field of visual rehabilitation

is in its early stages. Recently, researchers of this area developed a system that consists on an

artificial retina that converts the visual world in front of a blind person in a set of electrical signals

that can be used to stimulate the visual cortex in real time [1].

In these applications, the need for long time operation requires that the implant is powered

by the outside, in order to avoid unnecessary surgery for batteries replacement. To maintain the

long term usability for a minimally invasive implantation, the efficient power recovery from the

circuit should be maximized. First implants make use of wired links to transmit data and power

between the unit placed outside the body and that inside the body. However, this technique has a

high risk of infection and is considerably uncomfortable for the patient. In order to improve these

drawbacks, wireless solutions are presently being under development. Nevertheless, wireless

solutions present many challenges because power and wide bandwidth data have to be satisfac-

torily transmitted to the inside unit, in spite of the significant coupling losses. In what concerns the

inside unit power requirements, they depend on many issues, as for instance the electrode stim-

ulation power requirements, the internal control unit, the chosen technology, etc. Also, a duplex

data transmission system is desirable in order to have some information from inside unit status.

Visual cortex may be stimulated by microelectrodes arrays to allow profoundly blind peo-

ple have a limited but useful sense of vision of the world outside. The electrodes are activated

based in the data transferred by the outside unity. This data transmission is achieved through an

envelope modulated in FSK that is demodulated on the receiver using a low power PLL for this

2


purpose.

Reducing the size, the losses (improving the efficiency) and power consumption of the inter-

nal transcutaneous wireless link, of the Data/Clock Recovery and Power Supply Generator block

on receiver are the major challenges in designing these implantable circuits to make them less

invasive and more durable.

1.2 State of the Art

Cortical prostheses are under investigation by several groups. This project is part of one of

these groups, as stated earlier. The cortical prosthesis system developed in this research, use

an artificial retina that converts the visual world in front of a blind person in a set of electrical

signals that can be used to stimulate the visual cortex (generating phosphenes) in real time by

the intracranial circuitry (see Figure 1.1).

Fig. 1.1: Illustration of retinal prosthesis system.

The telemetry system consists of an internal unit for retinal stimulation and an external unit

for stimulation control and battery charging [2]. A pair of RF coils (one implanted in the human

body and another one close, but outside the body) links these two units providing stimulation

parameters and power to the internal electrodes (Fig. 1.1 and 1.2). To increase the power transfer

efficiency, normally both sides of the link are tuned to the same resonant frequency ([3], [4], [5] and

[6]). In order to improve the data transmission rate and the power efficiency, a bi-directional data

communication mode was adopted: the forward link transmits a power/data signal using binary

FSK (Frequency Shift Keying) modulation and the backward link operates in the reverse direction.

The RF transmitted signal is received by the internal coil and extracted through a half-wave rectifier

3


and a low pass filter ([5], [7] and [8]). Then, a voltage regulator generates the power needed to

the implanted microsystem ([9], [10], [11] and [2]). Using the same RF modulated signal, a data

decoder recovers the parameter data and uses it to stimulate the visual cortex. For this operation

it is necessary to recover the clock signal through a low power PLL [12]. Different topologies

for voltage-controlled oscillator (VCO) and Phase detector (PD) have been investigated over the

years ([4], [13], [14] and [15]). Ring oscillators are among the popular structures for VCOs due to

their wide tuning range and amenability to integration. The other VCO is a relaxation oscillator, as

the 555 type VCO is often used in monolithic integration, and capable of high speeds. The most

commonly phase detector used in these applications is the Phase Frequency Detector (PFD)

that ensures frequency and phase-lock by itself. The Electrode Stimulator block is responsible

for stimulating the electrodes and is essentially a digital controller that adresses several digital-

to-analog converter (DAC). The Control Circuit is a digital controller that provides the Electrode

Stimulator with the current amplitude and the duration of stimulation in clock cycles [1].

This work will focus only on the intracranial receptor, particularly in three blocks: RF Tran-

former, Power Supply Generator and Clock and Data Recovery.

1.3 Thesis Objectives

Implantable devices must work at ultra low-power level and be powered by wirelessly with

communication via a RF link. Power consumption and small integration area are major concerns

when designing such implantable circuits and systems.

The intracortical received energy to power up the implant must be rectified and regulated.

The rectifier gives a coarse DC voltage, which is then stabilizad by the LDO regulator. This LDO

voltage regulator is designed to have an improved efficiency and good transient response. The

voltage regulator must provide an approximately constant level voltage of 3.3 V for supplying the

implant circuit and the microelectrodes stimulators.

The low power PLL used to clock recovery must work at a central frequency of about 13.5

MHz (ISM band) and the data recovery should allow a demodulation of the signal sent to the

receiver with a bit rate of 1.25 Mbps.

Furthermore, the main objective of this thesis is to make a contribution to the ICONS project

that is being developed by INESC-ID.

4


Fig.

1.2:

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5


1.4 Outline

In this report, a cortical prosthesis system is presented. The general architecture is briefly

explained with more influence in two blocks (Power Supply Generator and Data/Clock Recovery),

where this work is focused.

In chapter 2, the RF wireless resonant transformer along with its efficiency main problems

are presented. Is presented two different topologies (series or parallel resonant circuit) to be

subsequently analyzed and compared.

Chapter 3focuses on the operation of RF carrier rectification and regulation. To realize this

operation two different topologies of class E rectifiers are studied (with a series capacitor or a

parallel inductor) and its consequencies in resonant frequency. Then, a LDO voltage regulator

is designed to obtain the desired voltage level to supply the implant. The circuit design and the

results are shown and explained.

In chapter 4 a PLL that is used in data and clock recovery is explained and each of its main

building blocks is described. The PLL circuit is designed and implemented in CMOS 0.35 µ m

technology.

Finally, in chapter 5 conclusions are reported and possible future work is discussed, in order

to realize some improvements.

In appendix A and D, LDO and PLL transistors sizes are shown, respectively. Appendix C

presents some PLL schematics and appendix B contains the graphics of LDO simulation results.

6

2RF Transformer Design

Contents2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Secondary Circuit in Series Resonance . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Secondary Circuit in Parallel Resonance . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Series Resonance vs Parallel Resonance . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7

CHAPTER 2. RF TRANSFORMER DESIGN

2.1 Introduction

The proposed transcutaneous transformer acts as a power RF link between the power

source and the load, with human body tissues between the coils ([3], [4], [5] and [6]). As the

dielectric environment surrounding the winding is an environment of low permeability magnetic,

not all the power lines of magnetic field generated on the primary side close by secondary side.

In this situation power losses occur (excessive losses on the implant side can damage the tissues

by overheating) due to a low coupling of the transformer. Others factors that contribute to a lower

transformer efficiency are: losses that depend of the dielectric environment and losses by Joule

effect [4].

A simple equivalent model of a coil, which is found in Figure 2.1(a), consists in a second-

order resonant circuit with a resistance that increases when the frequency of operation is in-

creased, and a capacity that results from the distributed capacity existing between any portion of

a coil and adjacent. Each coil is made by an insulated wire (Litz wire), wrapped in a flat single

layer circular coil, but can be made in multilayer (Fig. 2.1(b)) or in a cylindrical single layer coil.

(a) Equivalent model of a coil. (b) Foto of a multilayercircular coil.

Fig. 2.1: RF coil.

The parameters of some coil features (since it used the same coils on each side) measured

by an impedance analyzer are in table 2.1.

Tab. 2.1: Experimental results for both RF coils.N L (µH) Rac (Ω) C (pF) fp(MHz)

L1 16 12.29 3.74 2.70 27L2 16 12.29 3.74 2.70 27

Where: N is the number of turns; L is the coil inductance; Rac is the AC resistance; C is the

self capacitance and fp is the self-resonance frequency.

Figure 2.2 shows a simplified Steinmetz model of the transformer. The transformer is com-

posed of the two coils with inductances (λ11 and λ22) representing the magnetic field dispersion,

the mutual inductance (Lm), the resistances Rs1 and Rs2 that correspond to the series resistance

of the coils measured at 13.5 MHz and by the parasite capacitors (Cd1 and Cd2) from the individual

coils.

8


Fig. 2.2: Schematic of simplified Steinmetz model of a RF transformer.

To increase the power transfer efficiency and improve signal-noise ratio in data transferred,

both sides of the RF link are tuned at the same resonant frequency (13.5 MHz). This is realized

with the addition of a resonant capacitor in each side of the transformer.

Although the resonant capacitor in the primary side is always in series with the primary coil,

the secondary resonant capacitor can be added in series or in parallel with the secondary coil, as

shown in Fig. 2.3 [1]. The values of parasite capacitors (Cd1 and Cd2 ) from the individual coils are

negligible. The capacitors Cr1 and Cr2 (resonant capacitors) cancels the reactance of inductances

λ11 and λ22 for the working frequency.

Fig. 2.3: Schematic of the model of tuned transformer for low frequencies (frequencies muchlower than resonant frequency (fp)).

2.2 Secondary Circuit in Series Resonance

For the transformer coupling coefficient, k, equal to 1 all the lines of magnetic induction from

any of the coils windings are connected with all the turns of the other coil winding. In practice, this

situation is never achieved. The coupling factor depends on size and proximity of the coils and

decreases with the distance between them. The cranium thickness is considered equal to 1 cm

that corresponds to a value of k approximately equal to 0.15, therefore in practice the value of k

must be greater than this value (k ≤ 0.15).

Assuming a quality factor of a coil (Q# = ωL/Rs#, where # is the side of tranformer), the coil

values (L1 and L2) and the coupling coefficient, all the transformer elements can be calculated

through the folowing expressions: from (2.2.1) is obtained the value of mutual inductance (λ12 =

λ21 = Lm),

Łm = k√

L1 × L2, (2.2.1)

9


from (2.2.2) is obtained the values of the coils inductances λ11 and λ22,

λ11 = L1 − Lm

λ22 = L2 − Lm,(2.2.2)

from (2.4.2) is obtained the values of resistances Rs1 and Rs2

Rs# =ωL#

Q(2.2.3)

from (2.2.4) is obtained the values of resonant capacitors Cr1 and Cr2,

Cr#_serie =1

ω2r L#

, for series resonant frequency. (2.2.4)

The values of the transformer elements for the series ressonant topology are presented in

Table 2.2. The load resistance has the value of 220 Ω for a power consumption on secondary

system of 50 mW (suposing 3.3 V).

Tab. 2.2: RF tuned transformer parameters (k = 0.1; Q1 =Q2 = 279; Rload = 220 Ω; fr = 13.5 MHz)for experimental coils.

Parameter ValueCr1 [pF] 11.3Cr2 [pF] 11.3Rs1 [Ω] 3.74Rs1 [Ω] 3.74L1 [µH] 11.1L2 [µH] 11.1Lm [µH] 1.23

The graphic of the simulated frequency response RF transformer with series resonance is

shown in Fig. 2.4(a). As can be seen, the RF resonant transformer is tuned at the frequency

of 13.5 MHz. Zooming at the peak, it can be seen that the bandwidth of the the transformer is

approximately 822 kHz (see Fig. 2.4(b)). The bandwidth can be increased, decreasing the load

resistance, ie, a bandwidth of approximately 1.212 Mhz is achieved with Rload = 150 Ω.

2.3 Secondary Circuit in Parallel Resonance

For parallel resonant topology, all the link elements are calculated in the same way of the

series resonant topology.

The graphic of transfer function of RF transformer with parallel resonance is shown in Fig.

2.5(a). As can be seen, the RF resonant transformer is tuned at frequency of 13.5 MHz. The

bandwidth obtained for a load of 200 Ω and 150 Ω has, respectively, the value of ≈ 80 kHz and

176 kHz (see Fig. 2.5(b)).

10


(a) AC response. (b) Measure of the bandwidth.

Fig. 2.4: AC simulated response of the RF transformer with series resonance.

(a) AC response. (b) Measure of the bandwidth.

Fig. 2.5: AC response of the RF transformer with parallel resonance.

2.4 Series Resonance vs Parallel Resonance

Whereas the source resistance is zero is, the maximum theoretical efficiency that can be

obtained for the transformer is given by:

ηt =Pout

Pin=

RloadRs1 + Rs2 + Rload

= 96.7%. (2.4.1)

As can be seen from eq. (2.4.1), the efficiency of the transformer depends critically on the value

of resistors Rs1 and Rs2. It can be concluded that the only way to increase the efficiency of the

RF link, while maintaining a fixed value for the load resistance and the operating frequency of

the circuit, is to decrease the resistance losses of the coils. This means to use wire with larger

diameters in order to reduce the Stein effect, or to use Litz wire.

The primary system (emitter) consists of a power amplification stage, which was imple-

mented using a class E amplifier, a data shuffled, an oscillator that generates a sinusoidal signal

with a stable frequency and a control circuit that allows modulate the signal sent to the secondary

system [4] (see Fig. 1.2).

The simulations to measure the efficiency of the two transformer topologies are done using

11


as drive a power amplifier in primary side (Fig. 2.6). This device is a class E resonant circuit that

consists in a transistor (a MOSFET is used) that acts as a switch in the carrier frequency; and

an RF coil shock, which stores energy when the transistor is conducting, and releases the same

energy to the resonant circuit when the transistor is cuted off.

Fig. 2.6: Schematic of resonant RF transformer with a class E power amplifier as source.

The Power-added efficiency (PAE) efficiency is currently used to calculate power amplifier

efficiencies and is given by:

PAE =Pout − Pin

PDC. (2.4.2)

Pout is the power on load, Pin is the power at the power amplifier input and PDC is the power supply

consumption. The values of PAE efficiency measured for the two different topologies are shown

in Table 2.3. As can be seen, the topology that uses a resonant capacitor in parallel on secondary

side is more efficient than the other topology.

Tab. 2.3: Amplifier drive + RF tuned transformer efficiency (series and parallel topology).k = 0.1; Q1 =Q2 = 279; Rload = 220 Ω; fr = 13.5 MHz

Series resonant Parallel resonantPin [mW] 25.49 5.86PDC [mW] 878.3 877.7Pout [mW] 743.6 736.2PAE [%] 81.76 83.21

2.5 Synopsis

Contactless transformers require engineering modifications in order to decrease power con-

sumption and coil heating. In this chapter, was presented a RF transformer resonant at frequency

of 13.5 MHz, to minimize the winding resistance for reduce conduction loses. In order to improve

the data transmission rate and the power efficiency, two types of transformer topologies for con-

tactless applications are analysed: a series and a parallel resonant capacitor in secondary side

of the RF link. Consequently, efficiency is the parameter to maximise in all of them. As verified,

the topology with the parallel resonant capacitor in secondary side has an higher efficiency (83.21

%). However, the series resonant RF transformer has arrived at 81.76 %. The results achieved in

this chapter were obtained with the support of the PSpice tool [16].

12

3Power extraction from carrier


3.2 Rectification with a Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Class E rectifier with a series capacitor . . . . . . . . . . . . . . . . . . . . . . 14

3.2.2 Class E rectifier with a parallel inductor . . . . . . . . . . . . . . . . . . . . . 17

3.2.3 RF AC Rectification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Low Dropout (LDO) Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.1 Conventional LDO regulator topology . . . . . . . . . . . . . . . . . . . . . . 21

3.3.2 Proposed LDO regulator topology . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

13

CHAPTER 3. POWER EXTRACTION FROM CARRIER

3.1 Motivation

Among the circuits of the implant, the efficiency of the power recovery circuitry is consid-

ered one of the most important factors governing the overall implant performance. Rectifiers and

voltage regulators are known as power recovery circuitry (see Fig. 3.1).

The rectifier block performs an RF AC to DC non regulated conversion ([5], [7] and [8]).

The low pass filter in output filters the rectified signal providing coarse voltage regulation and

protection. The LDO regulator provides a stable DC level used for supplying the others blocks

present in the implant, including to stimulate the electrodes. The type of the on-implant regulators

is often chosen as a series (linear) regulator, designed to work properly with a small voltage drop

between input and output ([9], [10], [11] and [2]).

Fig. 3.1: Schematic of power recovery circuitry.

3.2 Rectification with a Schottky Diode

High frequency diode rectifiers have two main power losses contributions that are associ-

ated with the diodes: losses due to its forward voltage drop and a high frequency loss that can be

attributed to the finite switching time of the diode. However, there losses can be reduced by using

Schottky diodes. The voltage response is very fast on this type of diodes and the turn on voltage

is smaller than in conventional diodes.

The computer simulation of the two rectifiers topologies was made using the classe E ampli-

fier folowed by the RF resonant transformers optimized in the previous chapter 2 as source (see

Fig. 2.6).

3.2.1 Class E rectifier with a series capacitor

A Class E Zero-Voltage-Switching (ZVS) rectifier with series capacitor [7] is shown in Fig.

3.2. The series capacitor sets the ON time. Second-order lowpass output filter (L f e C f ) reduces

the ripple of output voltage, intended to be between 5 % and 10% of its average value.

14


Fig. 3.2: Schematics of class E rectifier with a series capacitor.

When the diode is OFF, the capacitor current is equal to source current. Consequently, the

capacitor (C f ) voltage rises linearly (if Rload <<). The voltage across the diode is vd = vc (C

voltage) −vin (input voltage). When the diode voltage reaches its threshold voltage, the diode

turns ON. Capacitor C (resonant capacitor of transformer) sets the ON time. The diode turns

on at low dvdiode/dt and turns off at zero dvdiode/dt and low didiode/dt, to minimize switching

losses and noise (see Figure 3.3 and 3.4). The simulated circuit includes the series and parallel

resonant transformer with the respective rectifier. The capacitor C is the resonant capacitor in

secondary side of the link. To topology with a parallel capacitor in secondary side, the simulations

were made with a additional C equal to 10 pF.

Fig. 3.3: Current and voltage waveforms in class E ZVS rectifier (with series resonant trans-former).

Fig. 3.5 and 3.6 shows the output voltage of rectifier. The output value with low ripple is

contained in the desired range of voltage.

The values of the low pass filter elements are presented in Table 3.1.

15


Fig. 3.4: Current and voltage waveforms in class E ZVS rectifier (with parallel resonant trans-former).

(a) Output voltage of the rectifier. (b) Ripple of the rectifier output voltage.

Fig. 3.5: Output voltage waveform in class E ZVS rectifier (with series resonant transformer).


Fig. 3.6: Output voltage waveform in class E ZVS rectifier (with parallel resonant transformer).

16


Tab. 3.1: Low pass filter elements of the ZVS class E rectifier.

Parameter ValueLf [µH] 5Cf [nF] 20

3.2.2 Class E rectifier with a parallel inductor

The basic circuit of a class E rectifier with a parallel inductor or Zero-Current-Switching

(ZCS) rectifier is present in Figure 3.7. It consists of a Schottky diode D, an inductor L, and a

filter capacitor C f [8]. The parallel inductor sets the ON time. The low pass filter set the ripple in

output voltage, intended to be between 5 % and 10% of the mean value.

Fig. 3.7: Schematics of class E rectifier with a parallel inductor.

While the diode is ON, voltage across the inductance is constant and equal to output voltage

(Vout) plus diode voltage. Thus, inductance current increases linearly with a slope Vout/L. When

the diode current reaches zero, diode turns OFF. Consequently, inductance current is equal to the

sinusoidal input current, resulting in a sinusoidal inductor voltage. The reverse diode voltage is

equal to the difference between output voltage and inductance voltage. The simulated circuit

includes the results to series and parallel resonant transformer.

The rectifier diode turns ON at low dvdiode/dt and zero didiode/dt, and turns OFF at low

didiode/dt, reducing switching losses and the reverse-recovery effect (see Fig. 3.8 and Fig. 3.9).

The voltage in rectifier output is present in Fig. 3.10 and Fig. 3.11. As shown, is obtained a

signal with low ripple contained in the desired voltage range.

The values of the low pass filter elements are presented in Table 3.2.

Tab. 3.2: Low pass filter elements of the class E ZCS rectifier.

Parameter ValueL [µH] 5Cf [nF] 20

17


Fig. 3.8: Current and voltage waveforms in class E ZCS rectifier (with series resonant trans-former).

Fig. 3.9: Current and voltage waveforms in class E ZCS rectifier (with parallel resonant trans-former).


Fig. 3.10: Output voltage waveform in class E ZCS rectifier (with series resonant transformer).

18



Fig. 3.11: Output voltage waveform in class E ZCS rectifier (with parallel resonant transformer).

3.2.3 RF AC Rectification Summary

The introduction of rectifiers (more active elements) does not change the resonance fre-

quency, as can be seen by Fig. 3.12 and 3.13. The resonance peak still continues at frequency

of 13.5 MHz.

(a) Rectifier with the series resonant transformer. (b) Rectifier with the parallel resonant transformer.

Fig. 3.12: AC response of the class E ZVS rectifier.

(a) Rectifier with the series resonant transformer. (b) Rectifier with the parallel resonant transformer.

Fig. 3.13: AC response of the class E ZCS rectifier.

Tab. 3.3 shows the efficiency of each set of transformer + Rectifier.

As can be seen, by the obtained results, a greater efficiency is achieved with the combina-

tion 1 and 3.

Where: 1 - Transformer with series resonance + Class E ZVS Rectifier; 2 - Transformer with

19


Tab. 3.3: RF transformer + Rectifier Efficiency.

PAE [%]1 34.72 23.63 33.64 24

parallel resonance + Class E ZVS Rectifier; 3 - Transformer with series resonance + Class E ZCS

Rectifier and 4 - Transformer with parallel resonance + Class E ZCS Rectifier.

3.3 Low Dropout (LDO) Regulator

An LDO regulator is a DC voltage source which delivers a constant output voltage regardless

of load variations and input voltage variations. The need of on-chip voltage levels makes voltage

regulators a critical part of an electronic system design.

The choice of a voltage regulator for a given application offers numerous design tradeoff

considerations. While switch mode regulators provide good power efficiencies, they are costly in

terms of silicon area, and the magnetic elements are bulky and cause electromagnetic interfer-

ence (EMI). Moreover, the output voltage ripple and output noise of switching regulators might

not be acceptable for several applications such as critical RF circuits. On the other hand, linear

regulators have very small output voltage ripple, are compact, have low output noise, and may be

designed to be stable with varying loads [9].

So, the voltage regulator implemented, accordance with these behavioral characteristics, is

the LDO regulator, which overall specifications are presented in Table 3.4.

Tab. 3.4: LDO Regulator overall specifications.

Parameter Symbol Min Typ Max UnitInput Voltage Vin 3.5 - 5 V

Reference Voltage Vre f - 1.2 - VOutput Voltage Vout - 3.3 - VOutput Current Iout - - 40 mA

Junction Temperature T -40 50 125 Co

The specifications of the proposed LDO regulator cannot be all predetermined before the de-

sign is started, because there are several tradeoffs between different specifications. These LDO

features can be classified into three classes: 1) static-state specification; 2) dynamic-state spec-

ification; and 3) high-frequency specification. Line and load regulations, as well as temperature

coefficient, are regarded as static-state specifications, while line and load transient responses, as

well as ripple rejection ratio, are dynamic-state specifications. The high-frequency specifications

are Power Supply Rejection (PSR) and output noise.

20


The idea is to design the LDO in a standard 0.35 µm CMOS technology to reduce board

space and power consumption, and to be used in the implantable biomedical microsystem pre-

sented in Fig. 1.2 from section 1.2.

3.3.1 Conventional LDO regulator topology

The structure of a classical CMOS LDO, as shown in Figure 3.14, is composed of an er-

ror amplifier, a pass device (PMOS transistor) in common-source configuration operating in the

saturation region, a feedback resistor network and a voltage reference ([10] and [2]).

Fig. 3.14: LDO regulator topology with output capacitor.

The error amplifier compares the voltage reference (Vre f ) with the ouput voltage (Vout)

sensed through the feedback resistors R1 and R2, creating an error signal to control the gate of

the pass transistor, which forms the negative feedback loop.

The output node of an LDO regulator is typically the drain of a power transistor and the

dropout voltage required in this configuration is the overdrive voltage required to keep the PMOS

transistor in saturation region. The dropout voltage (Vdo) is defined as the voltage difference be-

tween unregulated supply voltage and regulated ouput voltage. The minimum permissible dropout

voltage of a linear regulator defines the maximum achievable efficiency.

Seeing Fig. 3.15(a) reveals the fact that there are two low-frequency poles that need to be

taken into consideration in evaluating the frequency response of the LDOs closed-loop transfer

function ([17]). One of the poles lies at the gate of the pass transistor (p1) and the other one at

the output of the regulator (p2). Owing to the large size of the pass transistor and therefore, its

huge input capacitance, the pole at its gate is located at low frequencies.

Therefore, load variations move the pole P2 and can lead the LDO to become unstable. In

order to minimize this problem a large external (due to its large dimension) capacitor in the output

node is used (see 3.14). This technique is based on dominant-pole compensation with pole-

zero cancellation. The second pole p2 is cancelled by the zero z1 created by the RESR (series

resistance of the output capacitor), as shown in Fig. 3.15(b). The pole created by output capacitor

21


(p3) is located beyond the unity-gain frequency (ω0) of the loop gain to provide sufficient phase

margin. However, when loop gain is too high, p3 locates before the unity-gain frequency, and an

even larger output capacitance is required to retain LDO stability.

(a) Without compensation. (b) With compensation.

Fig. 3.15: AC response of conventional LDO.

3.3.2 Proposed LDO regulator topology

3.3.2.1 Circuit Design

The circuit shown on Fig. 3.16 can be divided into blocks with specific functions on the

overall structure; the bias unity, the amplifier stage and the control unity to make the interface

between the previous ones and regulation of the output voltage. The output stage contained in

control unity, is the pass element of the LDO, and the input stage is the error amplifier.

The proposed scheme generates a zero internally instead of relying on the zero generated

by the load capacitor and its series resistance combination for stability.

Error Amplifier The error amplifier design demands careful attention to meet the required loop

gain, transient response and stability. Ideal requirements of the error amplifier are: 1) high dc gain

to ensure high loop gain (typically from 60 dB to 80 dB) for all loads; 2) low output impedance to

keep the pole at the input of the pass transistor at high frequencies; 3) high rail output to turn off

pass transistor when the load turns off; and 4) internal poles at significantly higher frequencies

compared to the cross over loop frequency. High output impedance of the error amplifier pushes

the pole at the input of the pass transistor to lower frequencies.

The error amplifier implemented for the proposed LDO have a basic structure shown in Fig.

3.17. It consist in a NMOS differencial pair with a resistive load (made with PMOS transistors), to

reduce the open loop gain of the amplifier and therefore improve the margin phase. The bias of

22


Fig. 3.16: LDO regulator topology proposed

the amplifier is realized through the bias cell presented in Fig. 3.18, which also supply the others

blocks of circuit (trhough VCASN and VBIASN). This block receives 2 uA of bias current.

Pass Device The power PMOS transistor must operate in saturation region due to the stability

problem at different input voltages. The change in voltage gain due to different drain−source

voltage is not substantial when the transistor operates in saturation region. When delivering

the maximum current, the device should be in saturation, thus the pass device dimensions are

calculated through the folowing equation ([17]):

WL

=Iout max

kp.V2do

. (3.3.1)

The pass transistor is designed to deliver a drain current of 40 mA while maintaining a saturation

voltage, Vds ≥ Vgs−Vt , of 200 mV or less. The theoretical value of the W/L of the pass transistor

is found in Table 3.5.

Tab. 3.5: Pass Transistor parameters.Parameter kp (µA/V2) W(µm) L (µm)

Value 31 16129 0.5

The important design consideration for the pass transistor is the dropout voltage. Increasing

the size of the pass transistor lowers the dropout voltage for a particular output current, but wider

pass transistor introduces higher input capacitance making it difficult to meet stability require-

ments. The power PMOS transistor in the proposed LDO operates in linear region at dropout

(operating in saturation region instead as the input voltage increases), and hence, the required

23


Fig. 3.17: Schematic of the error amplifier for LDO.

transistor size can be reduced significantly for the ease of integration and cost reduction (see

Appendix A).

Resistor Network The voltage level in output of LDO is given by the relationship between the

voltage divider in feedback loop, ie,

Vre f =R2

R1 + R2Vout (=)

R1R2

= 1.75. (3.3.2)

The potential divider, are typically very large (R1 + R2 >> rdsPassDevice) for low quiescent

power consumption.

By using two transistors instead of two resistors, is possible reach the desirable gain and

have less consumption and more integration capability (Fig. 3.19). The transistors have the drains

shunted with the gates (connected like diodes) and they are designed to guarantee that they are

always in the saturation region, in order to achieve a good resistive behavior. The dimensions of

NMOS transistors are presented in Appendix A.

Control Block The LDO control is made by continuous adjustment of the output voltage (Vout).

The error amplifier generates at its output, a signal (Verror) proportional to the difference found

between the output voltage specified and the voltage level achieved (see Fig. 3.19). Thus, by

24


Fig. 3.18: Schematic of bias unity for LDO ciruit.

imposing the necessary voltage level to let the proper current pass in the power device, via the

voltage divider, Vout reaches the voltage level desired.

All the blocks have some transistors of power-down to shut off the circuit when is needed,

reducing the power consumption of the entire cell.

3.3.2.2 Results

AC Open Loop Analysis To ensure that the circuit will be stable in all operating conditions, the

dynamic behavior is studied considering the most relevant poles and zeros of the system.

The power transistor in the proposed LDO is much smaller that his theoretical value (3.3.1)

since it operates in triode region at dropout. The smaller size results in a smaller gate capacitance.

This helps to increase the frequencies of the nondominant poles and hence a better stability can

be achieved. Moreover, the smaller gate capacitance improves the slew rate at gate drive and

a faster transient response can be obtained. The stability of the proposed LDO is not affected

when the supply voltage increases from dropout. When the input voltage increases, the operation

region of the power transistor change from linear to saturation region.

The first pole (P1) is called the dominant pole. This pole is produced by the Miller effect

25


Fig. 3.19: Schematic of control unity for LDO ciruit.

associated to the CGtot of the pass transistor. Through a hspice simulation, the value of CGtot was

obtained, being equal to 5e-14 F.

As mentioned previously, when the loop gain increases, the classical LDO based on dominant-

pole compensation may be unstable. To guarantee system stability frequency compensation is

necessary. A solution to this problem is to introduce a zero that compensates the phase contri-

bution of one pole to guarantee phase margin better than 45 deg. So, the addition of an intern

capacitor generates a second pole (P2) and a zero (Z1) that compensates the circuit. This capac-

itor improves the transient response of the LDO. The MOSCAP introduced has the capacitance

value of 41 pF (see Fig. 3.19 the transistor in blue). The third pole (P3) in high frequencies is

introduced by the error amplifier.

The output capacitor (Cout)is important to obtained a good PSR at high frequencies.

Since the load plays the major role in system stability, two distinct situations are used to

observe the frequency performance: with full load (40 mA) and without load. Table 3.6 shows the

ac open-loop simulation results for the LDO under these conditions with maximum and minimum

26


Vin (see Fig. B.1 in the appendix B). System stability is guaranteed in all cases. The values of

the poles and zero for all the situations are described in tale 3.7. Without load the pole P2 moves

to lower frequencies due to the increase of output resistance.

Tab. 3.6: LDO AC open-loop simulation results.

Condition DC Gain [dB] Phase Margin [deg]Max. Vin & Max. Load 78.192 74.076Min. Vin & Max. Load 39.2 122.75Max. Vin & No Load 83.373 47.485Min. Vin & No Load 80.945 53.922

Tab. 3.7: Location of poles and zero.

Frequency (Hz)No load Full load

P1 459 97P2 265k >7MP3 7M 7MZ1 46k 57k

Output Impedance Seen that the objective of a voltage regulator is work as a voltage source,

the output impedance (Zout) should be zero, otherwise fluctuations in the output node can occur.

Thus, the LDO must keep the output impedance as low as possible. Fig. B.2, B.4, B.3 and B.5

in appendix B shows the evolution of the Zout with the load frequency. Table 3.8 summarizes the

simulations done.

Tab. 3.8: LDO output impedance simulation results.

Condition Zout@DC [Ω] [email protected] MHz [Ω]Max. Vin & Max. Load 176k 31kMin. Vin & Max. Load 7.3k 3.7kMax. Vin & No Load 225M 1.5GMin. Vin & No Load 174M 1G

Transient Response Load transient response is critical when there is a sudden change in load

current, and a good load transient response results in minimal overshoot, as well as undershoot,

and fast recovery time. The response time of an LDO depends on the voltages slew rate at the

gate drive of the power transistor and the loop-gain bandwidth.

A reason to use an external capacitor is to improve transient responses, because if charged,

it will work as a current source for a while with infinite bandwidth, allowing the regulator to settle

in the new state. During a high transient load change, the ripple presented at the output node

depends on the charge stored (Q) in the output capacitor and is given by

4V ≈ 4QCout

[V] (3.3.3)

27


The simulations of the transient responses (including the graphic of Power-Down signal) for

all the load and Vin states are shown in Fig. 3.20(a) and 3.20(b). The results achieved have the

overshoot peaks small and a fast circuit time response.

(a) Max. Vin.

(b) Min. Vin.

Fig. 3.20: LDO transient response with full and no load.

28


PSR Analysis In circuits like PLLs where power supply noise directly translates to degradation

in system performance, power supply rejection (PSR) is a key figure of merit for a voltage regula-

tor. It is therefore imperative to analyze the PSR of linear regulators over a large frequency range,

specially in operating frequency of the system.

A typical PSR curve of a conventional LDO voltage regulator is shown in Fig. 3.21. At low

frequencies (DC), PSR is proportional to the DC open-loop gain of the error amplifier. The band-

width of the amplifier, the unity-gain frequency (UGF) of the system and the pole corresponding to

the output impedance impose different behaviours in the shape of the curve. The UGF provides

low supply-ripple rejection at a range of frequencies, starting to degrade the LDO performance

at error amplifier bandwidth. At high frequencies, the output capacitor (Cout) shunts any ripple

appearing at the output to ground. However, since the output capacitor has a series resistance

(RESR), the PSR is limited at very high frequencies [11].

Fig. 3.21: PSR curve of a conventional LDO voltage regulator.

Fig. B.6, B.7, B.8 and B.9 in the appendix B shows the line regulation simulated for all

corners. The PSR curves obtained has the same behaviour as the one in Fig. 3.21. As can be

seen, a good PSR at frequency of 13.5 MHz (working frequency of the system) can be achieved.

The summarized results are presented in table 3.9.

Tab. 3.9: PSR simulation results.

Condition PSR@DC [dB] [email protected] MHz [dB]Max. Vin & Max. Load -66.585 -51.628Min. Vin & Max. Load -38.916 -33.086Max. Vin & No Load -68.73 -85.202Min. Vin & No Load -66.484 -82.229

29


Line and Load Regulation Line Regulation simulation tests the ability of the system to maintain

the output voltage with all the possible values of the input voltage, ie:

Line Regulation =4Vout4Vin

. (3.3.4)

In Figure 3.22 is possible to see that while the input voltage varies from approximately 3.5

V (≈ 200 mV )to 10 V the output voltage remains at approximately 3.3 V.

Fig. 3.22: LDO Line Regulation response with full and no load.

The Line Regulation curves obtained to all corners are shown in Fig. B.10 and B.11 in the

appendix B.

Load regulation characteristics are not symmetrical for increase and decrease in load cur-

rent. In the proposed circuit, when load current is increased instantaneously, the load capacitor

supplies the extra current and the capacitor voltage drops. This drop in output voltage is sensed

by the feedback circuit which in turn pulls down the gate of the PMOS pass transistor thus turning

it on and supplying the output current needed by the capacitor and load impedance. When the

load current is decreased instantaneously, the extra current from the output of the pass transis-

tor charges the output capacitor to a higher than nominal voltage. The feedback loop reacts by

switching the error amplifier to positive saturation limit thereby turning off the pass transistor. The

excess charge on the output capacitor is discharged through the feedback resistors; hence the

discharge time is large because R1 and R2 have a high dimension.

Load regulation simulation tests the ability of the system to maintain the output voltage in all

30


output current conditions, ie:

Load Regulation =4Vout4Iout

. (3.3.5)

In Fig. 3.23(a) and 3.23(b) is possible to see that while the output current varies from 4 uA

to 40 mA the output voltage has an absolute variation of 0.25%. This small variation is greatly due

to the high loop gain at low frequencies which decreases the output.

(a) Max. Vin.

(b) Min. Vin.

Fig. 3.23: LDO Load Regulation response

31


3.4 Synopsis

Power management is a very important issue in portable electronic applications. Thus, the

input signal on secondary side of transformer must be rectified and regulated to generate the

desired voltage levels needed to supply all the blocks of the implantable system.

Using the RF transformer optimized in previous chapter, two topologies of class E rectifiers

were studied and compared. Both topologies used a Schottky diode, due to its low forward voltage

drop and very fast switching action. As the voltage level in input of the rectifier signal is higher than

the voltage level allowed by the technology, the rectifier circuit cannot be produced in integrated

circuit.

A class E rectifier with a series capacitor or zero-voltage-switching mode, minimize the

power losses since the turn-on and turn-off switching are realized with low dvdiode/dt. This circuit

acts as a step-down AC-DC convertor. By his side, a class E rectifier with a parallel inductor or

zero-current-switching mode, minimize the losses since the turn-on and turn-off switching are

realized with low didiode/dt. A large conduction angle and a smooth waveform of the diode

current reduce harmonics and noise at the output of the rectifier. The obtained results allowed

realize that the combination RF transformer with series resonance in secondary side more the

class E ZVS or ZCS rectifier have greater efficiencies (respectively 33.6 % and 34.7 %).

These results were verified with Spectre simulations using the PSpice software.

The proposed LDO is a 3.5 V 40 mA capacitor CMOS regulator for system-on-chip applica-

tions , implemented in a standard 0.35 µm CMOS technology. The transistors used in the LDO

design are all high voltage because low voltage transistors can only stand a maximum of 3.6 V

level voltage in its nodes.

Of all the types of voltage regulators, low-dropout regulator (LDO) is regarded as a suitable

choice for local on-chip voltage regulation in SoC, due to its fast transient response and low-noise

advantages.

The design variables such as consumption, loop gain and output capacitor are chosen to

improve the performance of the LDO versus the implicit trade offs. These results were verified

with hspiceD simulations using the AMS kit of Cadence software.

The final characteristics of the LDO designed are presented in Table 3.10.

32


Tab. 3.10: Summarized LDO characteristics.

Parameter Min. Typ. Max.Startup Time [µs] 5.7 - 16

Current Consumption [µA] 20.44 - 20.49Vout - Line Regulation [V] 3.3071 3.3 3.3125Vout - Load Regulation [V] 3.308 3.3 3.311

Phase Margin with load [deg] 74 - 123Phase Margin without load [deg] 47 - [email protected] MHz with load [dB] -33 - -52

[email protected] MHz without load [dB] -82 - -85Cout [nF] - 100 -

33


34

4Data Receiver


4.2 Phase Locked Loop Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2.1 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.3 Voltage-Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.2.5 PLL Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3 Phase Locked Loop Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4 IC test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.5 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

35

CHAPTER 4. DATA RECEIVER

4.1 Motivation

The data receiver at secondary side of transformer will be processed, to generate the ap-

propriate voltage levels to activate the electrode array implanted in the visual cortex. Thus, it is

necessary to demodulate the data from primary side of transformer.

The data transmitted by the RF resonant transformer is modulated in frequency (FSK) which

provides good immunity to noise and to the severe amplitude fluctuations due to the transformer

weak coupling. The bit rate expected of the signal sent to the receiver is 1.25 Mbps and it is

modulated on a carrier with a frequency of 13.5 MHz. To perform this demodulation a low power

PLL was implemented to simultaneously recover the clock and data [12]. The PLL is one of the

most critical circuits in terms of dissipation of energy in the secondary system.

4.2 Phase Locked Loop Circuit Design

A Phase Locked Loop or a PLL is a feedback control circuit. The PLL implemented consists

of four fundamental functional blocks: a phase detector (PD), a charge pump, a loop filter and

a voltage controlled oscillator (VCO); with the circuit configuration shown in Fig. 4.1. Different

topologies for VCO and PFD have been investigated over the years ([4], [13], [14] and [15]). The

PLL implemented was based in [4], had as the main purpose the CMOS integration.

The phase detector compares the phase of the output signal with the phase of the reference

signal. The mean value at output of phase detector is a measure of the phase difference between

these two signals. This error signal is then generated to a charge pump that generate a current

which passes through the loop filter and provide a certain voltage level to control the VCO. The

control voltage on the VCO changes the frequency to reduce the phase difference between the

input signal and the local oscillator. In the synchronized or locked state, the phase error between

the output signal and the input signal is zero or very small. If a phase error builds up, a control

mechanism changes the output signal in such a way that minimizes the phase error with the input

signal. The period of frequency acquisition can be very long or very short, depending on the

bandwidth of the PLL, that depends on the characteristics of the PD, VCO and the loop filter.

In the next sections, is described the PLL intern structures and the main results obtained.

At last, the overall loop operation and PLL bandwidth will be analyzed.

Fig. 4.1: Basic block diagram of the PLL implemented.

36


4.2.1 Phase Detector

As reported earlier,the phase detector compares the phase between the digital input signal

and the VCO digital output signal to generate an error signal which is proportional to their phase

difference.

The most commonly phase detectors used in these applications are the sequential phase

detectors. One of them is the Phase Frequency Detector (PFD) that ensures frequency and

phase-lock by itself (its output signal depends not only on phase error, but also on frequency

error, when the PLL has not yet acquired lock) [13].

The block diagram of the PFD is presented in Figure 4.2. It consists of two D-type flip-flops

(D-FF) which have their D inputs connected to the VDD. Under this condition, the flip-flop with a

low Q output will transit to high at the next rising edge of its clock input. The upper D-FF, which is

clocked by clk_re f generates the up signal, while the lower D-FF clocked by clk_vco generates the

down signal. The NAND gate monitors the up and down signals and generates the reset signal

for the D-FFs when both outputs become active. The up and down signals are used to switch the

current sources in the charge-pump circuit.

Fig. 4.2: Block diagram of a sequential PD (PFD).

If the frequency of the input clk_re f is lower than the frequency of input clk_vco, the PFD

generates positive pulses at the output of the upper D-FF, while the output of the lower D-FF

remains at zero (during the positive time of clk_vco). Same is true for the other case, when fclk_re f

is higher than fclk_vco positive pulses appear at the lower D-FF, while the upper D-FF remains at

zero. The width of the pulses is equal to the phase difference between the inputs at clk_re f and

clk_vco. If fclk_re f = fclk_vco, then no pulses appear at both outputs.

The actual state of the PFD is determined by the positive-going transients of the signal at

input and output of the phase detector, as explained by the state diagram present in Fig. 4.3. A

positive transition of the signal clk_re f forces the PFD to go into its next higher state, unless it is

already in the state 1. In analogy, a positive edge of clk_vco forces the PFD into its next lower

37


state, unless it is already in the state 2. The error phase is a ternary signal of the PFD state.

Fig. 4.3: PFD state diagram.

In Fig. 4.4 and Fig. 4.5 are shown the simulation results of PFD using (Cadence Spectre

circuit simulator), which demonstrates the mode of operation explained above.

Fig. 4.4: Input signals (clk_re f and clk_vco) and output signals (up and dw)from phase detector.

The main advantage of this phase detector topology is its compactness. However, the

replacement of the conventional static logic circuitry by dynamic logic gates, leads to a reduction

of the number of transistors in the PFD ([15] and [14]). This new circuit for phase-frequency

detector is shown in Fig. 4.6 (see Appendix D).

When the phase difference of reference clock and VCO clock is smaller than the dead zone,

the PFD cannot detect this phase difference. So the phase error signal of PFD will remain zero,

resulting in unavoidable phase error between the two clocks. Thus, the PFD asserts both up and

down outputs as shown in Fig. 4.7 to avoid dead zone. For in-phase inputs, the charge pump

will see both up and down pulse for the same short period of time. If there is a phase difference

between reference and VCO clocks, the width of up and down pulse will be proportional to the

38


Fig. 4.5: Input signals (clk_re f and clk_vco) and output signals (up and dw)from phase detector,when both the signals have the same frequency, but lagged one of another.

phase differences of the inputs.

The PFDs explained previously are to be used in PLL to realize the clock recovery. To

perform the data recovery is necessary a particular PD, namely the Hodge Detector [[12]]. In

Fig. 4.8 is presented the schematic of this PD, which output give a retimed data according to the

respective clock signal. This block consists in a register active during the positive state of the

clock and a latch D active only on rising edge of the clock.

Fig. 4.9 shown the main operation of this phase detector, that allow to obtain a output signal

synchronized with the clock recover by the PLL.

4.2.2 Charge Pump

The up and down signals of the PFD are used to switch the current sources in the charge-

pump (Fig. 4.10) ([[4]], [[13]] and [[15]]). When up signal is active, a current with magnitude of

Icp is sourced by the charge-pump. Conversely, when down signal is active, current is retired

from the charge-pump. When up and down are inactive at same time, no current flows into or

out the output node of the charge pump. The output is in a high impedance state and no noise is

generated in VCO.

The designed charge pump consists of current sources namely MN0 and MP0 with MN1

and MP1 current mirror sources (that defines the bias current Ire f ), which feed current mirror

39


Fig. 4.6: Dynamic PFD circuit.

Fig. 4.7: Graphics of UP and DOWN pulse with variation as a function of input phase difference.

Fig. 4.8: Block diagram of Hodge phase detector (Linear PD).

40


Fig. 4.9: Graphic with the simulation result of Hodge phase detector operation.

Fig. 4.10: Basic schematic of charge-pump and low pass filter of PLL implemented.

transistors MN3 and MP3 (Fig. 4.11 and Appendix (D)) [15]. These are connected to loop filter via

the switches (consists of MN2 and MP2). The use of a cascode configuration in current sources

allow a higher load impedance (lower current level) and reduced noise coupled from power supply.

Each switch is now separated of output by one current sources to minimize the noise vc, caused

by charge and discharge the capacitors when switches are opened or closed.

41


Fig. 4.11: Schematic of charge-pump implemented.

Thus, it is possible the following relationship between the various currents of charge pump:

I1 = Ire f ×(W/L)MP1(W/L)MP0

[µA]

I2 = I1 ×(W/L)MP3(W/L)MP0

[µA]

I3 = I1 ×(W/L)MN3(W/L)MN1

[µA]

(4.2.1)

The designed CMOS model of the charge pump with discharging/charging current has an Icp =

20uA.

The signal Ip is thus a logical function of the PFD state. When PFD is in state 1, Icp must

be positive, and when PFD is in state 2, Icp must be negative. For state 0, the Icp will be zero.

Thus, the relation Icp versus phase error (θe) has a sawtooth function as shown in Fig. 4.12.

The curve is linear between −2π to 2π, and then repeats every 2π. If the phase error θe

exceeds 2π, the PFD behaves as if the phase error is rotated back to zero. Now, the gain of PFD

can be calculated and is given below

Kpd =Icp

2π[µA/rad] . (4.2.2)

42


Fig. 4.12: Plot of the function Icp vs. phase error θe.

4.2.3 Voltage-Controlled Oscillator

A voltage controlled oscillator (VCO) is a circuit whose output frequency f0 depends to the

control voltage, vctrl, generated by phase error detected at phase detector’s output.

Most commonly VCO used in PLL clock recovery designs is the ring oscillator ([4] and [15]),

due to it simplicity, easy IC integration and wide tuning range. The choice of the ring oscillator is

because of differential pair which is immune to common mode voltage. Moreover, the differential

cells used allow a high rejection to noise generated in the substrate, and to variations in supply

voltage. Thus, it is possible to minimize the PLL output jitter, since the dominant noise in a PLL is

generated by the VCO and the phase comparator.

In a ring oscillator, the periodic signal is generated by a ring of inverters. The oscillation

period will be 2ntd, where n is the number of inverters in the ring and td the delay of one inverter.

Normally, the number of inverters in the loop must be odd and larger than one, but differential in-

verters permit the use of even number of inverters since the feedback of the ring remains positive.

Frequency tuning is possible by varying the current that the inverters use to charge their

load capacitance. The more inverters the ring has, the lower is the range oscillation frequency of

VCO. The implemented VCO has 9 inverters to obtain a central frequency of 13.5 MHz (see Fig.

4.13).

Fig. 4.13: Block diagram of the ring oscillator with 9 inverters

Each stage, shown in Fig. 4.14, contains a source coupled pair with resistive load elements

called symmetric loads (see Appendix D). Symmetric loads consist of a diode-connected PMOS

device in shunt with an equally sized biased PMOS device.

43


Fig. 4.14: Schematic of source coupled delay with symmetrical loads.

Before VCO’s block, itself, there is a bias circuit (Fig. 4.15) which gives a voltage vbn

and generates another called vbp. The voltage vbp controls the load resistance of the VCO’s

basic cell while voltage vbn controls the current passing through it, which makes the VCO less

sensitive to the different technology processes, since it reduces the noise induced by source and

substrate. Signal vbn (replica vctrl) is directly proportional to VCO’s oscillation frequency, since

vbp is constant. The bias circuit is a half-buffer replica of the delay cell (Fig. 4.13 and Appendix

D).

Fig. 4.15: Schematic of the bias cell that provide the vbn voltage.

44


Additionally, there is a differential-to-single-ended converter (Fig. (4.16)) to obtain a square

wave that derivate of differentials signals in VCO’s output. The circuit consists of two differential

amplifiers in opposite phases with active loads, whose outputs are connected to the transistors

MP4 and MP5 (see Appendix D). For the converter to feel the voltage signal in same way that the

oscillator, it was made, so that they have the same current Id and in general the same voltages

in its nodes. Its output however are more amplified than the cell delay, as active loads formed out

of the PMOS transistors have a higher equivalent impedance (for all the current passes through

a transistor instead of two symmetrical in cell delay). In the output, was put a drive to serve as a

buffer so that the operation of folowing circuits do not interfere with the operation of the block.

Fig. 4.16: Schematic of the differencial-to-single-ended converter used with the ring oscillator.

The operation range of the ring oscillator is equivalent to the band of output frequencies;

which in the design is 6 MHz - 33 MHz with a center frequency of 13.5 MHz, as pretending in this

project (see Fig. 4.17).

Since voltage range is restricted to 0.1 V - 3.3 V, the VCO gain can be determined with the

aid of Fig. 4.18.

So the VCO gain is

K0 (ring VCO) =4ω0

4vctrl=

2π (33− 6) Mrad/s(3.3− 0.1)V

≈ 53 Mrad/sV. (4.2.3)

Another popular method for perform digital-output VCOs in CMOS technology is a CMOS

relaxation oscillator, particularly similar to the 555 VCO ([13] e [15]). The schematic is present in

Fig. 4.19 and Appendix C, Fig. C.1. See Appendix D to know the transistores sizes.

In this topology the capacitor C is discharged or charged by a voltage controlled current

mirror (the control voltage is generated in charge-pump circuit and then filtered - vctrl). The

45


Fig. 4.17: Graphic simulation of response of ring oscillator to a vctrl = 1.5.

Fig. 4.18: Graphic of ring oscillator gain.

46


Fig. 4.19: Basic block diagram of a similar 555 type VCO.

voltage remaining in capacitor (vc) is compared with a reference voltage (vre f ) to decide if the

capacitor must be charged or discharged. The reference voltage is given by a resistor chain.

In Figure 4.20 is described the main behaviour of this VCO, ie:

0 -vc ≤ vre f− ⇒ vo− =′ 1′ e vo+ =′ 0′ ⇒ vout =′ 0′ ⇒ vre f = vre f+⇒ charge C;

1 -vre f− < vc < vre f+ e vi− > vc⇒

vo− =′ 1′ and vo+ =′ 0′ ⇒ vout =′ 0′ ⇒

vre f = vre f+⇒ charge C;

2 -vc ≥ vre f+⇒ vo− =′ 0′ and vo+ =′ 1′ ⇒ vout =′ 1′ ⇒ vre f = vre f− ⇒ discharge C;

3 -vre f− < vc < vre f+ and vi− < vc⇒

vo− =′ 0′ and vo+ =′ 1′ ⇒ vout =′ 1′ ⇒

vre f = vre f− ⇒ discharge C.

Fig. 4.20: Illustration of the 555 VCO’s capacitor charge/discharge operation.

The current that passes trough the capacitor, Ic, is given by

4Vctrl =IcC× trampa [V] , (4.2.4)

where 4Vctrl = 3.3− 0.6 = 2.7 V and t = 37 ns since f = 13.5MHz.

47


The operation range of the relaxation VCO is equivalent to the band of output frequencies;

which in the design is 900 kHz - 40 Mhz. Since voltage range is restricted to 0.6 V - 3.3 V, with a

center frequency of 13.5 MHz, as pretending in this project (see Fig. 4.21).

Fig. 4.21: Graphic simulation of response of 555 type VCO to a vctrl = 1.5.

As the previous VCO, the 555 type VCO gain can be determined with the aid of Fig. 4.22.

Fig. 4.22: Graphic of relaxation VCO gain.

So the VCO gain is

K0 (555 VCO) =4ω0

4vctrl=

2π (40− 0.9) Mrad/s(3.3− 0.6)V

≈ 90 Mrad/sV. (4.2.5)

48


4.2.4 Loop Filter

The design of the PLL loop filter is the main tool in selecting the bandwidth of the PLL. The

voltages generated by the PFD allow to control two switches, acting on the charge and discharge

of the LPF capacitor, ie the average value of PFD’s output is obtained from deposition of charges

in the capacitor. Since higher order loop filter offer better noise cancellation, a loop filter of order

3 (two capacitors) is used. The designed loop filter configuration is shown in Fig. 4.23.

Fig. 4.23: Schematic of a second-order low pass filter.

The transfer function [[15]]of the loop filter is

Z f (s) =1 + sτ1

s (C1 + C2) (1 + sτ2), where (4.2.6)

τ1 =

√b

ωcand τ2 =

1√bωc

(4.2.7)

Thus, the values for resistor and capacitors of the loop filter are calculated by the folowing equa-

tions:

R1 =2πωc

Icp2πK0

bb− 1

; C1 =τ2

R1; C2 =

1R1

τ2τ3

τ2 − τ3; (4.2.8)

where b is a measure of stability which relates with phase margin (φm) by the equations explained

in Appendix E and ωc the PLL open-loop bandwith.

In Table 4.1 are shown the values of each element of the low pass filter, for the two VCO’s

implemented. These values are calculated considering that PLL have a φm = 60 and conse-

quently b = 13.93 (see Appendix E). For the dimensioning of the PLL loop for data recovery, the

cutoff frequency of loop filter is 1.25 MHz (ωc1). The choice of the poles and the zero was to

achieve a rapid acquisition to respond to the high rate of transmission (1.25 Mbit / s). In clock

recovery, a central frequency of 13.5 MHz was chosen. The loop filter is dimensioned to have a

cutoff frequency of 10 kHz (ωc2).

The filter implemented contains the minimum values of R and C’s. Externally is placed in

49


Tab. 4.1: Low pass filter elements values for the two cutoff frequencies and two VCOs.

ωc1 ωc2τ1[ns] 475 τ1[us] 59.4τ2[ns] 34.1 τ2[us] 4.27

VCO_ring VCO_555 VCO_ring VCO_555R1[kΩ] 49.1 28.5 R1[Ω] 393 228C1[pF] 9.67 16.7 C1[nF] 151 261C2[pF] 0.748 1.29 C2[nF] 11.7 20.2

parallel the additional elements to obtain the exact values for the desired frequencies.

4.2.5 PLL Performance Summary

Fig. 4.24 shows a simulation result of the PLL loop capture.

Fig. 4.24: Loop capture process of PLL.

The main features of the CMOs PLL are shown in Table 4.2.

The power consumed of the PLL was calculated using the current fonts provided by the

various blocks. The consumption of each one is in the Tab. 4.3.

50


Tab. 4.2: Summarized PLL characteristics.

Technology 0.35 µm CMOSSupply Bias 3.3 V

Operating Frequency Range ring oscillator 6 MHz - 33 MHz555 VCO 900 kHz - 40 MHz

Area 130 µm × 330 µm (without pads)

Tab. 4.3: Power consumption of each block of PLL.

Block Power Dissipation [mW]PDF typical 2.758

PDF 2.079Hodge Detector 1.737Charge Pump 0.138Ring oscillator 1.766

555 VCO 0.698

4.3 Phase Locked Loop Layout

The layout of the PLL was developed for 0.35 µ m CMOS technology to be integrated in

ICONS project as mentioned in chapter 2. The PLL complete circuit contains the three phase

detectors, the charge-pump, the low pass filter, the two VCOs and a logic circuits (mutiplexers

and switches) to select the VCO and PD in test (see Appendix C, Fig. C.3).

The layout was realized taking into account some considerations:

- All the transistors that require matching were design in layout as near as possible to min-

imize any gradient variations of the fabrication process. The wide transistors are composed by

smaller transistors in parallel called fingers.

- The resistors used in the layout are all designed using highly resistive poly-resistors that

can be implemented in an acceptable area and present a relatively high precision.

- Many contacts and vias at polly and metals are used in order to reduce voltage drop and

resistance.

The final Layout for the PLL can be seen in Fig. 4.25, and uses 42.9 nm2 of area in a

rectangular shape. There are 12 pads to test the folowing circuit inputs/outputs: in, out, data,

vctrl, up, dw, bit_PFD (to select one of the three phase detectors), bit_VCO (to select one of the

two VCOs), avdd, agnd, dvdd and dgnd. The need of two pairs of separated supplies (avdd, agnd,

dvdd and dgnd) is to minimize the effect of noise between the various blocks of PLL (usually the

noise of digital circuits in analog circuits).

For all blocks the layout is verified by verification tools and meets all the rules. These rules

were taken into account in the design of the layout and they specify the minimum or the maximum

distances and dimensions between the masks. The program used for layout design was Virtuosoo

from Cadence tools.

51


Fig. 4.25: Layout of low power PLL implemented.

4.4 IC test

To test the implemented PLL, the die was encapsulated and the wire-bonding between pads

and the pins of the dual-in-line package was made.

The chip was placed on a PCB (Printed Circuit Board) to perform the test of each block of the

PLL and PLL test itself. The PCB was performed primarily by image transference processes, using

ultra-violet radiation and exposure by chemical baths. Finally, there was realized the corrosion of

the metallic surface by dipping the PCB in a solution of iron perchlorate.

Fig. 4.26 shows the PCB implemented to test the PLL chip. This circuit contains logic to

select the VCO and the PFD to use and the extern filter. The schematic is found on Appendix C,

Fig. C.2.

Fig. 4.26: Foto of the PLL PCB.

52


4.5 Synopsis

This chapter presents the design of a low power charge-pump PLL in a 0.35 µm CMOS

technology. A PLL is a circuit that synchronizes an output signal with an input signal in frequency

as well as in phase and is used in this work to perform data and clock recovery. All the PLL

building blocks including the VCO, PFD, charge pump and a loop filter are designed to operate

with low power and to minimize the active area.

Several performance aspects of the PLL, such as the frequency pull-in range, the noise and

the spurious signals are dependent on the type of phase detector. Because the output signal of

the PFD depends on phase error in the locked state of the PLL and on the frequency error in the

unlocked state, a PLL that uses the PFD will lock under any condition, irrespective of the type

of loop filter used. For this reason the PFD is the preferred phase detector in PLLs. For data

recovery was implemented a particular PD that gives in its output the synchronized data with the

clock.

One of the VCOs used in the design is a nine-stage differential-type ring. A major design

challenge for integrated VCOs is to have a large tuning range to be able to compensate for tem-

perature and process variations in the device parameters. Ring oscillators are among the popular

structures for VCOs due to their wide tuning range and amenability to integration. The other VCO

is a relaxation oscillator, as the 555 type VCO is often used in monolithic integration, and capable

of high speeds.

The PLL implemented occupies 130 x 330 µm, has a lock range of 27 MHz (from 6 MHz to

33 MHz) in case of ring oscillator and 39.1 MHz (from 0.9 MHz to 40 MHz) in case of 555 type

VCO, which is within the frequency band defined by the ICONS project. The preliminary tests to

the PCB were made.

53


54

5Conclusions

Contents5.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

55

CHAPTER 5. CONCLUSIONS

Monitoring cortical activities and microstimulating some regions of the cortex are becoming

necessary to learn more and to allow the regain neuronal specific functions, such as vision for the

blind. Two main issues for implantable sensors are long-term biocompatibility and power man-

agement. Electronic circuit using CMOS technology is one of the best candidates for designing

the signal processing part due to its low power consumption and small size.

In this work, the cortical monitoring system implemented in the project ICONS is described.

This system is composed of two main parts: an external controller and an implant. In order to

link external and internal blocks a RF resonant transformer are presented and analysed. Its archi-

tecture was explained, the main problems found in the wireless energy efficiency are discussed

and the experimental results are presented. As seen, the RF wireless transformer in parallel with

resonant capacitor has the best efficiency performance (83.21 %).

Then, a Schottky diode rectification is used to obtain the DC voltage needed to activate

the microelectronic circuits. It was used two different topologies for RF transformers previously

optimized. The obtained results allowed realize that the combination RF transformer with series

resonance in secondary side more the class E ZVS or ZCS rectifier have greater efficiencies

(respectively 33.6 % and 34.7 %). The rectifier topology with an inductor on the cutoff filter still

remains resonant at working frequency.

To regulate this DC voltage a LDO voltage regulator was proposed. The LDO is 200 mV

(dropout voltage) 40 mA (maximal current) capacitor (C = 100 nF) CMOS regulator for system-on-

chip applications , implemented in a standard 0.35 µm CMOS technology. The entirely block has

a maximum current consuption of 20.49 µA. The simulation results for Line and Load Regulation

are: 3.3071 V and 3.308 V in minimum; 3.3125 V and 3.311 in maximum, respectively. The

LDO is stable for all cases with 47 deg in the worst case (without load and minimum Vin). The

simulated [email protected] MHz is -33 dB in the worst case (with load) and -85 dB as maximum value.

This design variables such as consumption, loop gain and output capacitor are chosen to improve

the performance of the LDO versus the implicit trade offs.

The system uses FSK modulation in data transference which provides better immunity to

noise and to the severe amplitude fluctuations due to the transformer weak coupling. A PLL was

implemented to simultaneously realize the data and clock recovery.

The PLL was designed with two types of VCOs and two different topologies for the PFD.

Several performance aspects of the PLL, such as the frequency pull-in range, the noise and the

spurious signals are dependent on the type of phase detector. Because the output signal of the

PFD depends on phase error in the locked state of the PLL and on the frequency error in the

unlocked state, a PLL that uses the PFD will lock under any condition, irrespective of the type

of loop filter used. For this reason the PFD is the preferred phase detector in PLLs. The data

demodulation is done through the same PLL, using a phase detector that has in its output the

56


synchronized data with the desired clock signal.

Ring oscillators are among the popular structures for VCOs due to their wide tuning range

and amenability to integration. The other VCO is a relaxation oscillator, as the 555 type VCO is

often used in monolithic integration, and capable of high speeds.

The layout area occuped has 130 x 330 µm, has a lock range of 27 MHz (from 6 MHz to

33 MHz) in case of ring oscillator and 39.1 MHz (from 0.9 MHz to 40 MHz) in case of 555 type

VCO, which is within the frequency band defined by the ICONS project (contains the working

frequency at 13.5 MHz). During thesis time, an IC chip (0.35 µm CMOS technology) of this circuit

is manufactured and the preliminary tests were made. It is confirmed that the PDs operates

properly.

In this work most of the results respects to the pretended goal, being the main objective the

integrated solution.

5.1 Future Work

In the future, to improve this work, some alterations could be done.

The LDO voltage regulator can be realized using a capless topology, to minimize the external

components in implant. With layout design, more corners simulations should be done. The major

concerns in this type of circuits are: fast response, consumption, PSRR and area. These are

relevant aspects, that the future work should focus on, in order to achieve better tradeoffs with

new technologies.

The test of the PLL chip must be fully realized and the results analysed to achieve a better

performance of the block.

Finally, could be tested the complete system of implant (with thw interaction of all blocks:

transformer, rectifier, LDO and PLL).

57


58

Bibliography

[1] M. Santos, J. R. Fernandes, and M. S. Piedade, “A microelectrode stimulation system for a

cortical neuroprosthesis,” Nov. 2006.

[2] S. Patri and K. S. R. KrishnaPrasad, “Self compensating ON chip LDO voltage regulator in

180nm,” Proceedings of World Academy of Science, vol. 34, 2008.

[3] G. Vandevoorde and R. Puers, “Wireless energy transfer for stand-alone systems: a com-

parision between low and high power applicability,” 2001.

[4] E. G. Varela, “Transmissão de sinais e de energia eléctrica para prótese visual intracraniana

utilizando a modulação ASK,” Graduation Thesis, IST, Oct. 2003.

[5] M. J. Martins, “Transmission of data and power to an intracranial retinal prosthesis,” Gradua-

tion Thesis, IST, 2003.

[6] G. B. Hmida, H. Ghariani, and M. Samet, “Design of wireless power and data transmission

circuits for implantable biomicrosystem,” 2007.

[7] M. Kazimierczuk and W. Szaraniec, “Analysis of a class e rectifier with a series capacitor,”

Circuits, Devices and Systems, IEE Proceedings G, vol. 139, no. 3, pp. 269–276, 1992.

[8] J. Jozwik and M. Kazimierczuk, “Class e zero-current-switching rectifier with a parallel induc-

tor,” in Aerospace and Electronics Conference, 1989. NAECON 1989., Proceedings of the

IEEE 1989 National, 1989, pp. 233–239 vol.1.

[9] C. Gong, K. Yao, Y. Huang, and M. Shiue, “An efficiency-enhanced CMOS voltage regulator

module for bio-electronic implants,” in Circuits and Systems, 2008. APCCAS 2008. IEEE Asia

Pacific Conference on, 2008, pp. 121–124.

[10] M. Ahmadi and G. Jullien, “A full CMOS voltage regulating circuit for bioimplantable applica-

tions,” in Circuits and Systems, 2005. 48th Midwest Symposium on, 2005, pp. 988–991 Vol.

2.

59

BIBLIOGRAPHY

[11] V. Gupta, G. Rincon-Mora, and P. Raha, “Analysis and design of monolithic, high PSR, linear

regulators for SoC applications,” in SOC Conference, 2004. Proceedings. IEEE International,

2004.

[12] M. H. Perrott, PLL Design Using the PLL Design Assistant Program, 2005.

[13] D. A. Johns and K. Martin, Analog Integrated Circuit Design. R.R. Donnelley/Crawfordsville,

1997.

[14] S. Kim, K. Lee, Y. Moon, D. Jeong, Y. Choi, and H. K. Lim, “A 960-Mb/s/pin interface for

skew-tolerant bus using low jitter PLL,” Solid-State Circuits, IEEE Journal of, vol. 32, no. 5,

pp. 691–700, 1997.

[15] C. S. Vaucher, K. Lee, Y. Moon, D. Jeong, Y. Choi, and H. K. Lim, Architectures for RF

frequency synthesizers. Kluwer Academic Publishers, 2003.

[16] “PSpice A/D and advanced analysis.” [Online]. Available: http://www.cadence.com/products/

orcad/pspice_simulation/pages/default.aspx

[17] A. Sedra and K. Smith, Microelectronic Circuits, fifth edition ed. Oxford University Press,

Sep. 2007.

60

http://www.cadence.com/products/orcad/pspice_simulation/pages/default.aspx

http://www.cadence.com/products/orcad/pspice_simulation/pages/default.aspx

ALDO Transistors Sizes

Tab. A.1: Error Amplifier transistors sizes.

Transistor W [ µm ] L [ µm ] ng

MP0 2 3 2

MP1 2 3 2

MN0 2 3 2

MN1 4 0.5 4

MN2 64 1 1

MN3 64 1 1

Tab. A.2: Bias Unity transistors sizes.


MN0 2 10 2

MN1 4 0.5 4

MN2 2 3 2

MN3 4 0.5 4

61

APPENDIX A. LDO TRANSISTORS SIZES

Tab. A.3: Control Unity transistors sizes.


MN0 2 3 2

MN1 4 0.5 4

MN2 2 3 2

MN3 4 0.5 4

MN4 2.1 2 2

MN5 0.5 2 1

MN6 900 20 45

MP0 1 2 1

MP1 2 2 2

MP2 40 0.5 4

MP3 4 3 4

Tab. A.4: Power-Down transistors sizes.


MNPD0 2 0.5 2

MNPD1 2 0.5 2

MNPD2 4 1 4

MPPD0 2 0.5 2

MPPD1 2 0.5 2

MPPD2 2 1 2

MPPD3 8 5 8

MPPD4 4 1 4

62

BLDO Simulation Graphics

63

APPENDIX B. LDO SIMULATION GRAPHICS

Fig. B.1: LDO AC open-loop simulation with/without load and max/min Vin.

Fig. B.2: LDO output impedance evolution with full load and maximum Vin.

64


Fig. B.3: LDO output impedance evolution with full load and minimum Vin.

Fig. B.4: LDO output impedance evolution with no load and maximum Vin.

65


Fig. B.5: LDO output impedance evolution with no load and minimum Vin.

Fig. B.6: LDO PSR curve with full load and maximum Vin (for all corners).

66


Fig. B.7: LDO PSR curve with full load and minimum Vin (for all corners).

Fig. B.8: LDO PSR curve with no load and maximum Vin (for all corners).

67


Fig. B.9: LDO PSR curve with no load and minimum Vin (for all corners).

Fig. B.10: LDO Line Regulation response with no load (for all corners).

68


Fig. B.11: LDO Line Regulation response with full load (for all corners).

69


70

CPLL Schematics

71

APPENDIX C. PLL SCHEMATICS

Fig.C.1:

Schem

aticofa

similar555

typeV

CO

.

72


Fig.

C.2

:P

CB

sche

mat

icof

PLL

.

73


Fig.C.3:

Schem

aticofP

LL.

74

DPLL Transistors Sizes

Tab. D.1: PFD transistors sizes.

Transistor W [ µm ] L [ µm ]

MP0 5 0.4

MP1 5 0.4

MP2 5 0.4

MP3 5 0.4

MP4 5 0.4

MP5 5 0.4

MP6 5 0.4

MP7 5 0.4

MN0 5 0.4

MN1 5 0.4

MN2 5 0.4

MN3 5 0.4

75

APPENDIX D. PLL TRANSISTORS SIZES

Tab. D.2: Charge-Pump transistors sizes.


MP0 1 2

MP1 5 2

MP2 1 0.5

MP3 5 2

MN0 0.6 6

MN1 1 2

MN2 1 0.5

MN3 5 2

Tab. D.3: Bias delay cell transistors sizes.


MP0 15 4.5

MN0 4 5

MN1 8 0.5

Tab. D.4: Delay cell transistors sizes.


MP0 15 4.5

MP1 15 4.5

MP2 15 4.5

MP3 15 4.5

MN0 8 10

MN1 5 0.5

MN2 5 0.5

76


Tab. D.5: Differencial-to-single-ended converter transistors sizes.


MP0 15 4.5

MP1 15 4.5

MP2 15 4.5

MP3 15 4.5

MP4 0.4 1

MP5 0.4 1

MN0 8 10

MN1 5 0.5

MN2 5 0.5

MN3 8 10

MN4 5 0.5

MN5 5 0.5

MN6 0.5 0.35

MN7 0.5 0.35

77


Tab. D.6: 555 type VCO transistors sizes.


MP0 5 0.5

MP1 1 0.5

MP2 1 0.4

MP3 1 0.5

MP4 1 0.5

MP5 2 1

MP6 2 1

MP7 1 0.4

MP8 1 4

MP9 1 4

MP10 1 4

MN0 5 0.5

MN1 1 0.4

MN2 1 0.4

MN3 1 0.5

MN4 1 0.5

MN5 2 8

MN6 8 2

MN7 8 2

MN8 5 3

MN9 1 0.4

78

ELow pass filter auxiliary

calculations

79

APPENDIX E. LOW PASS FILTER AUXILIARY CALCULATIONS

The closed-loop transfer function of the third-order implemented PLL is

H(s) =θVCO(s)θre f (s)

=G(s)

1 + G(s)=

2πKpdZ f (s)KVCO

s + 2πKpdZ f (s)KVCO, (E.0.1)

where the open-loop transfer function G(s) is

G(s) = KpdZ f (s)2πKVCO

s. (E.0.2)

The phase of transfer function G(jω) (ψ(jw)) is

ψ(jω) = −π + arg(1 + jωτ1)− arg(1 + jωτ2) = −π + arctan(ωτ1)− arctan(ωτ2), (E.0.3)

and the point of zero derivative of the phase response will be called ωmax, given by

ωmax =

√1

τ1τ2. (E.0.4)

The value of the maximum phase advance

φmax = ψ(jωmax) + π (E.0.5)

can be calculated as a function of τ1, τ2 and b = τ1 τ2 by inserting (E.0.4) in (E.0.3),

φmax = arctan(

τ1 − τ2

2√

τ1τ2

)= arctan

(b− 1

2√

b

). (E.0.6)

Solving (E.0.6) for b as a function of φmax yields

b =1

(−tanφmax + 1/cosφmax) 2 (E.0.7)

If ωc is dimensioned to be equal to ωmax, then the phase margin φm equals the value of φmax.

Now can be found τ1 and τ2 as a function of b and ωc.

80

icons - intracortical neuronal stimulator graphic simulation of response of 555 type vco to a vctrl...

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