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Outlier Screening For Zero DefectIC Quality

Adit D. Singh

Electrical & Computer Engineering

Auburn Universityadsingh@auburn.edu

05/18/01 V4.3

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Outline

Many integrated circuits contain

fabrication defects upon manufacture

Die yields may only be 20-50% for high

end circuits

ICs must be carefully tested to screen out

faulty parts before integration in systems

Small latent defects that cause early life

failuremust also be eliminated

New screening methods address this

problem

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IC Testing is a Difficult Problem

Need 23

= 8 input patterns toexhaustively test a 3-input NAND

2Ntests needed for N-input circuit

Many ICs have > 100 inputs

Only a very few input combinations

can be applied in practice

2100= 1.27 x 1030

Applying 1030tests at 109per second (1 GHZ)

will require1021secs = 400 billion centuries!

3-input NAND

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IC Testing in Practice

For high-end ICs20-100 seconds of test time on very expensive

production testers

Several thousand test patterns applied

Test patterns chosen to detect likely faults

High economic impact

-total test costs are approaching total

manufacturing costs

Despite the costs, testing is imperfect

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How well must we test?

Approximate order-of-magnitude estimatesNumber of parts per typical system: 100

Acceptable system defect rate: 1% (1 per 100)

Therefore, required part reliability

1 defect in 10,000

100 Defects Per Million (100 DPM)Requirement ~100 DPM for commercial ICs

~500 DPM for ASICs

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How well must we test?

Assume 2 million ICs manufactured with 50% yield

1 million GOOD >> shipped

1 million BAD >> test escapes cause defective

parts to be shipped

For 100 BAD parts in 1M shipped (DPM=100)

Test must detect 999,900

out of the 1,000,000 BAD

For 100 DPM: Needed Test Coverage = 99.99%

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DPM Depends on incoming YieldTest Coverage: 99.99% (Escapes 100 per million defective)

1 Million Parts @ 10% Yield

0.1 million GOOD >> shipped

0.9 million BAD >> 90 test escapes

DPM = 90 /0.1 = 900

1 Million Parts @ 90% Yield

0.9 million GOOD >> shipped

0.1 million BAD >> 10 test escapes

DPM = 10/0.9 = 11

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Defect Clustering on Wafers

Defects on semiconductor

wafers are not uniformly

distributed but are

clustered

Local regions of low yield

can give high DPM

xx x

x

x x

Good die from Bad Neighborhoods must be

more carefully tested to ensure no test escapes

x

x

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IC Reliability: Early Life Failures

Manufacturing defects cause ICs to fail the

production test - Killer defects

- failing parts discarded following testing

ICs also experience significant early life or

infant mortality failuresReliability problem

Infant mortality results from Latent defects- manufacturing flaws undetectable at initial test

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Defect Types

Killer Defect

Latent Defect

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Resistive open due to unfilled via causing a

TDF [Madge et al, IEEE D&T 2003]

A Resistive Via with an unfilled Void

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Stress Testing

Infant mortality results from latentmanufacturing flaws that are undetectable

at initial wafer probe testing

Tested using accelerated life cycle orstress tests

Burn-in tests exercise circuits at elevated

voltages and temperatures for a few hoursup to a few days in temperature controlled

burn-in ovens

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Burn-in is Expensive

High end circuits have nanometer featuresizes and operate on low voltages

Stress voltages and temperatures must be

carefully (individually) controlled to avoiddamaging the circuits >> expensive ovens

Needed burn-in times are growing because

voltage/temperature stress levels can onlybe marginally increased from the nominal

Most ICs today cannot afford Burn-in!

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Long warrantees ( ~ 4 years)

High warrantee repair costs ($1000)

Large number of parts per auto

High volumes ( ~30 million US sales)

Requirement:

< 10 DPM

Zero Defects Quality

New Automotive Reliability Specs

Motivated by

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Focus: DPM Due to Latents

Assume Latent Defect Density

- 1% Killer Defect Density

Average No. (per die)

Killer Defects l 1.0 0.5 0.1 0.01Latent Defects 0.01 0.005 0.001 0.0001

Die Yield (e-l) 37% 60% 90% 99%Probability of Latent

0.01 0.005 0.001 0.0001

PPM Latents 10,000 5,000 1,000 100

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Poisson Yield Model

Assume Latent Defect Density

- 1% Killer Defect Density

Die Yield (e-l) 37% 60% 90% 99%Probability of Latent 0.01 0.005 0.001 0.0001

PPM Latents 10,000 5,000 1,000 100

DPM from Latents:Digital 10,000 5,000 1,000 100Analog (Latents 0.1%?) 1,000 500 100 10

Analog Parts

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Reliability Screening

Screening involves discarding parts on

suspicionwithout proof of functional error

Excessive yield lossif parts from bad

neighborhoods are completely discarded

* 100-1000X overkillbecause there is no

test information from the die itself

Outlier detection methods can screen out

potential reliability failures with less overkill

- but at higher test cost

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Exploiting parameter correlation

outlier" screening

Key Idea:

Analog circuit performance measures within die

or between nearby die on the wafer should becorrelated because of parameter matching

Any anomalies, even if within functional

specifications, indicate a defect which could bea test escape and fail in the field, or result in a

reliability problem

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Exploiting parameter correlation

for Reliability Screening

Application to

- Digital Delay Testing

- Analog Testing

Looks for an outlier electrical signature of a

latent defect

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Timing Tests

Two-pattern test vectors cause a change at

the outputs

Switching delayis the time from the application

(launch) of V2 until change at the output

Worst caseswitching delay < clock period

V1

V2

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Limitation of Testing for TimingFails at Functional Clock Rate

Timing margins to allow for parametervariations, clock skew, variations in testconditions can make small defects

undetectable.

critical path

Timing Margin

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minVDD Testing

minVDD Testing finds the lowest VDD for

which the circuit passes a transition delay

fault (TDF) test for a given clock speed

An abnormal minVDD value with respect to

the expected value for the lot/neighborhood

indicates a defect that may be a test escapeor reliability failure

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minVDD Testing

minVDD is found by repeatedly running the

test vectors at different VDD voltages and

performing a binary search until the failingvoltage is identified within desired accuracy

Since binary searches on full vector sets can

be expensive, methods have been developedto work with reduced test sets.

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MinVDD Test

Reducing VDD slows the gates andincreases circuit delay until the circuit failsat the rated clock

A delay defect can make it fail earlier,

exposing hidden latent defects

critical path

Timing Margin

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MinVDD vs Device SpeedTwo different lots showing min VDD outliers and lot-to-lot intrinsic variation.

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Minimum VDD results for different functional testsclearly showing min VDD outliers (circled)

minVDD Testing

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Applying Outlier Screening toAnalog Parts

Outliers Screening with Multiple-

Parameter Correlation Testing for

Analogue ICs

Liguan Fang, Mohammed Lemnawar and Yizi Xing

Automotive Business Line

Philips Semiconductors

Nijmegen, The Netherlands

European Test Symposium, Southampton May 2006

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Outliers Screening with Multiple-Parameter Correlation Testing for

Analogue ICsGoal:

Achieve zero-defect product quality in

automotive application through outlier

screening

In Vehicle Network Communication IC

(interface between the protocol controller and

the physical bus)

H M lti l P t C l ti

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How Multiple-Parameter CorrelationTesting Works for Analog ICs

Specifications can have wide limits to allow fornormal process based parameter variations

However parameters within the same device

trackOne test result can often be more tightly

predicted based on others for the same part

- Two identical channels have matched gain- Blocks using the same core amplifier layout

should have measured gain reflecting the

feedback ratios

H M lti l P t C l ti

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How Multiple-Parameter CorrelationTesting Works

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Block Diagram of the test Vehicle

In Vehicle Network Communication IC

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Correlation in transmitter performancein two modes (A+B and A+C)

FA indicates 10% of field returns caused by

particle defects at C4 and C5

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Correlated Tests 540 and 550

Test 540: Blocks A and C active

Test 550: Blocks A and B active

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New Test 555

Test 555 = Test 550 - 0.35 * Test 540 + 57.94Mean value (from data) 0; standard deviation 2.2

6 Sigma Test limits for Test 555 = [-13.2, 13.2]

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Verification based on historic data logs

One 6-sigma New Test 555 outlier out of 160K

devices tested and passed over 4 months

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Test introduced in Production

Six screened parts in Batch A, mostly from

expected wafer locations: near wafer edge or nearother failed die

Defects observable in 4 out of 6 cases using only

visual inspection with microscope

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Defect Visualization

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Defect Visualization

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Defect Visualization

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Reduction Trend in Customer Returns

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Conclusions(Philips)

Virtually all the Outliers could be traced tophysical defects suggesting the potential for

reliability failure and customer returns

Reduction is customer returns sinceintroducing the test is strong evidence of its

effectiveness

The correlation test needs only minimum postdata calculation and no extra measurement

The extra test time was less than 1ms

Overall very low cost and effective approach

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European Test Symposium, Southampton U.K.May 2006

Adit D. SinghAuburn University

Outlier Screening

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What is screening?

Discarding some suspect die without conclusiveevidence that they will fail in operation

Based on:

Profiling: Bad Neighborhood

company you keep

Outliers: Behave differently in some way

something doesnt look right

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Basis for Screening

Profiling: company you keep

Outliers: something doesnt look right

Airport Security Screens

because exhaustive testing

- strip searching and x-raying -

every airline passenger is cost prohibitive

Same cost trade-off!

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What happens next?

Suspects are discarded- (bumped off the flight)

Suspects are tested further

Test Optimization

- saves high cost testing of exhaustive

testing of every passenger

Adaptive testing- Appropriate tests are applied

depending on what looks different

Extreme cases!

More generally

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Questions?