ic design front-end solution · ßgenerates hspice™ compatible files (.tr, .mt, *.ac)...

IC Design Front-End Solution

Scholar, SmartSpice, and Smartview

- 2 -Analog Front-end

Scholar, SmartSpice and SmartView Agenda

ß Silvaco’s Solution for Analog IC Front-End Design

ß Scholar™ Schematic Capture and Editor

ß SmartSpice™ Analog Circuit Simulator

ß SmartView™ Waveform Viewer and Post-Processor


Silvaco’s Solution for Analog IC Front-End Design

ß Scholar - Schematic Capture and Editor

ß SmartSpice - Berkeley based SPICE simulator

ß SmartView - Graphical postprocessor

ß Advantagesß Easy transition from other popular IC design tools

ß User-friendly and intuitive design environment

ß Design portability between platforms (SunOS, Windows, Linux)

ß PDKs (process design kits) to provide standard pre-built design models,cells, symbols, schematics for participating foundries


Analog/Mixed-Signal Design Flow


Agenda: Schematic Capture and Editor


ß Scholar™ Schematic Capture and Editor

ß SmartSpice™ Analog Circuit Simulator

ß SmartView™ Waveform Viewer and Post-Processor


Scholar Schematic Capture and Editor

ß Powerful front-end schematic editor and viewer

ß Tightly integrated with Silvaco’s SmartSpice and Smartview tools

ß Creates multi-sheet, multi-view, hierarchical, or flat designs

ß Import of EDIF 2 0 0 schematics, symbols, and cells

ß Intuitive left-to-right toolbar implementation to mirror design flow

ß Dialog box approach for building SPICE control cards and analysis

ß Analog environment for ease of saving and plotting vectors

ß Ability to switch processes and run process variant simulations onthe same schematic

ß Generate both SPICE netlist and LVS netlist from same schematic

ß Supported on Solaris, Red Hat Linux, and Windows OS



Schematic Area maybe maximized forlargest possibledrawing area



ß Library trees forselecting symbolsin a hierarchicallibrary format

ß Use of multiplelibraries or multipleworkspaces tochange betweenprocesses



Session area:

ß Reports schematicediting actions,warnings, anderrors

ß Reports creation ofinput deck andnetlist

ß Reports simulationfeedback fromSmartSpice



Cross Probe Mode

ß Select vectors tobe saved

ß Select vectors tobe plotted

ß Pre-Simualtionoptions


ß Hierarchicalascending anddescending in designand simulationmodes

ß View any level orlevels of a design peruser configuration



Scholar – Editing Instance Attributes

ß Spreadsheet style editor

ß Changes in a single attributedialog may apply to:ß Only selected instance

ß Selected instances

ß Matching symbol instances

ß All instances

ß Easy to change device modelsfor all devices and generatesubsequent runs


Scholar – Symbol Editor

ßDefine symbol type as:ß Primitiveß MOS, Bipolar, active, passive

ß Specialß GND, power, bus, PARAMS

ß Sub-schematicß Descend into circuit and pass

parameters

ß Netlistß Attach .SUBCKT netlist via file to

symbol

ß Verilog-Aß Attach Verilog-A module via file to

symbol

ßDefine symbol pins to have a fixedor non-fixed signal name atinstance level


Scholar – Symbol Editor

ßDefine attributes to be changeable or fixed at instance level

ßDefine expressions to be passed into the SPICE netlist

ßEdit SmartSpice and Guardian Strings


SmartSpice String:X_@PREFIX@PATH %C %B %E %VSUB XNPN AREA=@W $M

SmartSpice Netlist:X_Q27 NET8 BANDGAP NET2 GND XNPN AREA=1.5U M=1X_Q28 BANDGAP NET8 NET3 GND XNPN AREA=5U M=1

Guardian String:@PREFIX@PATH %C %B %E %VSUB NPN AREA='(1.25U*AREA)'

Guardian Netlist:Q28 BANDGAP NET8 NET3 GND NPN AREA='(1.25U*AREA)'Q27 NET8 BANDGAP NET2 GND NPN AREA='(1.25U*AREA)'

Scholar – SmartSpice and Guardian Strings

ß Schematic Drawings generate two netlists:ß SmartSpice netlist (represents simulation netlist)

ß Guardian netlist (represents LVS netlist)

ß Each symbol contains two strings:ß SmartSpice String

ß Guardian String

ß Example: 4 terminal npn device (references a subcircuitdefinition for SmartSpice and a BJT transistor for LVS)



ß Hierarchical design checkingand reporting system

ß Zoom to error for eacherror found

ß Automatically opens anylevel with error when erroris selected in report


Scholar - Customize Settings

ß Set default settings for individuals orworkgroupsß Choose settings for integrated tools

including:ß Set versions for SmartSpice and

SmartViewß Parallel SPICE and marching

waveforms

ß Customized initialization filesß Schematic and symbol grid settingß Sheet Border templatesß User-defined shortcuts and bindkeysß Color settingsß Autosave and recovery


Scholar – Control Deck Builder


Design Flow


Scholar – Creating Netlists and Input Decks

ß Netlists and input decksautomatically created by scholar

ß Netlists can be made as top-down oras .SUBCKT format


Scholar – Pre-Simulation

ß Choose which analysis to plot

ß Select what to be plotted:ß Voltage markers on nodes

ß Current markers on pins

ß Select what to be savedß All currents and voltages

ß Only what is marked

ß Save from control deck

ß Plot to:ß Existing plot

ß Create new plot


Scholar – During Simulation

ß Run-time dialogß Final simulation time

ß Current simulation time

ß Timestep

ß Temperature

ß Number of CPUs


Scholar – After Simulation

ß SmartSpice finishessimulation

ß SmartSpice writes *.rawand *.out files

ß SmartView is launched

ß The *.raw file is loadedautomatically intoSmartView

ß Ready for cross-probing


Scholar – Running Verilog-A Circuits

ß Verilog-A modules maybe mapped directly tosymbols

ß Verilog-A circuits may beas compact models or asbehavioral blocks, orboth

ß Verilog-A circuits andregular analog primitivecircuits may be mixedtogether and simulated

ß Results from analogprimitive circuit andVerilog-A can bemeasured and overlaid


Scholar File Handling


Agenda: SmartSpice Analog Circuit Simulator


ß Scholar Schematic Capture and Editor

ß SmartSpice Analog Circuit Simulator

ß SmartView Waveform Viewer and Post-Processor


SmartSpice – Analog Circuit Simulator

ß Industry leader in analog IC designsimulation

ß Berkeley SPICE compatibleß Superior simulator in speed and

convergenceß 100% HSPICE™ compatible for

netlists, models, analysis features,and results

ß Capacity - up to 400 thousandactive devices in 32 bit and 8million active devices in 64 bitversion

ß Modular design to include solvers,parsers, models, and engine

ß Supports latest technologiesß Supported on Solaris, Linux, and

Windows


SmartSpice – Analog Circuit Simulator

ß SmartSpice may be run threeways:ßBatch Mode

ß Run cell characterizationß Command line drivenß Generates HSPICE™ compatible

files (*.tr, *.mt, *.ac)

ß Interactive Modeß GUI interfaceß Easy access to simulation

information and input deckß Environment to manage designsß Integrated to postprocessor

ßSchematic Modeß Run directly from schematic capture

environmentß Schematic changes automatically

update the netlist and input deck forup-to-the-minute simulationenvironment


SmartSpice – Interactive Mode

ß Drag and drop input decks

ß Choose an analysis

ß Choose what to save or plot

ß Run Simulation

ß Display Statistics

ß Open vector menu and plot results


SmartSpice – File Handling


Agenda: SmartView Waveform Viewer and Post-Processor


ß Scholar Schematic Capture and Editor

ß SmartSpice Analog Circuit Simulator

ß SmartView Waveform Viewer and Post-Processor


SmartView – Graphical Post-Processor

ß Industry driven waveformanalysis toolß Hierarchical or flat vector

arrangementß Pre-filtering of data to streamline

resultsß View histories of concurrent

simulations on one plotß Vector Calculator with:

ß Built-in SPICE macros and functionsß Capability for user-defined functions

ß View *.raw, *.ac0, and *.tr0 formatsß Supported on Solaris, Linux, and

Windows



ß User-sizeable areas forplots, lists, and dataß Drag and drop capability

from vector tree into plotß Toolbars

ß Standardß Customizableß Dockable

ßMerge or delete vectorsacross single or split plotsß Undo and redo capability



ß Various measuring devicesß View more than one rawfile

at a timeß Simultaneous zooming

between plotsß Time synchronized panning

and zooming between plotsß Changing axis from linear

to logß Context sensitive menus for

all plot objects


SmartView – Measurements Tools

ß Plot to:ß Cartesianß Polarß Smithß Spectral Densityß Histogram

ß Measurement Dialogs:ß Rise timeß RMSß Min,max (P-P)ß Delayß Periodß Overshootß Averageß Derivativeß Inetgral


SmartView – Analyzing Parametrics

ß Parametric Analysisß View sweeps merged

ß View sweeps separate byvariable and value

ß Ability to combine and splitsweeps

ß Sweep managerß Manage all sweeps in rawfile

ß Choose which sweeps todisplay

ß Handles multiple parametricruns and secondary sweeps


Roadmap

ß Phase Iß Delivery of IC design flow tools in new GUI

ß All products to share common toolbars, controls, dialogs, look and feel

ß Standard window controls for each native OS

ß Phase IIß Schematic Driven Layout

ß DC Bias Display (Scholar)

ß Find/Replace dialogß Nets, instances, attributes, symbols

ß Back Annotationß Annotate over time

ß Annotate to discrete time

ß 1-D arrays and 2-D matrices dialog

ß Handling of serial arrays

ß Macro recording (SmartView)

ic design front-end solution · ßgenerates hspice™ compatible files (*.tr, *.mt, *.ac)...

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ic design front-end solution · ßgenerates hspice™ compatible files (.tr, .mt, *.ac)...