iay 0600 digital systems design digitaalsüsteemide disain course overview alexander sudnitson...

IAY 0600

Digital Systems Design

Digitaalsüsteemide disain Course Overview

Alexander SudnitsonTallinn University of Technology

2

Administrative

Aleksander Sudnitsõn (Alexander Sudnitson)

Department of Computer Engineering (Arvutitehnika instituut) Associate Professor (dotsent)

[email protected]. +372 5092356www.pld.ttu.ee/~alsu

http://www.pld.ttu.ee/~alsu

3

Course resources

www.pld.ttu.ee/~alsu

IAY0600 Digital Systems Design (LECTURES) Digitaalsüsteemide disain

IAY0600l Digital Systems Design (WORKSHOPS) Digitaalsüsteemide disain (LABS)

http://www.pld.ttu.ee/~alsu

http://ati.ttu.ee/~alsu/IAY0600.html

http://ati.ttu.ee/~alsu/IAY0600l.html


4

Lectures

Lecture:Wednesday 14.00 - 15.30


The first regular Lab time: 16.09.2015, 16.009.09.2015 are lectures only 14.00 – 17.30

5

Labs

A. Wednesday 16.00 - 17.30 (19.15)B. Thursday 17.45 – 19.15 (21.00)

Assistant: research scientist, Dimitri Mihhajlov, PhDTechnical Assistant: early stage researcher Artjem Rjabov

The first regular Lab time: 16.09.2015, 16.00

6

Labs


IAY0600l

7

Grading

To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations (20 points in final grade) and of the demonstration of the projects and the quality of a written reports (40 points in final grade for doing compulsary labs, up to additional 40 points in final grade for doing optional labs).

“LEARN BY DOING”Learning By Example Using VHDL (with FPGA Evaluation Boards)

8

Passing a Lab

Every completed experiment (project) must be presented to Assistant (D. Mihhailov), who will evaluate student’s results and effort

Each lab is passed in three steps:Step 1: Visual demonstrationStep 2: Submission of the reportStep 3: Defence/discussion of the report

Labs can be done either individually, or in teams of two.Note, that in case of teamwork Step 2 and Step 3 MUST be done by each team member separately.

9

Compulsory Labs

Labs labelled “compulsory” form the basic core of the course. In order to pass the course theselabs MUST be completed within the deadline. Passing all compulsory labs yields the minimumpositive final grade and allows possibility to attend the exam.

• Comparator• Adder• Parameterizable Adder• LFSR• Finite-State Machine

10

Optional Labs

Labs labelled “optional” are more advanced labs that are not required to be completed in order to pass the course. However, each successfully passed optional lab increases the final grade (up to the maximum for doing all optional labs).

• Greatest Common Divisor • Creeping Line • RISC Processor

11

LabsXilinx FPGA ToolsThe laboratory assignments are done using the Xilinx ISE Software.

simulationsynthesisimplementation

Digilent Nexys3 FPGA Board

13

Course goals

to elaborate knowledge of the design process from design description in VHDL through functional simulation, synthesis, timing simulation, and PLD (FPGA) programming;

to gain experience in designing and verifying digital systems using synthesis and simulation tools;

to provide students the theory and practice of rapid prototyping of digital systems in a laboratory environment;

14

Outcomes

to proceed from a digital system description in VHDL to its implementation in a PLD (FPGA) using of a number of computer-aided design software tools;to understand how to interpret design tool outputs in evaluating alternative system designs for a specific set of requirements, and how to use the knowledge gained to improve the design;to understand and comprehend asynchronous design methods, computational models, design terminology.

Why is this course worth taking?

• VHDL for synthesis: one of the most sought-after skills

• knowledge of state-of-the-art tools used in the industry

• knowledge of the modern FPGA & ASIC technologies

• unique knowledge and practical skills that make you competitive on the job market

16

Main topics

The course is based on the development of a real-world projects and case studies

Synthesizable VHDL Digital systems design methodology using

VHDL and PLD (FPGA) FPGAs as means for building reconfigurable

systems Rapid prototyping of digital systems.

17

Slides


Lecture slides (to be published before each lecture).

Auxiliary material:

Digital Systems Modeling and Synthesishttp://www.ati.ttu.ee/IAY0340/

18

Textbooks

Short K. L. VHDL for Engineers, Pearson Education, Inc., 2009, 2013.Chu P.P. FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008.Pedroni V. A. Circuit Design and Simulation with VHDL, Massachusetts Institute of Technology, 2010.Skljarov V., Skliarova I., Sudnitson A. Design of FPGA-based Circuits using Hierarchical Finite State Machines. TUT Press, Tallinn, 2012, 240 p.Richard E. Haskell & Darrin M. Hanna, "Digital Design“, 2nd Edition, 2012

19

Digital System

A discrete system is a system in which signals have a finite number of discrete values.(This contrasts with analog systems, in which signals have values from an infinite set).

Any finite number of discrete values can be represented by a vector of signals with just two values. Such a signal, which takes only two values, is called a digital signal (or binary, or logic), and any device that processes digital signals is called a digital device.

DiscreteSystem

Inputs Outputs

20

Design process

The design process consists of obtaining an implementation that satisfies the specification of a system.

Specification (behaviour)

Analysis (verification) Synthesis

Implementation(structure)

The analysis of a system has an objective the determination of its specification from an implementation. The synthesis consists of obtaining an implementation that satisfies the specification of a system

21

Design representation

A structural representation is one that the black box as a set of components and their connections. It specifies the product’s implementation without explicit reference to its functionality. The functionality could be derived from that of its interconnected components.

A behavioral or functional representation is one that looks at the design as a black box. A behavioral representation describes the functionality but not the implementation of a given design, defining the black box’s response to any combination of input values.

Three different domains of description:

A physical representation is one that specifies the physical characteristics of the black box, providing the dimensions and locations of each component and connection contained in the structural description..

22

Modified Y Chart: levels of abstruction

Programmable cores, IPs, ASICs

Registers, Adders, Multipliers, etc.

Logic netlist, Schematic

Boolean equations

Dataflow

Abstract Processes

Algorithm Processor, Memory, Peripheral interface

View

Behavior Description

Structural Description

Logic

Register Transfer (RTL)

System

Architectural

23

Timing units at different levels



Programmable cores, IPs, ASICs

Boolean equations

Dataflow

Abstract Processes


View



Delay

Clock Cycle

Computation Step

Comuncation Transaction

Time Units

24

Modified Y Chart : this course area


View





Dataflow / RTL

Boolean equations

Synthesis

Analysis

25

Modified Y Chart: transformations


View





Dataflow

Boolean equotions

Algorithmic

Register-Transfer

Logic

Transformations

26

Chart supporting synthesis activity

View



Algorithmic level of abstraction

Register-transfer level of abstraction

Logic level of abstraction

Behavioral synthesis

RTL synthesis

Logic synthesis

27

Example: HalfAdder

SumCarryHalfAdder

ab

Structure

Sum = ¬a&b a&¬b = a b

Carry = a & b

a b Sum Carry0 0 0 00 1 1 01 0 1 01 1 0 1

Behavior

b Carry

&

a Sum

28

Example: HalfAdder Behavioral Description

entity HALFADDER isport(a, b: in bit; Sum, Carry: out BIT); end HALFADDER;

Sum = ¬a&b a&¬b = a b

Carry = a & bHalfAdder

a

b

Sum

Carry

This is data flow behavioral description

architecture RTL of HALFADDER isbegin

Sum <= a xor b;Carry <= a and b;

end RTL;

Register Transfer Level (RTL) Design Description

Combinational Logic

Combinational Logic

Registers

…

30

Brief History of VHDL

VHDL is an industry standard hardware description language that is widely used for specifying, modeling, designing, an simulating digital systems.VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

The first version of VHDL:IEEE-1076 1987

The most commonly supported by CAD tools version of VHDL:IEEE-1076 1993

VHDL for Synthesis (vs. for Simulation)

31

VHDL was originally developed as a language for describing digital systems for the purpose of documentation and simulation, but not for synthesis.In 1999, the IEEE issued IEEE Std 1076.6-1999, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. This standard described a subset of IEEE Std 1076 suitable for RTL synthesis. It also described the syntax and semantics of this subset with regard to synthesis.IEEE 1076.6 defines a subset of the language that is considered the official synthesis subset.A revision of this standard was issued in 2004 and 2008.

32

VHDL vs. Verilog

Government Developed Commercially Developed

Ada based C based

Strongly Type Cast Mildly Type Cast

Difficult to learn Easier to Learn

More Powerful Less Powerful

Features of VHDL and Verilog:technology/vendor independentportablereusable

33

VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

VHDL for specification, simulation, and synthesis

34

Design flow for VHDL/PLD methodology

In our coursePLD = FPGA

iay 0600 digital systems design digitaalsüsteemide disain course overview alexander sudnitson...

Documents