HyperThreading

● Improves processor performance under certain workloads by providing useful work for execution units that would otherwise be idle

● Duplicates sections of the processor

– those that store the architectural state

– does not duplicate main execution resources

● allows a physical processor to be two ”logical” processors

– can schedule two threads or processes simultaneously

When processor stalls

● as a result of

– cache miss

– branch misprediction

– data dependency

● processor may use those execution resources to

execute other processes or threads

Architectural State

● Control Registers

– instruction flag registers

– interrupt mask registers

– memory management registers

– status registers

● General purpose registers (AX, BX, CX, DX, ...)

Improved Performance

● Uses 5% of the die area over the “normal”

processor

● Performance improvements of up to 30%

Dual Core

● One which combines two or more independent

processors into a single package

● Contains two independent microprocessors

● Allows thread-level parallelism w/o including

multiple microprocessors in separate physical

packages

● CMP – chip level multiprocessing

Advantages vs SMP

● Cache coherency

– Can operate at a much higher clock rate than is

possible if the signals have to travel off-chip

● Less space required

● Less power usage

Disadvantages

● Requires OS support

● Requires threaded applications

● Integration of multi-core chip drives production

yields down, they are more difficult to manage

thermally than lower-density single-chiop