hv7351 data sheet...2019/05/14 · 8-channel, ±70v, 3a programmable high-voltage...

HV73518-Channel, ±70V, 3A Programmable High-Voltage

Ultrasound-Transmit Beamformer

Features• Eight Channels with Return-to-Zero (RTZ)• Up to ±70V Output Voltage• ±3.0A Output Current• Stores up to Four Different Patterns• Independent Programmable Delays• 80-Lead Single 11 x 11 mm VQFN Package

Applications• Medical Ultrasound Imaging• Non-Destructive Testing (NDT)• Arbitrary Pattern Generator• High-Speed PIN Diode Driver

General DescriptionThe HV7351 device is an 8-channel, programmablehigh-voltage ultrasound-transmit beamformer. Eachchannel is capable of swinging up to ±70V with anactive discharge back to 0V. The outputs can sourceand sink up to 3.0A to achieve fast output rise and falltimes. The active discharge is also capable of sourcingand sinking 3.0A for a fast return to ground. The topol-ogy of the HV7351 will significantly reduce the numberof I/O logic control lines needed.

Each pulser has four associated 64-bit Shift registersfor storing predetermined transmit patterns and a 10-bitdelay counter for controlling the transmit time. One offour arbitrary patterns can be transmitted with adjust-able delay, depending on the data loaded into theseShift registers and the delay counter. The delay countercan be clocked up to 200 MHz, allowing incrementaldelays down to 5 ns.

Typical Application Circuit

Tx128

TRIG

Tx127

Tx3

Tx2

Tx1 tDELAY1

TRIG

HV73518-Channel

U1

HV73518-Channel

U2

HV73518-Channel

U16

tDELAY2

tDELAY3

tDELAY127

tDELAY128

E3

E1

E2

E127

E128

ArrayProbe

2015-2019 Microchip Technology Inc. DS20005412B-page 1

HV7351

Package Types (Top View)

HV735111 x 11 mm VQFN*

DOUT2

AVDD

INV

TCK

CS1

A0

74 71 68 65 6280 77

81

73 70 67 64 6179 76 72 69 66 6378 7527 30 33 36 3921 24 28 31 34 37 4022 25 29 32 35 3823 26

7

10

13

16

19

1

4

8

11

14

17

20

2

5

9

12

15

18

3

6

54

51

48

45

42

60

57

53

50

47

44

41

59

56

52

49

46

43

58

55

DIN2

SIZE

DVDD

SCK

EN

CW

CS2

DGNDTRIG

TCKVLL

DOUT1

DIN1

A1

PVSS

VNN

VPF

PGND

VPF

DGND

VNF

VPP

PVDD

PGND

PGND

DGND

DVDD

PVSSPGND

VNN

VNF

DGND

PVDD

VPP

NC

VR

N

PV

SS

TX2

TX3

VP

P

PV

DD

PG

ND

TX1

VN

N

VN

F

VP

F

PG

ND

VP

P

VP

P

VN

N

VN

N

VP

P

VN

N

TX4

NC

VR

P

PV

SS

TX7

TX6

VP

P

PV

DD

PG

ND

TX8

VN

N

VN

F

VP

F

PG

ND

VP

P

VP

P

VN

N

VN

N

VP

P

VN

N

TX5

VSUB

* Includes Exposed Thermal Pad (EP); see Table 2-1.

DS20005412B-page 2 2015-2019 Microchip Technology Inc.

HV7351

Block Diagram

INVEN/LDCW

CLK

16/32-BitSerial

Shift Reg.

INVEN/LDCW

CLK

16/32-BitSerial

Shift Reg.

INVEN/LDCW

CLK

16/32-BitSerial

Shift Reg.

INVEN/LDCW

CLK

16/32-BitSerial

Shift Reg.

Divide-by-2

6-Bit CounterDivide-by-NN = 1 to 64

LinearRegulator

LinearRegulator

ENEN10-Bit Delay

Counter

Divide-by-2

VLL to VDDTranslator

-

+

PGND

PGND

VPF

VPFVNF

VNF

PVSS

PVDD

PVSS

PVDD

VPP

VPF

VRN

VRP

VNF

VNN

VPP

TX1

VNN

PGND

PVDDPVSS

VPP

TX8

VNN

PGND

CW

fCW

PIN

NIN

ControlLogic

CW

fCW

PIN

NIN

ControlLogic

RTZ GATE DriverSupply Voltages

6-Bit CounterDivide-by-NN = 1 to 64

ENEN10-Bit Delay

Counter

8 10-Bit Registersfor Delay Counters

6-Bit forDivide-by-N

16/32-Bit RegisterPattern 4








P-Ch. Registers N-Ch. Registers

Dec

oder

VPFVRN

VPP

VNFVNN

VRP

VLLAVDDDVDD

EN

SIZE

SCKDIN1

DOUT1

A0A1

DIN2DOUT2

CWINV

TRIG

TCK

DGND

AGND

VSUB

CS2

CS1

TCK


HV7351

NOTES:


HV7351

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†Positive logic supply (VLL)............................................................................................................................ -0.5V to 5.5VPositive logic supply voltage (DVDD)............................................................................................................ -0.5V to 5.5VPositive gate drive supply voltage (PVDD) ................................................................................................... -0.5V to 5.5VPositive analog supply voltage (AVDD)......................................................................................................... -0.5V to 5.5VNegative gate drive supply voltage (PVSS) ................................................................................................ +0.5V to -5.5VHigh-voltage positive supply voltage (VPP) ................................................................................................. -0.5V to +80VHigh-voltage negative supply voltage (VNN) ............................................................................................... +0.5V to -80VDifferential high-voltage supply (VPP – VNN)...........................................................................................................+160VPositive floating supply voltage (VPF) .................................................................................................. VPP – 6.0V to VPPNegative floating supply voltage (VNF).................................................................................................VNN to VNN + 6.0VPositive supply for VNF regulator (VRP)............................................................................................................. 0V to 15VNegative supply for VPF regulator (VRN) .......................................................................................................... 0V to -15VOperating temperature ........................................................................................................................... -40°C to +125°CStorage temperature ............................................................................................................................... -65°C to +150°CESD Rating All Pins .............................................................................................................................................. 0.75 kV

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This isa stress rating only and functional operation of the device at those or any other conditions above those indicated inthe operational sections of this specification is not intended. Exposure to maximum rating conditions for extendedperiods may affect device reliability.

TABLE 1-1: OPERATING SUPPLY VOLTAGESElectrical Specifications: Unless otherwise specified: TA = +25°C. Boldface specifications apply over the TA range of -20°C to +85°C.

Parameter Sym. Min. Typ. Max. Units Conditions

Positive High-Voltage Supply VPP 3.0 — 70 V Note 1Negative High-Voltage Supply VNN -70 — -3.0 VLogic Interface Voltage VLL 2.85 3.30 3.6 VLow-Voltage Positive Analog Supply Voltage

AVDD 4.75 5.00 5.25 V

Low-Voltage Positive Digital Supply Voltage

DVDD 4.75 5.00 5.25 V

Low-Voltage Positive Gate Drive Supply Voltage

PVDD 4.75 5.00 5.25 V

Low-Voltage Negative Gate Drive Supply Voltage

PVSS -5.25 -5.00 -4.75 V

Low-Voltage Positive Supply for VNF Regulator

VRP 4.75 — 12 V

Low-Voltage Negative Supply for VPF Regulator

VRN -12 — -4.75 V

Reference Voltage Logic Trip Point for TCK Pin

TCK 0.4 VLL 0.5 VLL 0.6 VLL V

TCK/TCK Input Current ITCK/ITCK — — ±10 µA ITCK = 0 to VLL, TA = +25°C (Note 1)

Note 1: Specification is obtained by characterization and is not 100% tested.


HV7351

TABLE 1-2: REGULATOR OUTPUTSParameter Sym. Min. Typ. Max. Units Conditions

Positive Floating Gate Drive Voltage

VPF VPP – 5.25 VPP – 5.00 VPP – 4.00 V 4x1 µF ceramic capacitors across VPF and VPP

Negative Floating Gate Drive Voltage

VNF VNN + 4.00 VNN + 5.00 VNN + 5.25 V 4x1 µF ceramic capacitors across VNF and VNN

ELECTRICAL CHARACTERISTICSElectrical Specifications: Unless otherwise specified: VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.


VLL Quiescent Current IVLLQ — 384 500 µA EN = Low, all inputs are static

AVDD Quiescent Current IAVDDQ — 12 30 µA EN = Low, all inputs are staticDVDD Quiescent Current IDVDDQ — 12 30

PVDD Quiescent Current IPVDDQ — 70 100VRP Quiescent Current IVRPQ — 0.3 6 µA EN = Low,

all inputs are staticVRN Quiescent Current IVRNQ — -0.01 6PVSS Quiescent Current IPVSSQ -85 -45 — µA EN = Low,

all inputs are staticVPP Quiescent Current IVPPQ — 2.6 6 µA EN = Low,

all inputs are staticVNN Quiescent Current IVNNQ — -1.6 6VLL Enabled Quiescent Current

IVLLEN — 390 500 µA EN = High, all inputs are static

AVDD Enabled Quiescent Current

IAVDDEN — 600 800 µA EN = High, all inputs are static

DVDD Enabled Quiescent Current

IDVDDEN — 22 55

PVDD Enabled Quiescent Current

IPVDDEN — 44 100 µA EN = High, all inputs are static

VRP Enabled Quiescent Current

IVRPEN — 450 650 µA EN = High, all inputs are static

VRN Enabled Quiescent Current

IVRNEN -650 -350 —

PVSS Enabled Quiescent Current

IPVSSEN -100 -44 — µA EN = High, all inputs are static

VPP Enabled Quiescent Current

IVPPEN — 370 620 µA EN = High, all inputs are static

VNN Enabled Quiescent Current

IVNNEN -620 -420 —

VLL Current at 80 MHz Clock IVLLCW — 500 — µA VPP = +5.0V, VNN = -5.0V, EN = High, CW = High, 80 MHz on TCK,0.5 VLL on TCK, all eight channels active at 5.0 MHz, no load (Note 1)

DVDD Current at CW = 5 MHz IDVDDCW — 25 — mAVPP Current at CW = 5 MHz IVPPCW — 141 — mAVNN Current at CW = 5 MHz IVNNCW — 98 — mA

Note 1: Specification is obtained by characterization and is not 100% tested.


HV7351

AC ELECTRICAL CHARACTERISTICSElectrical Specifications: Unless otherwise specified: VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.


Transmit Clock Frequency

fTCK 0 — 200 MHz

Serial Clock Frequency fSCK 0 — 80 MHz No daisy-chain0 — 70 Daisy-chained (Note 2)

Setup Time Data into SCK

tSU-DIN 2 — — ns Note 1

Hold Time SCK to Data In

tH-DIN 2 — — ns Note 1

Setup Time CS1 Low to SCK

tSU-CS1 2 — — ns Note 2

Setup Time CS2 Low to SCK

tSU-CS2 2 — — ns Note 2

Setup Time from TRIG Fall to TCK Rise Edge

tSU-TRIG 2 — — ns Note 2

TRIG Pulse Width tW-TRIG 2 x TCK — — Cycle Note 2SCK to Data Out Low to High Delay Time

tLHDO 3 9 12 ns For DOUT1 (Note 1)3 9 10 For DOUT2 (Note 1)

SCK to Data Out High to Low Delay Time

tHLDO 3 9 12 ns For DOUT1 (Note 1)3 9 10 For DOUT2 (Note 1)

A1A0 Pulse Width tWA1A0 tW-TRIG + 40 — — ns Note 2Setup Time A1A0 to TRIG Rising Edge

tSUA1A0 — 20 — ns Note 1

Hold Time A1A0 to TRIG Falling Edge

tHA1A0 — 20 — ns

Device Enable Time tEN-ON — 1 — ms 1.0 µF capacitor on every VPF and VNF pin (Note 1)

Device Disable Time tEN-OFF — — 100 ns Note 1Output Rise Time from 0V to +HV

tr1 — 9 13 ns Load = 330 pF||2.5 k

Output Fall Time from 0V to -HV

tf1 — 9 13 ns

Damping Output Rise Time from -HV to 0V

tr2 — 9 13 ns

Damping Output Fall Time from +HV to 0V

tf2 — 9 13 ns

Output Rise Time from -HV to +HV

tr3 — 17 23 ns

Output Fall Time from +HV to -HV

tf3 — 17 23 ns

CW Output Rise Time trcw — 9 16 ns VPP = +5.0V, VNN = -5.0V,Load = 330 pF||2.5 kCW Output Fall Time tfcw — 9 16 ns

Note 1: Specification is obtained by characterization and is not 100% tested.2: Specification is for design guidance only.


HV7351

Output Propagation Delay Rise Time 1

tdr1 11 14 18 ns No load

Output Propagation Delay Fall Time 1

tdf1 11 14 18 ns


tdr2 12 15 19 ns


tdf2 11 15 18 ns


tdr3 12 15 19 ns


tdf3 11 15 18 ns

CW Output Propagation Delay Time from Low-to-High

tdcwlh 10 13 17 ns VPP = +5.0V, VNN = -5.0V,no load

CW Output Propagation Delay Time from High-to-Low

tdcwhl 10 14 17 ns

Delay Time Matching tdcwhl — ±0.7 — ns P to N, channel-to-channel matching

Delay Jitter on Rise or Fall

tJCW — 13 — ps VPP = +5.0V, VNN = -5.0V,Load = 50 (Note 2)

Latency LAT 3.5 TCK Note 2Output P-Channel MOSFET to VPP, CW = 0Output Saturation Current

IOUT 2.2 3.2 — A

Output On-Resistance RON — 4.2 — IOUT = 100 mAOutput Capacitance COSS — 62 — pF VPP – VOUT = 25V,

f = 1.0 MHz (Note 2)Output N-Channel MOSFET to VNN, CW = 0Output Saturation Current

IOUT 2.2 3.2 — A

Output On-Resistance RON — 2.4 — IOUT = -100 mAOutput Capacitance COSS — 50 — pF VNN – VOUT = -25V,

f = 1.0 MHz (Note 2)Output P-Channel MOSFET to VPP, CW = 1Output Saturation Current

IOUT 1.2 1.5 — A

Output On-Resistance RON — 8 — IOUT = 100 mAOutput Capacitance COSS — 62 — pF VPP – VOUT = 25V,

f = 1.0 MHz (Note 2)

AC ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise specified: VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.




HV7351

Output N-Channel MOSFET to VNN, CW = 1Output Saturation Current

IOUT 1.2 1.5 — A


f = 1.0 MHz (Note 2)Damping P-Channel MOSFET to PGNDOutput Saturation Current

IOUT 2.2 3.2 — A

Output On-Resistance RON — 4 — IOUT = 100 mAOutput capacitance COSS — 62 — pF VPP – VOUT = 25V,

f = 1.0 MHz (Note 2)Damping N-Channel MOSFET to PGNDOutput Saturation Current

IOUT 2.2 3.2 — A


f = 1.0 MHz (Note 2)Logic InputsClock Input Current ITCK — ±1.0 — µA Voltage 0 to VLLClock Input High Voltage

VIH_TCK VTCK + 0.15 — VLL V TCK = 0.5 VLL (Note 2)

Clock Input Low Voltage

VIL_TCK 0 — VTCK – 0.15 V

Logic Input High Voltage

VIH 0.8 VLL — VLL V For all logic inputs except clock inputs

Logic Input Low Voltage

VIL 0 — 0.2 VLL V

Input Logic High Current

IIH — — 1 µA

Input Logic Low Current

IIL -1 — — µA

Output Logic Low Voltage

VOL 0 — 0.7 V IOUT = 0 to -10 mA

Output Logic High Voltage

VOH VLL – 0.7 — VLL V IOUT = 0 to 10 mA

Input Logic Capacitance

CIN — — 5.0 pF Note 2

AC ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise specified: VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.




HV7351

TEMPERATURE SPECIFICATIONSElectrical Specifications: Unless otherwise specified: VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TA = +25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Temperature RangesOperating Ambient Temperature Range TA -40 — +125 °CStorage Temperature Range TA -65 — +150 °CMaximum Junction Temperature TJ -40 — +150 °CPackage Thermal ResistancesThermal Resistance, 80L-11x11 mm VQFN JA — 14 — °C/W

TABLE 1-3: LOGIC TRUTH TABLE

Mode

Inputs Outputs

CommentsEN CW

10-B

itC

ount

er

INV NIN PIN N-Ch. P-Ch. RTZ

Non-CW mode. Outputs not inverted. Outputs are controlled by data in the Shift registers.

1 0 x x 0 0 OFF OFF ON Return-to-Zero (RTZ) is activated when NIN and PIN are both low. Output is pulled to ground through a series diode.

1 0 x 0 0 1 OFF ON OFF Not inverted. Logic ‘1’ in the P-Channel register turns on the output P-Channel MOSFET.

1 0 x 0 1 0 ON OFF OFF Not inverted. Logic ‘1’ in the N-Channel register turns on the output N-Channel MOSFET.

1 0 x x 1 1 OFF OFF OFF Avoids cross overcurrent. A logic ‘1’ in both P- and N-Channel registers will put the output in a High-Z state.

Non-CW mode. Outputs are inverted. Outputs are controlled by data in the Shift registers.

1 0 x 1 0 1 ON OFF OFF Transmit pattern is inverted.1 0 x 1 1 0 OFF ON OFF

CW mode. Output follows fCW.

1 x All ‘1’s x x x OFF OFF OFF If 10-bit counter reaches all ‘1’s, then the channel will be turned off.

1 1 Not all ‘1’s

x x x OFF/ ON ON/ OFF OFF The channel’s output follows the fCW signal. The Shift registers for PIN and NIN remain static to save power.

Device disabled. 0 x x x x x OFF OFF OFF High-Z state.Legend: x = Don’t care.


HV7351

1.1 Timing Diagrams

FIGURE 1-1: Timing Diagram of 3-Level, 1-Cycle Bipolar RTZ TX Pulse.

FIGURE 1-2: Timing Diagram of 2-Level, 2-Cycle Bipolar non-RTZ TX Pulses with Damping.

TCK0V

3.3V

TRIG

TX1 0V

+70V

Internal CLK(for N = 2)

0VExample with TX2 Delay havingTwo TCK Cycles more than TX1

TCK = 1.65V (0.5 VLL)

TX2

Delay Time Set byTX2 10-Bit Counter


tWTRIG needs to be at least2 Rising Edges of TCK

0V

3.3V

0V

3.3V

-70V

+70V

-70V

3.5 TCK Cycles

tWTRIG

tSU-TRIG

tdr1 tdf2

tdf1

tr1 tf2

tdr2

10% 10%

90% 90%

10% 10%

90% 90%

tf1 tr2

Example with TX2 Delay havingOne TCK Cycle more than TX1


3.5 TCK Cycles

tSU-TRIG

tWTRIG needs to be at least2 Rising Edges of TCK

tWTRIG


tdf390%

10%10%

90%

tf3 tr3

tdr3

TCK0V

3.3V

TRIG

TX1 0V

+70V

Internal CLK(for N = 2)

0V

TCK = 1.65V (0.5 VLL)

TX2

0V

3.3V

0V

3.3V

-70V

+70V

-70V


HV7351

NOTES:


HV7351

2.0 PIN DESCRIPTIONThe descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLEPin Symbol Description

1 AVDD Positive analog supply voltage (+5.0V).2 DIN2 Serial data in for delay counters and frequency divider.

3 CS2 Activates DIN2. Input logic high = off, input logic low = on.4 SIZE Sets pattern width to either 16 bits or 32 bits. Logic low = 16 bits, logic high = 32 bits.5 INV Inverts the TX output waveform. See Table 1-3 for details.6 CW Activates CW mode. Logic low = non-CW mode, logic high = CW mode.

See Table 1-3 for details.7 DOUT2 Data out for delay counters and frequency divider.8 EN Enables and disables device. Logic low = off, logic high = on.9 SCK Serial clock input for Serial Shift registers.

10, 50 DVDD Positive digital supply voltage (+5.0V).11, 43, 51, 58 DGND Digital ground.

12 TRIG Toggles all TX outputs to transmit. Needs to be high for two rising edges of TCK. Delay counters will start on the rising edge of the TCK pin right after the falling edge of the TRIG signal. See Section 1.1 “Timing Diagrams” for details.

13 TCK The TCK and TCK pins can be driven by LVDS or SSTL types of output in a differential manner. The TCK pin can be driven by LVCMOS single-ended output while setting the TCK to GND (or DC value of 0.4V to 0.6V). The logic trip point is on the TCK rising edge and on the TCK falling edge, crossing in the differential manner. In the single-ended case, the trip point is on the TCK rising edge.

14 TCK

15 VLL Logic interface supply voltage (3.3V).

16 CS1 Activates DIN1. Input logic high = off, input logic low = on.17 DOUT1 Data out for P-Channel and N-Channel Pattern registers.18 A0 Decoded to select one of four patterns to be loaded.19 A120 DIN1 Serial data in for P-Channel and N-Channel Pattern registers.21 VRN Negative supply for VPF regulator (-5.0V).

22, 49, 52, 79 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V).23, 24, 46, 48,53, 55, 77, 78

PGND Power ground path for RTZ output transistors.

25, 47, 54, 76 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V).26, 45, 56, 75 VPF Linear regulator output gate drive voltage for the P-Channel output transistors. A

low-voltage 1.0 µF ceramic capacitor needs to be connected across every VPF and VPP pins. There are four capacitors required in total.

27 NC No connection.28, 42, 59, 73 VNF Linear regulator output gate drive voltage for the N-Channel output transistors. A

low-voltage 1.0 µF ceramic capacitor needs to be connected across every VNF to VNN pins. There are four capacitors required in total.

29, 34, 35, 40,41, 60, 61, 66,

67, 72

VNN Negative high-voltage supply (-3.0V to -70V).

30 TX1 Transmit pulser outputs for Channel 1.31, 32, 37, 38, 44, 57, 63, 64,

69, 70

VPP Positive high-voltage supply (+3.0V to +70V).


HV7351

33 TX2 Transmit pulser outputs for Channel 2.36 TX3 Transmit pulser outputs for Channel 3.39 TX4 Transmit pulser outputs for Channel 4.62 TX5 Transmit pulser outputs for Channel 5.65 TX6 Transmit pulser outputs for Channel 6.68 TX7 Transmit pulser outputs for Channel 7.71 TX8 Transmit pulser outputs for Channel 8.74 NC No connection.80 VRP Positive supply for VNF regulator (+5.0V).81 VSUB Exposed center pad must be externally connected to the ground (GND, 0V) on

PCB (DGND).

TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)Pin Symbol Description


HV7351

3.0 DEVICE DESCRIPTION

3.1 Loading Data into the Four 16/32-Bit Pattern Registers

A detailed circuit diagram of the Pattern registers isshown in Figure 3-1. There are four programmable pat-terns that can be stored. One of four patterns can be

selected via the two input logic decoder pins, A1 andA0. Data can be loaded on the selected pattern. Eachpattern can be either 16 or 32 bits wide. The SIZE pindetermines whether they are 16 or 32 bits wide.SIZE = H will set the pattern to be 32 bits wide whileSIZE = L will set it to 16 bits wide. DIN1 is the input datafor the register. When CS1 is high, data will not beshifted in. Data are shifted in only when CS1 is low.

FIGURE 3-1: Pattern Register Circuit Diagram.

With SIZE = H, the circuit is effectively a 64-bit SerialShift register. The data first enter into the P-Channel reg-ister and continue to be shifted though to the N-Channelregister. Data are clocked in during the rising edge of theclock. There is no activity during the falling edge of theclock. The DIN1 data enter into the S64 of the P-Channelregister and exit the S1 of the N-Channel register fromDOUT1. The SPI writing operation of the WaveformPattern registers is LSB first.

EXAMPLE 3-1:

Data are shifted in during the rising edge of the clock.S1 is the first bit shifted in, entering the P-Channelregister. After 64 clock cycles, S1 will be located in theN-Channel register, as shown in Figure 3-2; it will alsobe clocked out to DOUT1.

FIGURE 3-2: Waveform Pattern Register.

2-to-4Decoder

DOUT1

SCK

DIN1

SIZEENDIN

SCK

SIZE

16-/32-BitShift Register

P-Ch. Pattern 1

CS116-/32-Bit

Shift RegisterP-Ch. Pattern 2


P-Ch. Pattern 3

16/32-BitShift Register

P-Ch. Pattern 4

16/32-BitShift Register

N-Ch. Pattern 4


N-Ch. Pattern 3


N-Ch. Pattern 2


N-Ch. Pattern 1

SIZEENDIN

SCK

SIZEENDIN

SCK

SIZEENDIN

SCK

A1 A0 CS1

A1 A0 CS1

A1 A0 CS1

A1 A0 CS1

A1

A0

A1 A0 CS1

A1 A0 CS1

A1 A0 CS1

A1 A0 CS1

For: SIZE = High, 32 bits wideSIZE = Low, 16 bits wide

A1 = A0 = Low, Pattern 1 selectedCS1 = Low, data can be shifted in

64-Bit Serial Shift Register:32 bits for the P-Channeland32 bits for the N-Channel

DOUT1DIN1

SCK

32 Bits for P-Ch Pattern 1 32 Bits for N-Ch Pattern 1

32 Bits forP-Ch Pattern 1

32 Bits forN-Ch Pattern 1

S64 S63 S34 S33 S31S32 S2 S1


HV7351

A 2-to-4 decoder is provided to select which of the fourpatterns is to be used for all of the outputs. Logic inputs,A1 and A0, determine which patterns are selected, asshown in Table 3-1. Once A1 and A0 are set, a risingedge on the trigger logic input pin will automaticallyload the selected pattern to all of the outputs.

3.2 Loading Data into the Delay Counters and the Divide-by-N Counter

Each output channel (TX) has its own programmable10-bit delay counter. For eight channels, 80 bits areneeded. A 6-bit divide-by-N counter is also provided toprogram the desired TX frequency. To program all theindividual delay counters and the divide-by-N counter, an86-bit Serial Shift register is provided. It uses the sameclock input that the Pattern registers use. DIN2 is theinput data for this register. When CS2 is high, data will notbe shifted in. Data are shifted in only when CS2 is low.

As shown in Figure 3-3, the data first enter into the10-bit register for the TX8 delay counter and continueto be shifted through to the 6-bit register for thedivide-by-N counter. Data are clocked in during therising edge of the clock. There is no activity during thefalling edge of the clock. The MSB bit in the 6-bitDivide-by-N register is clocked out into DOUT2 forcascading multiple devices, if desired.

FIGURE 3-3: Delay and Divide-by-N Registers.

TABLE 3-1: DECODER TRUTH TABLELogic Decoder Input

Pattern SelectedA1 A2

0 0 10 1 21 0 31 1 4

10 bits TX8 10 bits TX7 10 bits TX6 10 bits TX5 10 bits TX4 DOUT2

LSB

DIN2SCK

LSB

86-Bit Serial Shift Register: 80 Bits for the Delay Counters and 6 Bits for the Divide-by-N

10 bits TX3 10 bits TX2 10 bits TX1 6 bits Divide-by-N

10 bits TX8 Delay Counter 10 bits TX7 Delay Counter 6 bits Divide-by-N

LSBMSB MSBMSB

S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S6 S5 S4 S3 S2 S1


HV7351

3.3 10-Bit Delay CounterThe TCK and TCK pins are the input clock for the 10-bitdelay counter. The maximum capable clock frequencyis up to 200 MHz. The counter counts upward.

TABLE 3-2: DELAY COUNTERMSB LSB Delay Time

0 0 0 0 0 0 0 0 0 0 1023 TCK Cycles0 0 0 0 0 0 0 0 0 1 1022 TCK Cycles0 0 0 0 0 0 0 0 1 0 1021 TCK Cycles0 0 0 0 0 0 0 0 1 1 1020 TCK Cycles•••

•••

•••

•••

•••

•••

•••

•••

•••

•••

•••

1 1 1 1 1 1 1 1 0 0 3 TCK Cycles1 1 1 1 1 1 1 1 0 1 2 TCK Cycles1 1 1 1 1 1 1 1 1 0 1 TCK Cycle1 1 1 1 1 1 1 1 1 1 No trigger

(Output of the channel is disabled when related

delay is all ‘1’s)


HV7351

3.4 6-Bit Divide-by-N CounterThe TCK and TCK pins are the input clock for the 6-bitdivide-by-N counter. It generates the clock frequencyfor the 16-/32-bit Serial Shift register for the outputP-Channel and N-Channel patterns. Each clock cyclewill set the TX output to be either at VPP, VNN,ground or high-impedance, depending on what waspre-programmed in their corresponding registers.

TABLE 3-3: 6-BIT DIVIDE-BY-N COUNTER REGISTER

MSB LSB N N-Ch, P-Ch and RTZ Output Pulse Width(s)

0 0 0 0 0 0 64 64 ÷ fTCK0 0 0 0 0 1 63 63 ÷ fTCK0 0 0 0 1 0 62 62 ÷ fTCK0 0 0 0 1 1 61 61 ÷ fTCK•••

•••

•••

•••

•••

•••

•••

•••

1 1 1 1 0 0 4 4 ÷ fTCK1 1 1 1 0 1 3 3 ÷ fTCK1 1 1 1 1 0 2 2 ÷ fTCK1 1 1 1 1 1 1 1 ÷ fTCK


HV7351

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information. Package may or may not includethe corporate logo.

3e

3e

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXYYWWNNN

35 mils

3e

80-Lead VQFN (11x11x0.9 mm)

HV7351K61933256 35 mils

3e

Example


HV7351

BA

0.15 C

0.15 C

0.10 C A B

(DATUM B)(DATUM A)

NOTE 1

2XTOP VIEW

SIDE VIEW

BOTTOM VIEW

For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging

Note:

NOTE 1

12

N

0.10 C A B

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-301A-8FX Sheet 1 of 2

80-Lead Plastic Quad Flat, No Lead Package (8FX) – 11x11x0.9 mm Body [VQFN]

2X

80X

D

E

12

N

e

80X L

80X K

E2

D2

80X b

(A3)A

CSEATING

PLANE

A1


HV7351


Note:

Dimension LimitsUnits

D

Overall Width

Overall LengthExposed Pad Length

Exposed Pad Width

Terminal Thickness

D2

E2E

9.70

MILLIMETERS

0.203 REF

MIN

(A3)

MAX

11.00 BSC

Terminal LengthTerminal Width

Lb

0.500.30

Notes:1.

KTerminal-to-Exposed Pad 0.20

NOM

BSC: Basic Dimension. Theoretically exact value shown without tolerances.3.2.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Standoff A1 -Overall Height A 0.85Pitch e 0.50 BSCNumber of Terminals N 80

0.300.18

9.50

0.000.80

0.250.40

-

9.6011.00 BSC

0.050.90

-

Pin 1 visual index feature may vary, but must be located within the hatched area.

Dimensioning and tolerancing per ASME Y14.5M.Package is saw singulated.

Microchip Technology Drawing C04-301A-8FX Sheet 2 of 2


9.709.50 9.60


HV7351

RECOMMENDED LAND PATTERN


Note:

Dimension LimitsUnits

C2

Optional Center Pad Width

Contact Pad Spacing

Optional Center Pad Length

Contact Pitch

Y2X2

9.709.70

MILLIMETERS

0.50 BSCMIN

EMAX

11.00

Contact Pad Length (X20)Contact Pad Width (X80)

Y1X1

0.800.30

Microchip Technology Drawing C04-2301A-8FX

NOM

SILK SCREEN

12

80

C1

C2

E

X1

Y1

G2

Y2

X2

C1Contact Pad Spacing 11.00

Contact Pad to Center Pad (X80) G2 0.20Thermal Via Diameter VThermal Via Pitch EV

0.331.200

ØV

EV

EV


G1

Contact Pad to Contact Pad (X76) G1 0.20

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss duringreflow process

1.

2.


HV7351

APPENDIX A: REVISION HISTORY

Revision B (October 2019)• Updated Figure 3-3.• Updated Table 3-2 and Table 3-3.

Revision A (June 2015)• Original Release of this Document.


HV7351

NOTES:


HV7351

PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. XX

PackageDevice

Device: HV7351: 8-Channel, ±70V, 3A Programmable High-Voltage Ultrasound-Transmit Beamformer

Package: K6 = 80-Lead Plastic Quad Flat, No Lead Package (8FX) – 11x11x0.9 mm Body (VQFN)

Environmental: G = Lead (Pb)-free/ROHS-compliant package

Examples:a) HV7351K6-G: Programmable High-Voltage

Ultrasound-Transmit Beamformer, 80-Lead 11x11 mm VQFN package

-X

Environmental


HV7351

NOTES:


Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2015-2019 Microchip Technology Inc.

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

TrademarksThe Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries.GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies.

© 2015-2019, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-5138-9

DS20005412B-page 27

www.microchip.com/qualitywww.microchip.com/quality


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.comAtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455Austin, TXTel: 512-257-3370 BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924DetroitNovi, MI Tel: 248-848-4000Houston, TX Tel: 281-894-5983IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380Los AngelesMission Viejo, CA Tel: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510New York, NY Tel: 631-435-6000San Jose, CA Tel: 408-735-9110Tel: 408-436-4270Canada - TorontoTel: 905-695-1980 Fax: 905-695-2078

ASIA/PACIFICAustralia - SydneyTel: 61-2-9868-6733China - BeijingTel: 86-10-8569-7000 China - ChengduTel: 86-28-8665-5511China - ChongqingTel: 86-23-8980-9588China - DongguanTel: 86-769-8702-9880 China - GuangzhouTel: 86-20-8755-8029 China - HangzhouTel: 86-571-8792-8115 China - Hong Kong SARTel: 852-2943-5100 China - NanjingTel: 86-25-8473-2460China - QingdaoTel: 86-532-8502-7355China - ShanghaiTel: 86-21-3326-8000 China - ShenyangTel: 86-24-2334-2829China - ShenzhenTel: 86-755-8864-2200 China - SuzhouTel: 86-186-6233-1526 China - WuhanTel: 86-27-5980-5300China - XianTel: 86-29-8833-7252China - XiamenTel: 86-592-2388138 China - ZhuhaiTel: 86-756-3210040

ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444 India - New DelhiTel: 91-11-4160-8631India - PuneTel: 91-20-4121-0141Japan - OsakaTel: 81-6-6152-7160 Japan - TokyoTel: 81-3-6880- 3770 Korea - DaeguTel: 82-53-744-4301Korea - SeoulTel: 82-2-554-7200Malaysia - Kuala LumpurTel: 60-3-7651-7906Malaysia - PenangTel: 60-4-227-8870Philippines - ManilaTel: 63-2-634-9065SingaporeTel: 65-6334-8870Taiwan - Hsin ChuTel: 886-3-577-8366Taiwan - KaohsiungTel: 886-7-213-7830Taiwan - TaipeiTel: 886-2-2508-8600 Thailand - BangkokTel: 66-2-694-1351Vietnam - Ho Chi MinhTel: 84-28-5448-2100

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829Finland - EspooTel: 358-9-4520-820France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - GarchingTel: 49-8931-9700Germany - HaanTel: 49-2129-3766400Germany - HeilbronnTel: 49-7131-72400Germany - KarlsruheTel: 49-721-625370Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44Germany - RosenheimTel: 49-8031-354-560Israel - Ra’anana Tel: 972-9-744-7705Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781Italy - PadovaTel: 39-049-7625286 Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340Norway - TrondheimTel: 47-7288-4388Poland - WarsawTel: 48-22-3325737 Romania - BucharestTel: 40-21-407-87-50Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91Sweden - GothenbergTel: 46-31-704-60-40Sweden - StockholmTel: 46-8-5090-4654UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service

05/14/19

http://support.microchip.comhttp://www.microchip.com

FeaturesApplicationsGeneral DescriptionTypical Application CircuitPackage Types (Top View)Block Diagram1.0 Electrical CharacteristicsAbsolute Maximum Ratings†TABLE 1-1: Operating Supply VoltagesTABLE 1-2: Regulator Outputs

Electrical CharacteristicsAC Electrical CharacteristicsTemperature SpecificationsTABLE 1-3: Logic Truth Table1.1 Timing DiagramsFIGURE 1-1: Timing Diagram of 3-Level, 1-Cycle Bipolar RTZ TX Pulse.FIGURE 1-2: Timing Diagram of 2-Level, 2-Cycle Bipolar non-RTZ TX Pulses with Damping.

2.0 Pin DescriptionTABLE 2-1: Pin Function Table

3.0 Device Description3.1 Loading Data into the Four 16/32-Bit Pattern RegistersFIGURE 3-1: Pattern Register Circuit Diagram.EXAMPLE 3-1:FIGURE 3-2: Waveform Pattern Register.TABLE 3-1: Decoder Truth Table

3.2 Loading Data into the Delay Counters and the Divide-by-N CounterFIGURE 3-3: Delay and Divide-by-N Registers.

3.3 10-Bit Delay CounterTABLE 3-2: Delay Counter

3.4 6-Bit Divide-by-N CounterTABLE 3-3: 6-Bit Divide-by-N Counter Register

4.0 Packaging Information4.1 Package Marking Information

Appendix A: Revision HistoryRevision B (October 2019)Revision A (June 2015)

Product Identification SystemWorldwide Sales and Service

hv7351 data sheet...2019/05/14 · 8-channel, ±70v, 3a programmable high-voltage...

Documents